Commit graph

374 commits

Author SHA1 Message Date
Simon Glass
78a10b6656 rockchip: pinctrl: Implement the get_gpio_mux() method
Implement this so that the GPIO command will be able to report whether a
GPIO is used for input or output.

Signed-off-by: Simon Glass <sjg@chromium.org>
2016-01-21 20:42:35 -07:00
Simon Glass
63c52648e4 rockchip: pinctrl: Reduce the size for SPL
This file has many features that are not needed by SPL. Use #ifdef to
remove the unused features and reduce the code size.

Signed-off-by: Simon Glass <sjg@chromium.org>
2016-01-21 20:42:35 -07:00
Simon Glass
77eaa19e73 dm: pinctrl: Add a way for a GPIO driver to obtain a pin function
GPIO drivers want to be able to show if a pin is enabled for input, output,
or is being used by another function. Some drivers can easily find this
and the code is included in the driver. For some SoCs this is more complex.
Conceptually this should be handled by pinctrl rather than GPIO. Most
pinctrl drivers will have this feature anyway.

Add a method by which a GPIO driver can obtain the pin mux value given a
GPIO reference. This avoids repeating the code in two places.

Signed-off-by: Simon Glass <sjg@chromium.org>
2016-01-21 20:42:35 -07:00
Simon Glass
bea705c993 rockchip: pinctrl: Add a full pinctrl driver
We can make use of the device tree to configure pinctrl settings. Add this
support for the driver so we can use it in U-Boot proper.

Signed-off-by: Simon Glass <sjg@chromium.org>
2016-01-21 20:42:35 -07:00
Simon Glass
a4275f5e52 rockchip: Convert the PMU IOMUX registers into an array
This is easier to deal with when using generic code since it allows us to
use a register index instead of naming each register.

Adjust it, adding an enum to improve readability.

Signed-off-by: Simon Glass <sjg@chromium.org>
2016-01-21 20:42:34 -07:00
Simon Glass
52db39a22b dm: pinctrl: Add a function to parse PIN_CONFIG flags
Add a function which produces a flags word from a few common PIN_CONFIG
settings. This is useful for simple pinctrl drivers that don't need to worry
about drive strength, etc.

Signed-off-by: Simon Glass <sjg@chromium.org>
2016-01-21 20:42:34 -07:00
Jeffy Chen
9d19e5d3da rockchip: rk3036: Bind GPIO banks
Call dm_scan_fdt_node() in rk3036 pinctrl uclass binding.

Signed-off-by: Jeffy Chen <jeffy.chen@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
2016-01-21 20:04:04 -07:00
Simon Glass
5589a81829 pinctrl: Avoid binding all pinconfig nodes before relocation
This can create a large number of pinctrl devices. It chews up early
malloc() memory and takes time. Only bind those which are marked as needed
before relocation.

Signed-off-by: Simon Glass <sjg@chromium.org>
2016-01-20 19:06:22 -07:00
huang lin
49ecaa928f rockchip: rk3036: Add pinctrl driver
Add a driver which support pin multiplexing setup for rk3036

Signed-off-by: Lin Huang <hl@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-12-01 08:07:22 -07:00
Tom Rini
da58dec866 Various Makefiles: Add SPDX-License-Identifier tags
After consulting with some of the SPDX team, the conclusion is that
Makefiles are worth adding SPDX-License-Identifier tags too, and most of
ours have one.  This adds tags to ones that lack them and converts a few
that had full (or in one case, very partial) license blobs into the
equivalent tag.

Cc: Kate Stewart <kstewart@linuxfoundation.org>
Signed-off-by: Tom Rini <trini@konsulko.com>
2015-11-10 09:19:52 -05:00
Masahiro Yamada
8497ccc4c2 ARM: uniphier: rename CONFIG_MACH_* to CONFIG_ARCH_UNIPHIER_*
I want these prefixed with CONFIG_ARCH_UNIPHIER_ to clarify
they belong to UniPhier SoC family.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2015-09-25 00:27:53 +09:00
Masahiro Yamada
080b7a5b45 pinctrl: uniphier: add UniPhier PH1-LD6b pinctrl driver
Add pin configuration and pinmux support for UniPhier PH1-LD6b SoC.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2015-09-25 00:27:47 +09:00
Masahiro Yamada
833de5fafb pinctrl: uniphier: add UniPhier ProXstream2 pinctrl driver
Add pin configuration and pinmux support for UniPhier ProXstream2
SoC.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2015-09-25 00:26:27 +09:00
Masahiro Yamada
b82ca82ed2 pinctrl: uniphier: add UniPhier PH1-Pro5 pinctrl driver
Add pin configuration and pinmux support for UniPhier PH1-Pro5 SoC.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2015-09-25 00:25:29 +09:00
Masahiro Yamada
06b2ae5890 pinctrl: uniphier: add UniPhier PH1-sLD8 pinctrl driver
Add pin configuration and pinmux support for UniPhier PH1-sLD8 SoC.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2015-09-25 00:24:30 +09:00
Masahiro Yamada
a343812461 pinctrl: uniphier: add UniPhier PH1-Pro4 pinctrl driver
Add pin configuration and pinmux support for UniPhier PH1-Pro4 SoC.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2015-09-25 00:23:15 +09:00
Masahiro Yamada
e4410e8207 pinctrl: uniphier: add UniPhier PH1-LD4 pinctrl driver
Add pin configuration and pinmux support for UniPhier PH1-LD4 SoC.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2015-09-25 00:21:13 +09:00
Masahiro Yamada
5dc626f836 pinctrl: uniphier: add UniPhier pinctrl core support
The core support for the pinctrl drivers for all the UniPhier SoCs.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2015-09-23 23:21:32 +09:00
Masahiro Yamada
8a5f6129d1 pinctrl: move dm_scan_fdt_node() out of pinctrl uclass
Commit c5acf4a2b3 ("pinctrl: Add the concept of peripheral IDs")
added some additional change that was not mentioned in the git-log.

That commit added dm_scan_fdt_node() in the pinctrl uclass binding.
It should be handled by the simple-bus driver or the low-level
driver, not by the pinctrl framework.

I guess Simon's motivation was to bind GPIO banks located under the
Rockchip pinctrl device.  It is true some chips have sub-devices
under their pinctrl devices, but it is basically SoC-specific matter.

This commit partly reverts commit c5acf4a2b3 to keep the only
pinctrl-generic features in the uclass.  The dm_scan_fdt_node()
should be called from the rk3288_pinctrl driver.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
2015-09-19 15:42:15 -06:00
Simon Glass
bb4e4a5d96 rockchip: rk3288: Add pinctrl driver
Add a driver which supports pin multiplexing setup for the most commonly
used peripherals.

Signed-off-by: Simon Glass <sjg@chromium.org>
2015-09-02 21:28:24 -06:00
Simon Glass
c5acf4a2b3 pinctrl: Add the concept of peripheral IDs
My original pinctrl patch operating using a peripheral ID enum. This was
shared between pinmux and clock and provides an easy way to specify a device
that needs to be controlled, even it is does not (yet) have a driver within
driver model.

Masahiro's new simple pinctrl gets around this by providing a
set_state_simple() pinctrl method. By passing a device to that call the
peripheral ID becomes unnecessary. If the driver needs it, it can calculate
it itself and use it internally.

However this does not solve the problem for peripheral clocks. The 'pure'
solution would be to pass a driver to the clock uclass also. But this
requires that all devices should have a driver, and a struct udevide. Also
a key optimisation of the clock uclass is allowing a peripheral clock to
be set even when there is no device for that clock.

There may be a better way to achive the same goal, but for now it seems
expedient to add in peripheral ID to the pinctrl uclass. Two methods are
added - one to get the peripheral ID and one to select it. The existing
set_state_simple() is effectively the union of these.

Signed-off-by: Simon Glass <sjg@chromium.org>
2015-09-02 21:28:22 -06:00
Simon Glass
458a070076 pinctrl: Add help text to Kconfig
The pinctrl Kconfig options should have help messages. Add this to a few
options.

Signed-off-by: Simon Glass <sjg@chromium.org>
2015-09-02 21:28:22 -06:00
Masahiro Yamada
9c6a3c6772 pinctrl: sandbox: add sandbox pinctrl driver
This driver actually does nothing but test pinctrl uclass, and
demonstrate how things work.

To try this driver, uncomment /* #define DEBUG */ in the
drivers/pinctrl/pinctrl-sandbox.c, and debug messages will be
displayed.

  DRAM:  128 MiB
  sandbox pinmux: group = 1 (serial_a), function = 1 (serial)
  Using default environment

  In:    cros-ec-keyb
  Out:   lcd
  Err:   lcd
  Net:   Net Initialization Skipped
  eth0: eth@10002000, eth1: eth@80000000, eth5: eth@90000000
  => i2c dev 0
  Setting bus to 0
  sandbox pinmux: group = 0 (i2c), function = 0 (i2c)
  sandbox pinconf: group = 0 (i2c), param = 3, arg = 1

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-08-31 07:57:29 -06:00
Masahiro Yamada
d90a5a30de pinctrl: add pin control uclass support
This creates a new framework for handling of pin control devices,
i.e. devices that control different aspects of package pins.

This uclass handles pinmuxing and pin configuration; pinmuxing
controls switching among silicon blocks that share certain physical
pins, pin configuration handles electronic properties such as pin-
biasing, load capacitance etc.

This framework can support the same device tree bindings, but if you
do not need full interface support, you can disable some features to
reduce memory foot print.  Typically around 1.5KB is necessary to
include full-featured uclass support on ARM board (CONFIG_PINCTRL +
CONFIG_PINCTRL_FULL + CONFIG_PINCTRL_GENERIC + CONFIG_PINCTRL_PINMUX),
for example.

We are often limited on code size for SPL.  Besides, we still have
many boards that do not support device tree configuration.  The full
pinctrl, which requires OF_CONTROL, does not make sense for those
boards.  So, this framework also has a Do-It-Yourself (let's say
simple pinctrl) interface.  With CONFIG_PINCTRL_FULL disabled, the
uclass itself provides no systematic mechanism for identifying the
peripheral device, applying pinctrl settings, etc.  They must be
done in each low-level driver.  In return, you can save much memory
footprint and it might be useful especially for SPL.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-08-31 07:57:29 -06:00