Fix:
mpc8568mds.c: In function 'local_bus_init':
mpc8568mds.c:150:7: warning: variable 'lbc_hz' set but not used [-Wunused-but-set-variable]
mpc8568mds.c: In function 'pib_init':
mpc8568mds.c:271:11: warning: variable 'orig_i2c_bus' set but not used [-Wunused-but-set-variable]
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
The top level Makefile does not do any recursion into subdirs when
cleaning, so these clean/distclean targets in random arch/board dirs
never get used. Punt them all.
MAKEALL didn't report any errors related to this that I could see.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
The function fsl_setup_hose clears the variable pci1_hose.
Set pci1_hose.config_table after it.
Signed-off-by: Zhao Chenhui <chenhui.zhao@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Move fsl_ddr_get_spd into common mpc8xxx/ddr/main.c as most boards
pretty much do the same thing. The only variations are in how many
controllers or DIMMs per controller exist. To make this work we
standardize on the names of the SPD_EEPROM_ADDRESS defines based on the
use case of the board.
We allow boards to override get_spd to either do board specific fixups
to the SPD data or deal with any unique behavior of how the SPD eeproms
are wired up.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Every 85xx board implements fsl_ddr_get_mem_data_rate via get_ddr_freq()
and every 86xx board uses get_bus_freq(). If implement get_ddr_freq()
as a static inline to call get_bus_freq() we can remove
fsl_ddr_get_mem_data_rate altogether and just call get_ddr_freq()
directly.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Remove duplicated code in MPC8568MDS board and utilize the common
fsl_pcie_init_board(). We also now dynamically setup the LAWs for PCI
controllers based on which PCIe controllers are enabled.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Add spaces to cause the informational prints to line up with
the ones from init_func_ram() in board.c. Output now looks like
this:
....
DRAM: Detected 4096 MB of memory
This U-Boot only supports < 4G of DDR
You could rebuild it with CONFIG_PHYS_64BIT
DDR: 2 GiB (DDR2, 64-bit, CL=5, ECC off)
....
The prints from lbc_sdram_init() have also been modified to line
line up and changed to start with "LBC SDRAM" instead of the
confusing "SDRAM".
Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
sdram_init() is used to initialize sdram on the lbc. Rename it
accordingly.
Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Correct initdram to use phys_size_t to represent the size of
dram; instead of changing this all over the place, and correcting
all the other random errors I've noticed, create a
common initdram that is used by all non-corenet 85xx parts. Most
of the initdram() functions were identical, with 2 common differences:
1) DDR tlbs for the fixed_sdram case were set up in initdram() on
some boards, and were part of the tlb_table on others. I have
changed them all over to the initdram() method - we shouldn't
be accessing dram before this point so they don't need to be
done sooner, and this seems cleaner.
2) Parts that require the DDR11 erratum workaround had different
implementations - I have adopted the version from the Freescale
errata document. It also looks like some of the versions were
buggy, and, depending on timing, could have resulted in the
DDR controller being disabled. This seems bad.
The xpedite boards had a common/fsl_8xxx_ddr.c; with this
change only the 517 board uses this so I have moved the ddr code
into that board's directory in xpedite517x.c
Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org>
Tested-by: Paul Gortmaker <paul.gortmaker@windriver.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Now that we have serdes support for all 85xx/86xx/Pxxx chips we can
replace the is_fsl_pci_cfg() code with the is_serdes_configured().
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Before this commit, weak symbols were not overridden by non-weak symbols
found in archive libraries when linking with recent versions of
binutils. As stated in the System V ABI, "the link editor does not
extract archive members to resolve undefined weak symbols".
This commit changes all Makefiles to use partial linking (ld -r) instead
of creating library archives, which forces all symbols to participate in
linking, allowing non-weak symbols to override weak symbols as intended.
This approach is also used by Linux, from which the gmake function
cmd_link_o_target (defined in config.mk and used in all Makefiles) is
inspired.
The name of each former library archive is preserved except for
extensions which change from ".a" to ".o". This commit updates
references accordingly where needed, in particular in some linker
scripts.
This commit reveals board configurations that exclude some features but
include source files that depend these disabled features in the build,
resulting in undefined symbols. Known such cases include:
- disabling CMD_NET but not CMD_NFS;
- enabling CONFIG_OF_LIBFDT but not CONFIG_QE.
Signed-off-by: Sebastien Carlier <sebastien.carlier@gmail.com>
Clean up Makefile, and drop a lot of the config.mk files on the way.
We now also automatically pick all boards that are listed in
boards.cfg (and with all configurations), so we can drop the redundant
entries from MAKEALL to avoid building these twice.
Signed-off-by: Wolfgang Denk <wd@denx.de>
The change is currently needed to be able to remove the board
configuration scripting from the top level Makefile and replace it by
a simple, table driven script.
Moving this configuration setting into the "CONFIG_*" name space is
also desirable because it is needed if we ever should move forward to
a Kconfig driven configuration system.
Signed-off-by: Wolfgang Denk <wd@denx.de>
Previously we used an alias the pci node to determine which node to
fixup or delete. Now we use the new fdt_node_offset_by_compat_reg to
find the node to update.
Additionally, we replace the code in each board with a single macro call
that makes assumes uniform naming and reduces duplication in this area.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Currently, 83xx, 86xx, and 85xx have a lot of duplicated code
dedicated to defining and manipulating the LBC registers. Merge
this into a single spot.
To do this, we have to decide on a common name for the data structure
that holds the lbc registers - it will now be known as fsl_lbc_t, and we
adopt a common name for the immap layouts that include the lbc - this was
previously known as either im_lbc or lbus; use the former.
In addition, create accessors for the BR/OR regs that use in/out_be32
and use those instead of the mismash of access methods currently in play.
I have done a successful ppc build all and tested a board or two from
each processor family.
Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org>
Acked-by: Kim Phillips <kim.phillips@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
When referring to PCIe and USB 'endpoint' is the standard naming
convention.
Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
Acked-by: Stefan Roese <sr@denx.de>
Acked-by: Remy Bohmer <linux@bohmer.net>
Use new fsl_pci_init_port() that reduces amount of duplicated code in the
board ports, use IO accessors and clean up printing of status info.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Refactor the code into a simple bitmask lookup table that determines if
a given PCI controller is enabled and if its in host/root-complex or
agent/end-point mode.
Each processor in the PQ3/MPC86xx family specified different encodings
for the cfg_host_agt[] and cfg_IO_ports[] boot strapping signals.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
There are really no differences between all the 85xx linker scripts so
we can just move to a single common one. Board code is still able to
override the common one if need be.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
For historic reasons we had defined some additional PLATFORM_CPPFLAGS
like:
PLATFORM_CPPFLAGS += -DCONFIG_E500=1
PLATFORM_CPPFLAGS += -DCONFIG_MPC85xx=1
PLATFORM_CPPFLAGS += -DCONFIG_MPC8548=1
However these are all captured in the config.h and thus redudant.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Every platform that calls fsl_pci_init calls fsl_pci_setup_inbound_windows
before it calls fsl_pci_init. There isn't any reason to just call it
from fsl_pci_init and simplify things a bit.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Every platform that calls fsl_pci_init calls pci_setup_indirect before
it calls fsl_pci_init. There isn't any reason to just call it from
fsl_pci_init and simplify things a bit.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Rename the pci header for FSL HW so we can move some prototypes
in there and stop doing explicit externs
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
A recent gcc added a new unaligned rodata section called '.rodata.str1.1',
which needs to be added the the linker script. Instead of just adding this
one section, we use a wildcard ".rodata*" to get all rodata linker section
gcc has now and might add in the future.
However, '*(.rodata*)' by itself will result in sub-optimal section
ordering. The sections will be sorted by object file, which causes extra
padding between the unaligned rodata.str.1.1 of one object file and the
aligned rodata of the next object file. This is easy to fix by using the
SORT_BY_ALIGNMENT command.
This patch has not be tested one most of the boards modified. Some boards
have a linker script that looks something like this:
*(.text)
. = ALIGN(16);
*(.rodata)
*(.rodata.str1.4)
*(.eh_frame)
I change this to:
*(.text)
. = ALIGN(16);
*(.eh_frame)
*(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
This means the start of rodata will no longer be 16 bytes aligned.
However, the boundary between text and rodata/eh_frame is still aligned to
16 bytes, which is what I think the real purpose of the ALIGN call is.
Signed-off-by: Trent Piepho <xyzzy@speakeasy.org>
Introduce a new define to seperate out the virtual address that PCI
memory is at from the physical address. In most situations these are
mapped 1:1. However any code accessing the bus should use VIRT.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Acked-by: Andy Fleming <afleming@freescale.com>
Use the _MEM_PHYS defines instead of _MEM_BUS for LAW and real address fields
of TLBs. This is what we should have always been using from the start.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Acked-by: Andy Fleming <afleming@freescale.com>
Use CONFIG_SYS_PCI*_IO_BUS for the bus relative address instead
of _IO_BASE so we are more explicit.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Use CONFIG_SYS_{PCI,RIO}_MEM_BUS for the bus relative address instead
of _MEM_BASE so we are more explicit.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Acked-by: Andy Fleming <afleming@freescale.com>
On newer CPUs, 8536, 8572, and 8610, the CLKDIV field of LCRR is five bits
instead of four.
In order to avoid an ifdef, LCRR_CLKDIV is set to 0x1f on all systems. It
should be safe as the fifth bit was defined as reserved and set to 0.
Code that was using a hard coded 0x0f is changed to use LCRR_CLKDIV.
Signed-off-by: Trent Piepho <tpiepho@freescale.com>
Acked-by: Kumar Gala <galak@kernel.crashing.org>
Acked-by: Jon Loeliger <jdl@freescale.com>
The DDR controller of 8548/8544/8568/8572/8536 processors
have the ECC data init feature, and the new DDR code is
using the feature, and we don't need the way with DMA to
init memory any more.
Signed-off-by: Dave Liu <daveliu@freescale.com>
Acked-by: Andy Fleming <afleming@freescale.com>
Converted ATUM8548, MPC8536DS, MPC8544DS, MPC8548CDS, MPC8568MDS,
MPC8572DS, TQM85xx, and SBC8548 to use fsl_pci_setup_inbound_windows()
and ft_fsl_pci_setup().
With these changes the board code is a bit smaller and we get dma-ranges
set in the device tree for these boards.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Signed-off-by: Andrew Fleming-AFLEMING <afleming@freescale.com>
Because some dimm parameters like n_ranks needs to be used with the board
frequency to choose the board parameters like clk_adjust etc. in the
board_specific_paramesters table of the board ddr file, we need to pass
the dimm parameters to the board file.
* move ddr dimm parameters header file from /cpu to /include directory.
* add ddr dimm parameters to populate board specific options.
* Fix fsl_ddr_board_options() for all the 8xxx boards which call this function.
Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
The recent change to move the .bss outside of the image gives older
binutils (ld from eldk4.1/binutils-2.16) some headache:
ppc_85xx-ld: u-boot: Not enough room for program headers (allocated 3, need 4)
ppc_85xx-ld: final link failed: Bad value
We workaround it by being explicit about the program headers and not
assigning the .bss to a program header.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* Move to using absolute addressing always. Makes the scripts a bit more
portable and common
* Moved .bss after the end of the image. These allows us to have more
room in the resulting binary image for code and data.
* Removed .text object files that aren't really needed
* Make sure _end is 4-byte aligned as the .bss init code expects this.
(Its possible that the end of .bss isn't 4-byte aligned)
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
This patch changes the return type of initdram() from long int to phys_size_t.
This is required for a couple of reasons: long int limits the amount of dram
to 2GB, and u-boot in general is moving over to phys_size_t to represent the
size of physical memory. phys_size_t is defined as an unsigned long on almost
all current platforms.
This patch *only* changes the return type of the initdram function (in
include/common.h, as well as in each board's implementation of initdram). It
does not actually modify the code inside the function on any of the platforms;
platforms which wish to support more than 2GB of DRAM will need to modify
their initdram() function code.
Build tested with MAKEALL for ppc, arm, mips, mips-el. Booted on powerpc
MPC8641HPCN.
Signed-off-by: Becky Bruce <becky.bruce@freescale.com>
With the new LAW interface (set_next_law) we can move to letting the
system allocate which LAWs are used for what purpose. This makes life
a bit easier going forward with the new DDR code.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Signed-off-by: Andy Fleming <afleming@freescale.com>
Acked-by: Jon Loeliger <jdl@freescale.com>
Acked-by: Becky Bruce <becky.bruce@freescale.com>
Remove unused and unconfigured DDR test code from FSL 85xx boards.
Besides, other common code exists.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
This commit gets rid of a huge amount of silly white-space issues.
Especially, all sequences of SPACEs followed by TAB characters get
removed (unless they appear in print statements).
Also remove all embedded "vim:" and "vi:" statements which hide
indentation problems.
Signed-off-by: Wolfgang Denk <wd@denx.de>
The cross compiler is responsible for providing the correct libraries
and the logic to find the linking libraries.
Signed-off-by: Jason Wessel <jason.wessel@windriver.com>
Each file that can be built here now follows some
CONFIG_ option so that they are appropriately built
or not, as needed. And CONFIG_ defines were added
to various board config files to make sure that happens.
The other board/freescale/*/Makefiles no longer need
to reach up and over into ../common to build their
individually needed files any more.
Boards that are CDS specific were renamed with cds_ prefix.
Signed-off-by: Jon Loeliger <jdl@freescale.com>
When we go to 36-bit physical addresses we need to keep the concept of
the physical CCSRBAR address seperate from the virtual one.
For the majority of boards CFG_CCSBAR_PHYS == CFG_CCSRBAR
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Many of the spd.h #includers don't need it,
and wanted to have spd_sdram() declared instead.
Since they didn't get that, some also had open
coded extern declarations of it instead or as well.
Fix it all up by using spd_sdram.h where needed.
Signed-off-by: Jon Loeliger <jdl@freescale.com>
