Commit graph

2380 commits

Author SHA1 Message Date
Kishon Vijay Abraham I
4564faeafb ti: dwc3: Enable clocks in enable_basic_clocks() in hw_data.c
Commit d3cfcb3 (ARM: DRA7: Enable clocks for USB OTGSS and USB PHY)
changed the member names of prcm_regs from cm_l3init_usb_otg_ss_clkctrl
to cm_l3init_usb_otg_ss1_clkctrl and from cm_coreaon_usb_phy_core_clkctrl
to cm_coreaon_usb_phy1_core_clkctrl in order to differentiate between
the two dwc3 controllers present in dra7xx/am43xx and enabled these
clocks in enable_basic_clocks() in hw_data.c. However these clocks
continued to be enabled in board files/driver files for dwc3 host
mode functionality causing compilation break with few configs.

Fixed it here by making all the clocks enabled in enable_basic_clocks()
and removing it from board files/driver files here.

Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2015-04-16 15:08:36 -04:00
Tom Rini
20913018fb Merge branch 'master' of http://git.denx.de/u-boot-sunxi 2015-04-16 12:51:23 -04:00
Hans de Goede
a0e2b1b865 sunxi: usbc: Wait for vbus to fall after disabling it
When u-boot boots the board may be powering vbus, we turn off vbus in
sunxi_usbc_request_resources, if we are too quick with reading vusb-detect
after this we may see a residual charge and assume we've an external vusb
connected even though we do not. So when we see an external vusb wait a bit
and try again.

Without this when dealing with a pmic controller vbus and doing "reset" on
the u-boot console the musb host will only init once every other boot, because
the other boot it thinks an external vbus is present, this commit fixes this.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
2015-04-15 16:17:17 +02:00
Hans de Goede
046ea8b390 sunxi: usbc: Initialize vusb value on request_resources
On boards which use the pmic to enable/disable vbus on the otg port, the
vbus value is not reset to 0 on reset, as reset only resets the SoC and not
the pmic, so explicitly set vbus to 0 on init (request_resources) by moving
the gpio_direction_output call into request_resources.

For consistency also move the gpio_direction_input call for vbus-detect into
request_resources.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
2015-04-15 16:17:17 +02:00
Paul Kocialkowski
487b3277d4 sunxi: GPIO pin mux hardware-feature-specific function index defines
Each hardware feature exposed through the GPIO pin mux is usually using the same
function index (for a given port), so there is no need to define one value per
pin: one value per hardware feature per port is sufficient, avoids duplication
and makes everything easier to understand.

Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
Acked-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
2015-04-15 16:17:17 +02:00
Paul Kocialkowski
ebd468b2d2 sunxi: common VBUS detection logic in usbc
VBUS detection could be needed not only by the musb code (to prevent host mode),
but also by e.g. gadget drivers to start only when a cable is connected.

In addition, this allows more flexibility in vbus detection, as it could easily
be extended to other USBC indexes. Eventually, this would help making musb
support independent from a hardcoded USB controller index (0).

Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
Acked-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
2015-04-15 16:17:17 +02:00
Paul Kocialkowski
5eaacb4340 sunxi: usb: Drop AXP-sepcific VBUS detection and drive logic
VBUS detection and enable is now be used with virtual AXP GPIOs, so all the USB
code has to use GPIO in every case and let sunxi_gpio do the heavy lifting.

Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
Acked-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
2015-04-15 16:17:17 +02:00
Kishon Vijay Abraham I
fc2f15d2f7 ARM: AM43xx: Enable clocks for USB OTGSS and USB PHY
Enabled clocks for dwc3 controller and USB PHY present in AM43xx.

Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Reviewed-by: Lukasz Majewski <l.majewski@samsung.com>
2015-04-14 05:48:08 +02:00
Kishon Vijay Abraham I
d3cfcb3e2c ARM: DRA7: Enable clocks for USB OTGSS and USB PHY
Enabled clocks for dwc3 controller and USB PHY present in DRA7.

Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Reviewed-by: Lukasz Majewski <l.majewski@samsung.com>
2015-04-14 05:48:08 +02:00
Tom Rini
1d2f74690c Merge branch 'master' of git://www.denx.de/git/u-boot-imx 2015-04-13 10:52:46 -04:00
Stefan Roese
4adb46a314 arm: armada-xp: Fix SPL for AXP by using save_boot_params_ret
Patch e11c6c27 (arm: Allow lr to be saved by board code) introduced
a different method to return from save_boot_params(). The SPL support
for AXP has been pulled and changing to this new method is now
required for SPL to work correctly.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Cc: Luka Perkov <luka.perkov@sartura.hr>
2015-04-11 11:49:00 +02:00
Albert ARIBAUD \(3ADEV\)
412ae53aad lpc32xx: add support for board work_92105
Work_92105 from Work Microwave is an LPC3250-
based board with the following features:
- 64MB or 128MB SDR DRAM
- 1 GB SLC NAND, managed through MLC controller.
- Ethernet
- Ethernet + PHY SMSC8710
- I2C:
  - EEPROM (24M01-compatible)
  - RTC (DS1374-compatible)
  - Temperature sensor (DS620)
  - DACs (2 x MAX518)
- SPI (through SSP interface)
  - Port expander MAX6957
- LCD display (HD44780-compatible), controlled
  through the port expander and DACs

This board has SPL support, and uses the LPC32XX boot
image format.

Signed-off-by: Albert ARIBAUD (3ADEV) <albert.aribaud@3adev.fr>
2015-04-10 14:23:39 +02:00
Albert ARIBAUD \(3ADEV\)
981219eebe lpc32xx: add LPC32xx SSP support (SPI mode)
Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
Signed-off-by: Albert ARIBAUD (3ADEV) <albert.aribaud@3adev.fr>
2015-04-10 14:23:20 +02:00
Albert ARIBAUD \(3ADEV\)
606f704760 lpc32xx: add GPIO support
This driver only supports Driver Model, not legacy model.

Signed-off-by: Albert ARIBAUD (3ADEV) <albert.aribaud@3adev.fr>
2015-04-10 14:23:09 +02:00
Albert ARIBAUD \(3ADEV\)
5e862b9539 lpc32xx: i2c: add LPC32xx I2C interface support
Signed-off-by: Albert ARIBAUD (3ADEV) <albert.aribaud@3adev.fr>
2015-04-10 14:23:07 +02:00
Albert ARIBAUD \(3ADEV\)
c8381bf435 lpc32xx: mtd: nand: add MLC NAND controller
The controller's Reed-Solomon ECC hardware is
used except of course for raw reads and writes.
It covers in- and out-of-band data together.

The SPL framework is supported.

Signed-off-by: Albert ARIBAUD (3ADEV) <albert.aribaud@3adev.fr>
2015-04-10 14:22:56 +02:00
Albert ARIBAUD \(3ADEV\)
ac2916a224 lpc32xx: add Ethernet support
Signed-off-by: Albert ARIBAUD (3ADEV) <albert.aribaud@3adev.fr>
2015-04-10 14:22:48 +02:00
Albert ARIBAUD
b491d9757d Merge branch 'u-boot/master' 2015-04-10 14:22:23 +02:00
Andrej Rosano
3bf801a217 ARM: mx5: add support for USB armory board
Add support for Inverse Path USB armory board, an open source
flash-drive sized computer based on Freescale i.MX53 SoC.

http://inversepath.com/usbarmory

Signed-off-by: Andrej Rosano <andrej@inversepath.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Chris Kuethe <chris.kuethe@gmail.com>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: Vagrant Cascadian <vagrant@debian.org>
Tested-By: Vagrant Cascadian <vagrant@debian.org>
Tested-by: Chris Kuethe <chris.kuethe@gmail.com>
2015-04-09 09:14:12 +02:00
Andrej Rosano
424ee3d157 ARM: mx5: move to a standard arch/board approach
Move the MX5 based boards to arch/arm/cpu/armv7/mx5, following the
commit: 89ebc82137

Signed-off-by: Andrej Rosano <andrej@inversepath.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Vagrant Cascadian <vagrant@debian.org>
Tested-by: Chris Kuethe <chris.kuethe@gmail.com>
2015-04-09 09:13:54 +02:00
Tom Rini
e049b772ae am33xx/ddr.c: Fix regression on DDR2 platforms
Back in fc46bae a "clean up" was introduced that intended to reconcile
some of the AM335x codepaths based on how AM43xx operates.
Unfortunately this introduced a regression on the DDR2 platforms.  This
was un-noticed on DDR3 (everything except for Beaglebone White) as we
had already populated sdram_config correctly in sequence.  This change
brings us back to the older behavior and is fine on all platforms.

Tested on Beaglebone White, Beaglebone Black and AM335x GP EVM

Reported-by: Matt Ranostay <mranostay@gmail.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
2015-04-07 08:41:10 -04:00
Ajay Kumar
6102560891 Exynos5: Fix rpll_sdiv to support both peach-pit and peach-pi panels
The existing setting for rpll_sdiv generates 70.5Mhz RPLL
video clock to drive 1366x768 panel on peach_pit.

This clock rate is not sufficient to drive 1920x1080 panel on peach-pi.
So, we adjust rpll_sdiv to 3 so that it generates 141Mhz pixel clock
which can drive peach-pi LCD.

This change doesn't break peach-pit LCD since 141/2=70.5Mhz, i.e FIMD
divider at IP level will get set to 1(the required divider setting
will be calculated and set by exynos_fimd_set_clock()) and hence
peach-pit LCD still works fine.

Signed-off-by: Ajay Kumar <ajaykumar.rs@samsung.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2015-04-06 14:34:40 +09:00
Ajay Kumar
70b4fb660d arm: exynos: add display clocks for Exynos5800
Add get_lcd_clk and set_lcd_clk callbacks for Exynos5800 needed by
exynos video driver.

Signed-off-by: Ajay Kumar <ajaykumar.rs@samsung.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2015-04-06 14:34:40 +09:00
Guillaume GARDET
0467faf555 Exynos: Clock: Fix exynos5_get_periph_rate for I2C.
Commit 2e82e92526 'Exynos: Clock: Cleanup
soc_get_periph_rate' introduced a bug in I2C config. This patch makes cros_ec
keyboard working again on Samsung Chromebook (snow).

Changes in V2: reorder lines as requested by Joonyoung Shim.

Signed-off-by: Guillaume GARDET <guillaume.gardet@free.fr>
Cc: Akshay Saraswat <akshay.s@samsung.com>
Cc: Minkyu Kang <mk7.kang@samsung.com>
Cc: Joonyoung Shim <jy0922.shim@samsung.com>
Reviewed-by: Simon Glass <sjg@chroimum.org>
Tested-by: Simon Glass <sjg@chroimum.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2015-04-06 14:05:45 +09:00
Tom Rini
692e5c4e7e Merge branch 'master' of git://git.denx.de/u-boot-tegra
Conflicts:
	board/armltd/vexpress64/vexpress64.c

Signed-off-by: Tom Rini <trini@konsulko.com>
2015-04-03 09:14:38 -04:00
Tom Rini
9da7e3daf3 Merge branch 'master' of git://git.denx.de/u-boot-imx 2015-03-31 11:45:36 -04:00
Stephen Warren
0edb3a8ec9 ARM: tegra: pinctrl: move Tegra210 code to the correct dir
Patches that added the Tegra210 pinctrl driver and renamed directories
arch/arm/cpu/tegra{$soc}-common -> arch/arm/mach-tegra/tegra-${soc}
crossed. Move the Tegra210 pinctrl driver to the correct location. This
wasn't detected since Tegra210 support is in the process of being added,
and isn't buildable yet.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2015-03-30 09:54:06 -07:00
Iain Paton
e71b422bd7 sunxi: use CONFIG_SYS_CLK_FREQ to set cpu clock
make the CPU clock selectable via Kconfig

this removes the sunxi specific CONFIG_CLK_FULL_SPEED defined in each
soc header and replaces it's use in board/sunxi/board.c with
CONFIG_SYS_CLK_FREQ from Kconfig which allows us to configure board
specific frequency on boot

Signed-off-by: Iain Paton <ipaton0@gmail.com>
[hdegoede@redhat.com s/CONFIG_SYS_CLK_FREQ/CONFIG_TIMER_CLK_FREQ/ for the
 arch-timer clk speed on sun7i to fix mis-compile on sun7i]
Acked-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
2015-03-29 13:36:03 +02:00
Iain Paton
7a140117ef sunxi: sun4i: improve cpu clock selection method
clock_set_pll1 would pick the next highest available cpu clock speed if
a value not in the pre defined table was selected. this potentially
results in overclocking the soc.

reverse the selection method so that we select the next lowest speed
and add the missing 912Mhz setting that's requested by sun7i which also
uses the sun4i clock code.

Signed-off-by: Iain Paton <ipaton0@gmail.com>
Acked-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
2015-03-29 13:08:39 +02:00
Hans de Goede
246e3b8787 sunxi: musb: Fix some lo speed devices not working with musb host
The usb0 / otg phy on sunxi boards has a bug where it wrongly detects a
high speed squelch on usb reset deassert when a lo speed device is plugged in.

The android kernel has a work around for this in the form of temporary
disabling the phy's squelch detection on reset deassert, this commit adds
the same workaround to the u-boot sunxi musb code, thereby fixing various usb
lo speed devices not working.

Tested with a (before non working) usb keyboard and a usb 2.4 GHz wireless
keyboard/mouse combo receiver.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
2015-03-29 12:58:59 +02:00
Masahiro Yamada
ddf6bd4876 ARM: bcm283x: merge BCM2835/BCM2836 directories into mach-bcm283x
BCM2835 (used on Raspberry Pi) and BCM2836 (used on Raspberry Pi 2)
are similar enough.  One of the biggest differences is the ARM
processor.  It is reasonable to collect the source files into a
single place, arch/arm/mach-bcm283x/.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Acked-by: Stephen Warren <swarren@wwwdotorg.org>
2015-03-28 09:03:09 -04:00
Masahiro Yamada
326a682358 malloc_f: enable SYS_MALLOC_F by default if DM is on
This option has a bool type, not hex.
Fix it and enable it if CONFIG_DM is on because Driver Model always
requires malloc memory.  Devices are scanned twice, before/after
relocation.  CONFIG_SYS_MALLOC_F should be enabled to use malloc
memory before relocation.  As it is board-independent, handle it
globally.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Acked-by: Stephen Warren <swarren@wwwdotorg.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Acked-by: Robert Baldyga <r.baldyga@samsung.com>
2015-03-28 09:03:09 -04:00
Masahiro Yamada
91405b7fa9 malloc_f: remove redundant defalut values of CONFIG_SYS_MALLOC_F_LEN
The default value of CONFIG_SYS_MALLOC_F_LEN is defined by ./Kconfig
as 0x400.  Each defconfig or Kconfig need not repeat the same value.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Acked-by: Stephen Warren <swarren@wwwdotorg.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Acked-by: Robert Baldyga <r.baldyga@samsung.com>
2015-03-28 09:03:08 -04:00
Masahiro Yamada
79d75d7527 ARM: move -march=* and -mtune= options to arch/arm/Makefile
My main motivations for this commit are:

[1] Follow the arch/arm/Makefile style of Linux Kernel

[2] Maintain compiler options systematically
  Currently, we give -march=* and -mtune=* options inconsistently:
  Only some of the CPUs pass -march=* and -mtune=* options.
  By collecting such options into the single place arch/arm/Makefile
  we can tell which options are missing at a glance.

[3] Prepare for deprecating arch/*/cpu/*/config.mk

Note:
  This commit just moves the compiler options so as not to change
  the behavior at all.  It does not care about the correctness of
  the given options.  Fox example, "-march=armv5te" might be better
  than "-march=armv4" for ARM946EJS, but it is beyond the scope this
  commit.  Also, filling the missing -march=* and -tune=* is left
  to follow-up patches.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Acked-by: Marek Vasut <marex@denx.de>
Acked-by: Stefan Roese <sr@denx.de>
2015-03-27 16:55:22 +01:00
Rob Herring
7682a99826 remove unnecessary version.h includes
Various files are needlessly rebuilt every time due to the version and
build time changing. As version.h is not actually needed, remove the
include.

Signed-off-by: Rob Herring <robh@kernel.org>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Minkyu Kang <mk7.kang@samsung.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Tom Warren <twarren@nvidia.com>
Cc: Michal Simek <monstr@monstr.eu>
Cc: Macpaul Lin <macpaul@andestech.com>
Cc: Wolfgang Denk <wd@denx.de>
Cc: York Sun <yorksun@freescale.com>
Cc: Stefan Roese <sr@denx.de>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Cc: Simon Glass <sjg@chromium.org>
Cc: Philippe Reynes <tremyfr@yahoo.fr>
Cc: Eric Jarrige <eric.jarrige@armadeus.org>
Cc: "David Müller" <d.mueller@elsoft.ch>
Cc: Phil Edworthy <phil.edworthy@renesas.com>
Cc: Robert Baldyga <r.baldyga@samsung.com>
Cc: Torsten Koschorrek <koschorrek@synertronixx.de>
Cc: Anatolij Gustschin <agust@denx.de>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Reviewed-by: Łukasz Majewski <l.majewski@samsung.com>
2015-03-24 10:50:50 -04:00
Boris BREZILLON
058d231687 board/seco: Add mx6q-uq7 basic board support
Add basic SECO MX6Q/uQ7 board support (Ethernet, UART, SD are supported).
It also adds a Kconfig skeleton to later add more SECO board (supporting
SoC and board variants).

Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
2015-03-23 13:19:18 +01:00
Boris BREZILLON
89ebc82137 ARM: mx6: move to a standard arch/board approach
Freescale boards are currently all defined in arch/arm/Kconfig, which
makes them hard to detect.
Moreover the MX6 SoC variant (Q, D, DL, S, SL) selection is currently
done via the SYS_EXTRA_OPTIONS option which marked as deprecated.

Move to a more standard way to select sub-architecture and board by
creating a Kconfig under arch/arm/cpu/armv7/mx6 and a new ARCH_MX6
option.

Existing MX6 board definitions should be moved in this new Kconfig in
choice menu, and new boards should be directly declared in this menu.

Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
2015-03-23 13:18:01 +01:00
Tom Rini
a538ae997a Merge branch 'master' of git://www.denx.de/git/u-boot-imx 2015-03-18 07:07:43 -04:00
Nishanth Menon
cdef0b3f3a ARM: OMAP3: rx51: Enable workaround for ARM errata 454179, 430973, 621766
RX51 has a secure logic which uses different parameters compared to
traditional implementation. So, make the generic secure acr write
over-ride-able by board file and refactor rx51 code to use this.

While at it, enable the OMAP3 specific errata code for 454179, 430973,
621766.

Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2015-03-13 09:29:33 -04:00
Nishanth Menon
c6f90e1418 ARM: OMAP3: Enable workaround for ARM errata 454179, 430973, 621766
Enable the OMAP3 specific errata code for 454179, 430973, 621766
and while at it, remove legacy non-revision checked errata logic.

Signed-off-by: Nishanth Menon <nm@ti.com>
Tested-by: Matt Porter <mporter@konsulko.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2015-03-13 09:29:24 -04:00
Nishanth Menon
fc7368ec85 ARM: OMAP5 / DRA7: Setup L2 Aux Control Register with recommended configuration
Update to existing recommendation for L2ACTLR configuration to prevent
system instability and optimize performance.

These apply to both OMAP5 and DRA7.

Reported-by: Vivek Chengalvala <vchengalvala@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2015-03-13 09:29:13 -04:00
Praveen Rao
5f603761c3 ARM: DRA7 / OMAP5: Add workaround for ARM errata 798870
This patch enables the workaround for ARM errata 798870 for OMAP5 /
DRA7 which says "If back-to-back speculative cache line fills (fill
A and fill B) are issued from the L1 data cache of a CPU to the
L2 cache, the second request (fill B) is then cancelled, and the
second request would have detected a hazard against a recent write or
eviction (write B) to the same cache line as fill B then the L2 logic
might deadlock."

An l2auxctlr accessor implementation for OMAP5 and DRA7 is introduced
here as well.

Signed-off-by: Praveen Rao <prao@ti.com>
Signed-off-by: Angela Stegmaier <angelabaker@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Tested-by: Matt Porter <mporter@konsulko.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2015-03-13 09:29:01 -04:00
Nishanth Menon
49ec949091 ARM: OMAP3: Get rid of omap3_gp_romcode_call and replace with omap_smc1
omap_smc1 is now generic enough to remove duplicate
omap3_gp_romcode_call logic that omap3 introduced.

As part of this change, move to using the generic lowlevel_init.S for
omap3 as well.

Signed-off-by: Nishanth Menon <nm@ti.com>
Tested-by: Matt Porter <mporter@konsulko.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2015-03-13 09:29:00 -04:00
Nishanth Menon
6d8abe6a8a ARM: OMAP: Change set_pl310_ctrl_reg to be generic
set_pl310_ctrl_reg does use the Secure Monitor Call (SMC) to setup
PL310 control register, however, that is something that is generic
enough to be used for OMAP5 generation of processors as well. The only
difference being the service being invoked for the function.

So, convert the service to a macro and use a generic name (same as
that used in Linux for some consistency). While at that, also add a
data barrier which is necessary as per recommendation.

While at this, smc #0 is maintained as handcoded assembly thanks to
various gcc version eccentricities, discussion thread:
http://marc.info/?t=142542166800001&r=1&w=2

Signed-off-by: Nishanth Menon <nm@ti.com>
Tested-by: Matt Porter <mporter@konsulko.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2015-03-13 09:28:55 -04:00
Nishanth Menon
9b4d65f918 ARM: Introduce erratum workaround for 621766
621766: Under a specific set of conditions, executing a sequence of
	NEON or vfp load instructions can cause processor deadlock
Impacts: Every Cortex-A8 processors with revision lower than r2p1
Work around: Set L1NEON to 1

Based on ARM errata Document revision 20.0 (13 Nov 2010)

Signed-off-by: Nishanth Menon <nm@ti.com>
Tested-by: Matt Porter <mporter@konsulko.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2015-03-13 09:28:53 -04:00
Nishanth Menon
5902f4ce0f ARM: Introduce erratum workaround for 430973
430973: Stale prediction on replaced inter working branch causes
	Cortex-A8 to execute in the wrong ARM/Thumb state
Impacts: Every Cortex-A8 processors with revision lower than r2p1
Work around: Set IBE to 1

Based on ARM errata Document revision 20.0 (13 Nov 2010)

Signed-off-by: Nishanth Menon <nm@ti.com>
Tested-by: Matt Porter <mporter@konsulko.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2015-03-13 09:28:52 -04:00
Nishanth Menon
b45c48a7c3 ARM: Introduce erratum workaround for 454179
454179: Stale prediction may inhibit target address misprediction on
	next predicted taken branch
Impacts: Every Cortex-A8 processors with revision lower than r2p1
Work around:  Set IBE and disable branch size mispredict to 1

Also provide a hook for SoC specific handling to take place if needed.

Based on ARM errata Document revision 20.0 (13 Nov 2010)

Signed-off-by: Nishanth Menon <nm@ti.com>
Tested-by: Matt Porter <mporter@konsulko.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2015-03-13 09:28:48 -04:00
Nishanth Menon
c616a0df29 ARM: Introduce erratum workaround for 798870
Add workaround for Cortex-A15 ARM erratum 798870 which says
"If back-to-back speculative cache line fills (fill A and fill B) are
issued from the L1 data cache of a CPU to the L2 cache, the second
request (fill B) is then cancelled, and the second request would have
detected a hazard against a recent write or eviction (write B) to the
same cache line as fill B then the L2 logic might deadlock."

Implementations for SoC families such as Exynos, OMAP5/DRA7 etc
will be widely different.

Every SoC has slightly different manner of setting up access to L2ACLR
and similar registers since the Secure Monitor handling of Secure
Monitor Call(smc) is diverse. Hence an weak function is introduced
which may be overriden to implement SoC specific accessor implementation.

Based on ARM errata Document revision 18.0 (22 Nov 2013)

Signed-off-by: Nishanth Menon <nm@ti.com>
Tested-by: Matt Porter <mporter@konsulko.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2015-03-13 09:28:29 -04:00
Dirk Behme
9d16c52f62 mx6: soc: Switch to cold reset
Disable the warm reset and enable the cold reset for a more reliable
restart ('reset'). This is taken from the Linux kernel, see imx_src_init()
in arch/arm/mach-imx/src.c.

Signed-off-by: Dirk Behme <dirk.behme@de.bosch.com>
2015-03-13 13:29:42 +01:00
Peng Fan
0c1842a01f imx:mx6 remove duplicated includes
There is no need to include asm/bootm.h twice, so remove one.

Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
2015-03-13 13:28:04 +01:00