Commit graph

47268 commits

Author SHA1 Message Date
Marek Vasut
033b611989 clk: rmobile: Add R8A7796 xHCI clock
Add xHCI entry into the clock tables, so that the xHCI USB driver
can enable the clock for the xHCI block via clock framework.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2017-11-30 02:32:33 +01:00
Marek Vasut
18cac5afc2 clk: rmobile: Move preboot clock shutdown to the driver
The MSTP registers were poked in boards/renesas/rcar-common/common.c
in arch_preboot_os hook thus far to shut down the clock before Linux
takes over. With DM, this is no longer needed and we can do the same
in the clock driver .remove callback. This patch adds such a .remove
callback for R8A7795 and R8A7796.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2017-11-30 02:32:33 +01:00
Marek Vasut
942ee0933e fdtdec: Support parsing multiple /memory nodes
It is legal to have multiple /memory nodes in a device tree . Currently,
fdtdec_setup_memory_size() only supports parsing the first node . This
patch extends the function such that if a particular /memory node does
no longer have further "reg" entries and CONFIG_NR_DRAM_BANKS still
allows for more DRAM banks, the code moves on to the next memory node
and checks it's "reg"s. This makes it possible to handle both systems
with single memory node with multiple entries and systems with multiple
memory nodes with single entry.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Tom Rini <trini@konsulko.com>
Cc: Simon Glass <sjg@chromium.org>
2017-11-30 02:32:33 +01:00
Marek Vasut
9db60e257b MAINTAINERS: Add myself as RCar/RMobile comaintainer
To help out with the RCar/RMobile upstreaming, I'm adding myself
as the RCar/RMobile maintainer.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2017-11-30 02:32:33 +01:00
Tom Rini
b06c46de63 Xilinx changes for v2018.1
Zynq:
 - Add support for Syzygy and cc108 boards
 - Add support for mini u-boot configurations (cse)
 - dts updates
 - config/defconfig updates in connection to Kconfig changes
 - Fix psu_init handling
 
 ZynqMP:
 - SPL fixes
 - Remove slcr.c
 - Fixing r5 startup sequence
 - Add support for external pmufw
 - Add support for new ZynqMP chips
 - dts updates
 - Add support for zcu102 rev1.0 board
 
 Drivers:
 - nand: Support external timing setting and board init
 - ahci: Fix wording
 - axi_emac: Wait for bit, non processor mode, readl/write conversion
 - zynq_gem: Fix SGMII/PCS support
 -----BEGIN PGP SIGNATURE-----
 Version: GnuPG v1
 
 iEYEABECAAYFAloeqWoACgkQykllyylKDCHO1wCggsSgQqOPdCo207FqI3yj2p0E
 MYkAoI1wKvQcjGJJY19YEC1r70Op8RNo
 =BqNN
 -----END PGP SIGNATURE-----

Merge tag 'xilinx-for-v2018.01' of git://www.denx.de/git/u-boot-microblaze

Xilinx changes for v2018.1

Zynq:
- Add support for Syzygy and cc108 boards
- Add support for mini u-boot configurations (cse)
- dts updates
- config/defconfig updates in connection to Kconfig changes
- Fix psu_init handling

ZynqMP:
- SPL fixes
- Remove slcr.c
- Fixing r5 startup sequence
- Add support for external pmufw
- Add support for new ZynqMP chips
- dts updates
- Add support for zcu102 rev1.0 board

Drivers:
- nand: Support external timing setting and board init
- ahci: Fix wording
- axi_emac: Wait for bit, non processor mode, readl/write conversion
- zynq_gem: Fix SGMII/PCS support
2017-11-29 08:26:07 -05:00
Siva Durga Prasad Paladugu
a04a5daae2 net: xilinx_axi_emac: Use readl and writel for io ops
This patch uses readl and writel instead of in_be32 and
out_be32 for io ops as these internally uses readl,
writel for microblaze and for Zynq, ZynqMP there is
no need of endianness conversion and readl, writel
should work straightaway. This patch starts supporting
the driver for Zynq and ZynqMP platforms.

Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2017-11-29 08:02:40 +01:00
Siva Durga Prasad Paladugu
dd12a27ce2 net: zynq_gem: Dont enable SGMII and PCS selection
Dont enable SGMII and PCS selection if internal PCS/PMA
is not used, by getting the info about internal/external
PCS/PMA usage from dt property "is-internal-phy".

Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2017-11-29 08:02:40 +01:00
Michal Simek
b8d4497f99 arm: zynq: Change Zynq/ZynqMP Kconfig description
Use more accurate description for Xilinx Zynq and ZynqMP based platforms.
With using driver model there shouldn't be a need to create separate
Kconfig config options.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2017-11-29 08:02:40 +01:00
Jean-Francois Dagenais
df4950e302 tools: zynqmpimage: adjust ug1085 reference to v1.4 of the document
The chapter in which the table explaining the image format changed
chapter as the document evolved. This should help people track the
info down faster.

Signed-off-by: Jean-Francois Dagenais <jeff.dagenais@gmail.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2017-11-29 08:02:40 +01:00
Joe Hershberger
6d3fa0dfdd mtd: nand: zynq: Add support for the NAND lock/unlock operation
Zynq NAND driver is not support for NAND lock or unlock operation.
Hence, accidentally write into the critical NAND region might cause
data corruption to occur.

This commit is to add NAND lock/unlock command into NAND SMC register
set for NAND lock/unlock operaion.

Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Signed-off-by: Keng Soon Cheah <keng.soon.cheah@ni.com>
Cc: Chen Yee Chew <chen.yee.chew@ni.com>
Cc: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Cc: Michal Simek <michal.simek@xilinx.com>
Cc: Scott Wood <oss@buserror.net>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2017-11-29 08:02:40 +01:00
Wilson Lee
310995d9f9 mtd: zynq: nand: Move board_nand_init() function to board.c
Putting board_nand_init() function inside NAND driver was not appropriate
due to it doesn't allow board vendor to customise their NAND
initialization code such as adding NAND lock/unlock code.

This commit was to move the board_nand_init() function from NAND driver
to board.c file. This allow customization of board_nand_init() function.

Signed-off-by: Wilson Lee <wilson.lee@ni.com>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Cc: Keng Soon Cheah <keng.soon.cheah@ni.com>
Cc: Chen Yee Chew <chen.yee.chew@ni.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Michal Simek <michal.simek@xilinx.com>
Cc: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Cc: Scott Wood <oss@buserror.net>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2017-11-29 08:02:40 +01:00
Michal Simek
40df796133 arm: zynq: Add ps7_init for cc108
After some generic cleanup adding ps7_init* to repository
is not big pain now.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2017-11-29 08:02:40 +01:00
Michal Simek
29fb570378 arm: zynq: Show information about silicon version
Show information about silicon in bootlog.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2017-11-29 08:02:40 +01:00
Michal Simek
d28dc3d3dc arm: zynq: Do not show information from checkboard twice
There is no reason to show information about board twice.
Remove boardinfo late calls.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2017-11-29 08:02:40 +01:00
Michal Simek
30829447a4 arm: zynq: Use unsigned type with comparison with ARRAY_SIZE
Sparse is return warning about this:
arch/arm/mach-zynq/slcr.c: In function 'zynq_slcr_get_mio_pin_status':
arch/arm/mach-zynq/slcr.c:185:16: warning: comparison between signed and
unsigned integer expressions [-Wsign-compare]
  for (i = 0; i < ARRAY_SIZE(mio_periphs); i++) {
                ^

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2017-11-29 08:02:39 +01:00
Michal Simek
460b05d96d arm: zynq: Convert all board to use arch ps7_init code
Use generic implementation. It will also reduce config data size for
converted boards.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2017-11-29 08:02:39 +01:00
Michal Simek
11ea6f556c arm: zynq: Add support for EMIT_WRITE operation
Add proper support for EMIT_WRITE operation which is write only.
Do not use EMIT_MASKWRITE which is read-modify-write.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2017-11-29 08:02:39 +01:00
Michal Simek
f29074803c arm: zynq: Add ps7GetSiliconVersion() to ps7_spl_init
Unfortunately camelcase is coming from ps7_init* format.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2017-11-29 08:02:39 +01:00
Michal Simek
c0823a76df arm: zynq: Move common ps7_init* initialization to arch code
This patch is based on work done in topic board where the first address
word also storing operation which should be done. This is reducing size
of configuration data.
This patch is not breaking an option to copy default ps7_init_gpl* files
from hdf file but it is doing preparation for ps7_init* consolidation.

The patch is also marking ps7_config as weak function.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2017-11-29 08:02:39 +01:00
Michal Simek
a8ea299c48 arm: zynq: Get rid of ps7_reset_apu() for syzygy board
There is no reason to call separate function.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2017-11-29 08:02:39 +01:00
Michal Simek
f0b619ec29 arm: zynq: Move ps7_* to separate file
Extract ps7_* from spl code to prepare for extension.
And also return value.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2017-11-29 08:02:39 +01:00
Michal Simek
a3b36c8424 arm: zynq: Remove ps7_debug code
SPL is not calling this code that's why it is dead code and can be
removed.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2017-11-29 08:02:39 +01:00
Michal Simek
2665fb0336 arm: zynq: Enable debug uart on zc706
Enable debug uart by default.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2017-11-29 08:02:38 +01:00
Michal Simek
96b96adf0b arm: zynq: Add missing ps7_post_config declaration
Add missing declaration to header.

Warning log:
arch/arm/mach-zynq/spl.c:94:12: warning: symbol 'ps7_post_config' was
not declared. Should it be static?

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2017-11-29 08:02:38 +01:00
Siva Durga Prasad Paladugu
89ce5a9dbe net: xilinx_axi_emac: Add support for non processor mode
Add support for non processor mode, this mode doesn't have
access to some of the registers and hence this patch
bypasses it and also length has to be calculated from
status instead of app4 in this mode.

Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
2017-11-29 08:02:33 +01:00
Tom Rini
fcc8250c2f Merge git://git.denx.de/u-boot-mips 2017-11-28 16:54:30 -05:00
Tom Rini
74a4818415 Merge git://git.denx.de/u-boot-uniphier 2017-11-28 16:54:09 -05:00
Paul Burton
caead80a66 boston: Add u-boot.mcs make target
U-Boot is generally flashed to a MIPS Boston development board by means
of a .mcs file which Xilinx Vivado software can write to the flash
present on the board. As such we'd generally want to produce an mcs file
when building U-Boot to target the Boston board. Introduce a make target
for u-boot.mcs which generates it using the srec_cat tool available from
the SRecord project, and build it by default when srec_cat is present.

Signed-off-by: Paul Burton <paul.burton@mips.com>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Cc: u-boot@lists.denx.de
2017-11-28 21:59:30 +01:00
Paul Burton
fabcffe930 boston: Set CONFIG_SYS_LOAD_ADDR to 0x88000000
Generally we load Linux kernels on Boston boards in the form of FIT
images containing a compressed kernel binary. Linux is linked at
0x80100000 and so we need to decompress the kernel binary to that
address, however this is our default load address which means that
unless explicitly avoided we hit a decompression error as the
uncompressed kernel binary overwrites its compressed version from the
FIT image.

Avoid this by adjusting CONFIG_SYS_LOAD_ADDR to 0x88000000 (or
0xffffffff88000000 for MIPS64 builds) which avoids the address overlap
between compressed & uncompressed kernel binaries.

Signed-off-by: Paul Burton <paul.burton@mips.com>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Cc: u-boot@lists.denx.de
2017-11-28 21:59:30 +01:00
Paul Burton
cc4f36435f MIPS: Break out of cache loops for unimplemented caches
If we run on a CPU which doesn't implement a particular cache then we
would previously get stuck in an infinite loop, executing a cache op on
the first "line" of the missing cache & then incrementing the address by
0. This was being avoided for the L2 caches, but not for the L1s. Fix
this by generalising the check for a zero line size & avoiding the cache
op loop when this is the case.

Signed-off-by: Paul Burton <paul.burton@mips.com>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Cc: u-boot@lists.denx.de
2017-11-28 21:59:30 +01:00
Paul Burton
d8b326976a MIPS: Clear instruction hazards in flush_cache()
When writing code, for example during relocation, we ensure that the
icache has a coherent view of the new instructions with a call to
flush_cache(). This handles the bulk of the work to ensure the new
instructions will execute as expected, however it does not ensure that
the CPU pipeline doesn't already contain instructions taken from a stale
view of the affected memory. This could theoretically be a problem for
relocation, but in practice typically isn't because we sync caches for
enough code after the entry point of the newly written code that by the
time the CPU pipeline might possibly fetch any of it we'll have long ago
written it back & invalidated any stale icache entries. This is however
a problem for shorter regions of code.

In preparation for later patches which write shorter segments of code,
ensure any instruction hazards are cleared by flush_cache() by
introducing & using a new instruction_hazard_barrier() function which
makes use of the jr.hb instruction to clear the hazard.

Signed-off-by: Paul Burton <paul.burton@mips.com>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Cc: u-boot@lists.denx.de
2017-11-28 21:59:30 +01:00
Paul Burton
219c2db384 MIPS: Ensure cache ops complete in cache maintenance functions
A typical use of cache maintenance functions is to force writeback of
data which a device is about to read using DMA - for example a
descriptor or command structure. Such users of cache maintenance
functions require that operations on the cache have completed before
they proceed to instruct a device to read memory. This requires that we
place a completion barrier (ie. sync instruction) between the cache ops
and whatever write informs the device to perform DMA.

Whilst strictly speaking this isn't all users of the cache maintenance
functions & we could instead place the barriers in the drivers that
require them, it would be much more invasive to do so than to just have
the barrier be the default by placing it in the cache functions
themselves. The cost is low enough that it shouldn't matter to us in any
rare cases that we use the cache functions when not performing DMA.

Signed-off-by: Paul Burton <paul.burton@mips.com>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Cc: u-boot@lists.denx.de
2017-11-28 21:59:30 +01:00
Paul Burton
c5bf161fac Update Paul Burton's email address
MIPS is no longer a part of Imagination Technologies, and as such my
@imgtec.com email address will soon cease to function. This patch
updates occurrances of it with my new @mips.com email address, and adds
an entry in .mailmap such that git (& tools such as get_maintainer.pl
when examining history) will use the new address.

Signed-off-by: Paul Burton <paul.burton@mips.com>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Cc: u-boot@lists.denx.de
2017-11-28 21:59:30 +01:00
Paul Burton
73780b012e MIPS: Drop unused PTR_COUNT_SHIFT from u-boot.lds
The u-boot.lds linker script for MIPS defines a PTR_COUNT_SHIFT macro to
2 or 3 for 32 bit or 64 bit builds respectively. This macro is never
actually used though, so remove the dead code.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2017-11-28 21:59:30 +01:00
Paul Burton
64f733d3fa boston: Remove unused label in lowlevel_display
The lowlevel_display() function includes a "1:" label which is never
used. Remove it.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2017-11-28 21:59:30 +01:00
Paul Burton
555a652953 boston: Drop unused return value
The boston lowlevel_init() function zeroes the return register v0,
despite the function not being expected to return a value & that value
never being used.

Remove the redundant assignment to v0.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2017-11-28 21:59:30 +01:00
Masahiro Yamada
a27bcbf815 ARM: uniphier: remove unused NAND CONFIG options
The Denali NAND driver does not use these options any more.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-11-29 00:29:00 +09:00
Masahiro Yamada
b443fb4210 ARM: dts: uniphier: Sync with Linux 4.15-rc1
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-11-29 00:29:00 +09:00
Masahiro Yamada
e9986a4fa7 gpio: uniphier: import dt-binginds header from Linux
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-11-29 00:28:59 +09:00
Masahiro Yamada
10c62f41e3 ARM: uniphier: remove XIRQ pin settings
The XIRQ pins are now set up on the Linux side by the GPIO hogging.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-11-29 00:28:59 +09:00
Masahiro Yamada
eadd95a97e ARM: uniphier: remove IRQ settings
This work-around has been here in U-Boot because the AIDET and GPIO
drivers were missing in the upstream Linux.  Both are now available
in Linus' tree:
  - drivers/irqchip/irq-uniphier-aidet.c
  - drivers/gpio/gpio-uniphier.c

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-11-29 00:28:59 +09:00
Masahiro Yamada
53c149c3a5 ARM: uniphier: set CONFIG_LOGLEVEL to 6
Print out KERN_NOTICE or higher level log messages.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-11-29 00:28:59 +09:00
Masahiro Yamada
350d052dab mtd: nand: denali: sync with Linux 4.15-rc1
I largely reworked the Denali NAND controller driver in Linux.
This commit imports the improvements from Linux.  The code is
almost synced with Linux 4.15-rc1.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-11-29 00:28:59 +09:00
Masahiro Yamada
e6001371d1 mtd: nand: introduce NAND_ROW_ADDR_3 flag
Several drivers check ->chipsize to see if the third row address cycle
is needed.  Instead of embedding magic sizes such as 32MB, 128MB in
drivers, introduce a new flag NAND_ROW_ADDR_3 for clean-up.  Since
nand_scan_ident() knows well about the device, it can handle this
properly.  The flag is set if the row address bit width is greater
than 16.

Delete comments such as "One more address cycle for ..." because
intention is now clear enough from the code.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Acked-by: Wenyou Yang <wenyou.yang@microchip.com>
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>

[Linux commit: 14157f861437ebe2d624b0a845b91bbdf8ca9a2d]
2017-11-29 00:28:59 +09:00
Masahiro Yamada
a01549ba40 mtd: nand: add a shorthand to generate nand_ecc_caps structure
struct nand_ecc_caps was designed as flexible as possible to support
multiple stepsizes (like sunxi_nand.c).

So, we need to write multiple arrays even for the simplest case.
I guess many controllers support a single stepsize, so here is a
shorthand macro for the case.

It allows to describe like ...

NAND_ECC_CAPS_SINGLE(denali_pci_ecc_caps, denali_calc_ecc_bytes, 512, 8, 15);

... instead of

static const int denali_pci_ecc_strengths[] = {8, 15};
static const struct nand_ecc_step_info denali_pci_ecc_stepinfo = {
        .stepsize = 512,
        .strengths = denali_pci_ecc_strengths,
        .nstrengths = ARRAY_SIZE(denali_pci_ecc_strengths),
};
static const struct nand_ecc_caps denali_pci_ecc_caps = {
        .stepinfos = &denali_pci_ecc_stepinfo,
        .nstepinfos = 1,
        .calc_ecc_bytes = denali_calc_ecc_bytes,
};

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>

[Linux commit: a03c60178c181767ecfb26fb311a88742d228118]
2017-11-29 00:28:59 +09:00
Masahiro Yamada
470c29d1c2 mtd: nand: add generic helpers to check, match, maximize ECC settings
Driver are responsible for setting up ECC parameters correctly.
Those include:
  - Check if ECC parameters specified (usually by DT) are valid
  - Meet the chip's ECC requirement
  - Maximize ECC strength if NAND_ECC_MAXIMIZE flag is set

The logic can be generalized by factoring out common code.

This commit adds 3 helpers to the NAND framework:
nand_check_ecc_caps - Check if preset step_size and strength are valid
nand_match_ecc_req - Match the chip's requirement
nand_maximize_ecc - Maximize the ECC strength

To use the helpers above, a driver needs to provide:
  - Data array of supported ECC step size and strength
  - A hook that calculates ECC bytes from the combination of
    step_size and strength.

By using those helpers, code duplication among drivers will be
reduced.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>

[Linux commit: 2c8f8afa7f92acb07641bf95b940d384ed1d0294]
2017-11-29 00:28:59 +09:00
Boris Brezillon
52cde35b96 mtd: nand: Pass the CS line to ->setup_data_interface()
Some NAND controllers can assign different NAND timings to different
CS lines. Pass the CS line information to ->setup_data_interface() so
that the NAND controller driver knows which CS line is concerned by
the setup_data_interface() request.

Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
[Linux commit: 104e442a67cfba4d0cc982384761befb917fb6a1]
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-11-29 00:28:59 +09:00
Masahiro Yamada
436fb2b84d mtd: nand: allow drivers to request minimum alignment for passed buffer
In some cases, nand_do_{read,write}_ops is passed with unaligned
ops->datbuf.  Drivers using DMA will be unhappy about unaligned
buffer.

The new struct member, buf_align, represents the minimum alignment
the driver require for the buffer.  If the buffer passed from the
upper MTD layer does not have enough alignment, nand_do_*_ops will
use bufpoi.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>

[Linux commit: 477544c62a84d3bacd9f90ba75ffc16c04d78071]
2017-11-29 00:28:59 +09:00
Boris Brezillon
c7c553f249 mtd: nand: Wait for PAGEPROG to finish in drivers setting NAND_ECC_CUSTOM_PAGE_ACCESS
Drivers setting NAND_ECC_CUSTOM_PAGE_ACCESS are supposed to handle the
full read/write page sequence, and waiting for a page to actually be
programmed is part of this write-page sequence.
This is also what is done in ->write_oob_xxx() hooks, so let's do that in
->write_page_xxx() as well to make it consistent.

Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
[Linux commit: 41145649f4acb30249b636b945053db50c9331c5]
[masahiro:
 There is no driver setting NAND_ECC_CUSTOM_PAGE_ACCESS in U-Boot.
 No driver is affected by this change.]
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-11-29 00:28:58 +09:00
Boris Brezillon
94b50a8aae mtd: nand: Drop the ->errstat() hook
The ->errstat() hook is no longer implemented NAND controller drivers.
Get rid of it before someone starts abusing it.

Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
[Linux commit: 7d135bcced20be2b50128432c5426a7278ec4f6d]
[masahiro: modify davinci_nand.c for U-Boot]
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-11-29 00:28:58 +09:00