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https://github.com/AsahiLinux/u-boot
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arm: zynq: Convert all board to use arch ps7_init code
Use generic implementation. It will also reduce config data size for converted boards. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
This commit is contained in:
Michal Simek
parent
11ea6f556c
commit
460b05d96d
12 changed files with 6 additions and 1629 deletions
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@ -5,8 +5,7 @@
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* SPDX-License-Identifier: GPL-2.0+
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*****************************************************************************/
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#include "ps7_init_gpl.h"
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#include "asm/io.h"
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#include <asm/arch/ps7_init_gpl.h>
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unsigned long ps7_pll_init_data_3_0[] = {
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EMIT_WRITE(0XF8000008, 0x0000DF0DU),
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@ -255,92 +254,11 @@ unsigned long ps7_post_config_3_0[] = {
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EMIT_EXIT(),
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};
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unsigned long ps7_reset_apu_3_0[] = {
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EMIT_MASKWRITE(0xF8000244, 0x00000022U, 0x00000022U),
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EMIT_EXIT(),
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};
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#define PS7_MASK_POLL_TIME 100000000
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static inline void iowrite(unsigned long val, unsigned long addr)
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{
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__raw_writel(val, addr);
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}
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static inline unsigned long ioread(unsigned long addr)
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{
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return __raw_readl(addr);
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}
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int ps7_config(unsigned long *ps7_config_init)
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{
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unsigned long *ptr = ps7_config_init;
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unsigned long opcode; /* current instruction .. */
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unsigned long args[16]; /* no opcode has so many args ... */
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int numargs; /* number of arguments of this instruction */
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int j; /* general purpose index */
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unsigned long addr;
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unsigned long val, mask;
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int finish = -1; /* loop while this is negative ! */
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int i = 0; /* Timeout variable */
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while (finish < 0) {
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numargs = ptr[0] & 0xF;
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opcode = ptr[0] >> 4;
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for (j = 0; j < numargs; j++)
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args[j] = ptr[j + 1];
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ptr += numargs + 1;
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switch (opcode) {
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case OPCODE_EXIT:
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finish = PS7_INIT_SUCCESS;
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break;
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case OPCODE_WRITE:
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addr = args[0];
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val = args[1];
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iowrite(val, addr);
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break;
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case OPCODE_MASKWRITE:
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addr = args[0];
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mask = args[1];
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val = args[2];
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iowrite((val & mask) | (ioread(addr) & ~mask) , addr);
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break;
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case OPCODE_MASKPOLL:
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addr = args[0];
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mask = args[1];
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i = 0;
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while (!(ioread(addr) & mask)) {
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if (i == PS7_MASK_POLL_TIME) {
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finish = PS7_INIT_TIMEOUT;
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break;
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}
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i++;
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}
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break;
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case OPCODE_MASKDELAY:
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addr = args[0];
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mask = args[1];
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int delay = get_number_of_cycles_for_delay(mask);
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perf_reset_and_start_timer();
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while (ioread(addr) < delay)
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;
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break;
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default:
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finish = PS7_INIT_CORRUPT;
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break;
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}
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}
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return finish;
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}
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int ps7_post_config(void)
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{
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@ -377,39 +295,3 @@ int ps7_init(void)
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return PS7_INIT_SUCCESS;
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}
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/* For delay calculation using global timer */
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/* start timer */
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void perf_start_clock(void)
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{
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iowrite((1 << 0) | /* Timer Enable */
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(1 << 3) | /* Auto-increment */
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(0 << 8), /* Pre-scale */
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SCU_GLOBAL_TIMER_CONTROL);
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}
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/* stop timer and reset timer count regs */
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void perf_reset_clock(void)
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{
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perf_disable_clock();
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iowrite(0, SCU_GLOBAL_TIMER_COUNT_L32);
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iowrite(0, SCU_GLOBAL_TIMER_COUNT_U32);
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}
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/* Compute mask for given delay in miliseconds*/
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int get_number_of_cycles_for_delay(unsigned int delay)
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{
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return APU_FREQ * delay / (2 * 1000);
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}
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/* stop timer */
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void perf_disable_clock(void)
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{
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iowrite(0, SCU_GLOBAL_TIMER_CONTROL);
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}
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void perf_reset_and_start_timer(void)
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{
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perf_reset_clock();
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perf_start_clock();
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}
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@ -1,80 +0,0 @@
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/******************************************************************************
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*
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* (c) Copyright 2010-2014 Xilinx, Inc. All rights reserved.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*****************************************************************************/
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#ifdef __cplusplus
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extern "C" {
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#endif
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#define OPCODE_EXIT 0U
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#define OPCODE_CLEAR 1U
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#define OPCODE_WRITE 2U
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#define OPCODE_MASKWRITE 3U
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#define OPCODE_MASKPOLL 4U
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#define OPCODE_MASKDELAY 5U
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/* Encode number of arguments in last nibble */
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#define EMIT_EXIT() ((OPCODE_EXIT << 4) | 0)
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#define EMIT_WRITE(addr, val) ((OPCODE_WRITE << 4) | 2) , addr, val
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#define EMIT_MASKWRITE(addr, mask, val) ((OPCODE_MASKWRITE << 4) | 3) ,\
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addr, mask, val
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#define EMIT_MASKPOLL(addr, mask) ((OPCODE_MASKPOLL << 4) | 2) ,\
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addr, mask
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#define EMIT_MASKDELAY(addr, mask) ((OPCODE_MASKDELAY << 4) | 2) ,\
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addr, mask
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/* Returns codes of PS7_Init */
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#define PS7_INIT_SUCCESS (0)
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#define PS7_INIT_CORRUPT (1)
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#define PS7_INIT_TIMEOUT (2)
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#define PS7_POLL_FAILED_DDR_INIT (3)
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#define PS7_POLL_FAILED_DMA (4)
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#define PS7_POLL_FAILED_PLL (5)
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/* Freq of all peripherals */
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#define APU_FREQ 650000000
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#define DDR_FREQ 525000000
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#define DCI_FREQ 10096154
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#define QSPI_FREQ 200000000
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#define SMC_FREQ 10000000
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#define ENET0_FREQ 125000000
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#define ENET1_FREQ 10000000
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#define USB0_FREQ 60000000
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#define USB1_FREQ 60000000
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#define SDIO_FREQ 100000000
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#define UART_FREQ 100000000
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#define SPI_FREQ 10000000
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#define I2C_FREQ 108333336
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#define WDT_FREQ 108333336
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#define TTC_FREQ 50000000
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#define CAN_FREQ 10000000
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#define PCAP_FREQ 200000000
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#define TPIU_FREQ 200000000
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#define FPGA0_FREQ 50000000
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#define FPGA1_FREQ 10000000
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#define FPGA2_FREQ 10000000
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#define FPGA3_FREQ 10000000
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/* For delay calculation using global registers*/
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#define SCU_GLOBAL_TIMER_COUNT_L32 0xF8F00200
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#define SCU_GLOBAL_TIMER_COUNT_U32 0xF8F00204
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#define SCU_GLOBAL_TIMER_CONTROL 0xF8F00208
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#define SCU_GLOBAL_TIMER_AUTO_INC 0xF8F00218
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int ps7_config(unsigned long *);
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int ps7_init(void);
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int ps7_post_config(void);
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void perf_start_clock(void);
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void perf_disable_clock(void);
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void perf_reset_clock(void);
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void perf_reset_and_start_timer(void);
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int get_number_of_cycles_for_delay(unsigned int delay);
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#ifdef __cplusplus
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}
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#endif
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@ -14,7 +14,7 @@
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*
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*****************************************************************************/
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#include "ps7_init_gpl.h"
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#include <asm/arch/ps7_init_gpl.h>
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unsigned long ps7_pll_init_data_3_0[] = {
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// START: top
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@ -12591,139 +12591,6 @@ unsigned long ps7_post_config_1_0[] = {
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#include "xil_io.h"
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#define PS7_MASK_POLL_TIME 100000000
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char*
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getPS7MessageInfo(unsigned key) {
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char* err_msg = "";
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switch (key) {
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case PS7_INIT_SUCCESS: err_msg = "PS7 initialization successful"; break;
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case PS7_INIT_CORRUPT: err_msg = "PS7 init Data Corrupted"; break;
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case PS7_INIT_TIMEOUT: err_msg = "PS7 init mask poll timeout"; break;
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case PS7_POLL_FAILED_DDR_INIT: err_msg = "Mask Poll failed for DDR Init"; break;
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case PS7_POLL_FAILED_DMA: err_msg = "Mask Poll failed for PLL Init"; break;
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case PS7_POLL_FAILED_PLL: err_msg = "Mask Poll failed for DMA done bit"; break;
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default: err_msg = "Undefined error status"; break;
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}
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return err_msg;
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}
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unsigned long
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ps7GetSiliconVersion () {
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// Read PS version from MCTRL register [31:28]
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unsigned long mask = 0xF0000000;
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unsigned long *addr = (unsigned long*) 0XF8007080;
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unsigned long ps_version = (*addr & mask) >> 28;
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return ps_version;
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}
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void mask_write (unsigned long add , unsigned long mask, unsigned long val ) {
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unsigned long *addr = (unsigned long*) add;
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*addr = ( val & mask ) | ( *addr & ~mask);
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//xil_printf("MaskWrite : 0x%x--> 0x%x \n \r" ,add, *addr);
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}
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int mask_poll(unsigned long add , unsigned long mask ) {
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volatile unsigned long *addr = (volatile unsigned long*) add;
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int i = 0;
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while (!(*addr & mask)) {
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if (i == PS7_MASK_POLL_TIME) {
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return -1;
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}
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i++;
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}
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return 1;
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//xil_printf("MaskPoll : 0x%x --> 0x%x \n \r" , add, *addr);
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}
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unsigned long mask_read(unsigned long add , unsigned long mask ) {
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unsigned long *addr = (unsigned long*) add;
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unsigned long val = (*addr & mask);
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//xil_printf("MaskRead : 0x%x --> 0x%x \n \r" , add, val);
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return val;
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}
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int
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ps7_config(unsigned long * ps7_config_init)
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{
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unsigned long *ptr = ps7_config_init;
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unsigned long opcode; // current instruction ..
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unsigned long args[16]; // no opcode has so many args ...
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int numargs; // number of arguments of this instruction
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int j; // general purpose index
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volatile unsigned long *addr; // some variable to make code readable
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unsigned long val,mask; // some variable to make code readable
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int finish = -1 ; // loop while this is negative !
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int i = 0; // Timeout variable
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while( finish < 0 ) {
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numargs = ptr[0] & 0xF;
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opcode = ptr[0] >> 4;
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for( j = 0 ; j < numargs ; j ++ )
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args[j] = ptr[j+1];
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ptr += numargs + 1;
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switch ( opcode ) {
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case OPCODE_EXIT:
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finish = PS7_INIT_SUCCESS;
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break;
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case OPCODE_CLEAR:
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addr = (unsigned long*) args[0];
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*addr = 0;
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break;
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case OPCODE_WRITE:
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addr = (unsigned long*) args[0];
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val = args[1];
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*addr = val;
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break;
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case OPCODE_MASKWRITE:
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addr = (unsigned long*) args[0];
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mask = args[1];
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val = args[2];
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*addr = ( val & mask ) | ( *addr & ~mask);
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break;
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case OPCODE_MASKPOLL:
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addr = (unsigned long*) args[0];
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mask = args[1];
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i = 0;
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while (!(*addr & mask)) {
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if (i == PS7_MASK_POLL_TIME) {
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finish = PS7_INIT_TIMEOUT;
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break;
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}
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i++;
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}
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break;
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case OPCODE_MASKDELAY:
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addr = (unsigned long*) args[0];
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mask = args[1];
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int delay = get_number_of_cycles_for_delay(mask);
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perf_reset_and_start_timer();
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while ((*addr < delay)) {
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}
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break;
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default:
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finish = PS7_INIT_CORRUPT;
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break;
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}
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}
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return finish;
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}
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unsigned long *ps7_mio_init_data = ps7_mio_init_data_3_0;
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unsigned long *ps7_pll_init_data = ps7_pll_init_data_3_0;
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@ -12811,41 +12678,3 @@ ps7_init()
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/* For delay calculation using global timer */
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/* start timer */
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void perf_start_clock(void)
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{
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*(volatile unsigned int*)SCU_GLOBAL_TIMER_CONTROL = ((1 << 0) | // Timer Enable
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(1 << 3) | // Auto-increment
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(0 << 8) // Pre-scale
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);
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}
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/* stop timer and reset timer count regs */
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void perf_reset_clock(void)
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{
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perf_disable_clock();
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*(volatile unsigned int*)SCU_GLOBAL_TIMER_COUNT_L32 = 0;
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*(volatile unsigned int*)SCU_GLOBAL_TIMER_COUNT_U32 = 0;
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}
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/* Compute mask for given delay in miliseconds*/
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int get_number_of_cycles_for_delay(unsigned int delay)
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{
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// GTC is always clocked at 1/2 of the CPU frequency (CPU_3x2x)
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return (APU_FREQ*delay/(2*1000));
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}
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/* stop timer */
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void perf_disable_clock(void)
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{
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*(volatile unsigned int*)SCU_GLOBAL_TIMER_CONTROL = 0;
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}
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void perf_reset_and_start_timer()
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{
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perf_reset_clock();
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perf_start_clock();
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}
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@ -1,116 +0,0 @@
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/******************************************************************************
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*
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* (c) Copyright 2010-2014 Xilinx, Inc. All rights reserved.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*
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*
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*******************************************************************************/
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/****************************************************************************/
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/**
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*
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* @file ps7_init.h
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*
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* This file can be included in FSBL code
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* to get prototype of ps7_init() function
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* and error codes
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*
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*****************************************************************************/
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#ifdef __cplusplus
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extern "C" {
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#endif
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//typedef unsigned int u32;
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/** do we need to make this name more unique ? **/
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//extern u32 ps7_init_data[];
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extern unsigned long * ps7_ddr_init_data;
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extern unsigned long * ps7_mio_init_data;
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extern unsigned long * ps7_pll_init_data;
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extern unsigned long * ps7_clock_init_data;
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extern unsigned long * ps7_peripherals_init_data;
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#define OPCODE_EXIT 0U
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#define OPCODE_CLEAR 1U
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#define OPCODE_WRITE 2U
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#define OPCODE_MASKWRITE 3U
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#define OPCODE_MASKPOLL 4U
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#define OPCODE_MASKDELAY 5U
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#define NEW_PS7_ERR_CODE 1
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/* Encode number of arguments in last nibble */
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#define EMIT_EXIT() ( (OPCODE_EXIT << 4 ) | 0 )
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#define EMIT_CLEAR(addr) ( (OPCODE_CLEAR << 4 ) | 1 ) , addr
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#define EMIT_WRITE(addr,val) ( (OPCODE_WRITE << 4 ) | 2 ) , addr, val
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#define EMIT_MASKWRITE(addr,mask,val) ( (OPCODE_MASKWRITE << 4 ) | 3 ) , addr, mask, val
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#define EMIT_MASKPOLL(addr,mask) ( (OPCODE_MASKPOLL << 4 ) | 2 ) , addr, mask
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#define EMIT_MASKDELAY(addr,mask) ( (OPCODE_MASKDELAY << 4 ) | 2 ) , addr, mask
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/* Returns codes of PS7_Init */
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#define PS7_INIT_SUCCESS (0) // 0 is success in good old C
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#define PS7_INIT_CORRUPT (1) // 1 the data is corrupted, and slcr reg are in corrupted state now
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#define PS7_INIT_TIMEOUT (2) // 2 when a poll operation timed out
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#define PS7_POLL_FAILED_DDR_INIT (3) // 3 when a poll operation timed out for ddr init
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#define PS7_POLL_FAILED_DMA (4) // 4 when a poll operation timed out for dma done bit
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#define PS7_POLL_FAILED_PLL (5) // 5 when a poll operation timed out for pll sequence init
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/* Silicon Versions */
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#define PCW_SILICON_VERSION_1 0
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#define PCW_SILICON_VERSION_2 1
|
||||
#define PCW_SILICON_VERSION_3 2
|
||||
|
||||
/* This flag to be used by FSBL to check whether ps7_post_config() proc exixts */
|
||||
#define PS7_POST_CONFIG
|
||||
|
||||
/* Freq of all peripherals */
|
||||
|
||||
#define APU_FREQ 666666687
|
||||
#define DDR_FREQ 533333374
|
||||
#define DCI_FREQ 10158731
|
||||
#define QSPI_FREQ 200000000
|
||||
#define SMC_FREQ 10000000
|
||||
#define ENET0_FREQ 125000000
|
||||
#define ENET1_FREQ 10000000
|
||||
#define USB0_FREQ 60000000
|
||||
#define USB1_FREQ 60000000
|
||||
#define SDIO_FREQ 50000000
|
||||
#define UART_FREQ 50000000
|
||||
#define SPI_FREQ 10000000
|
||||
#define I2C_FREQ 111111115
|
||||
#define WDT_FREQ 111111115
|
||||
#define TTC_FREQ 50000000
|
||||
#define CAN_FREQ 10000000
|
||||
#define PCAP_FREQ 200000000
|
||||
#define TPIU_FREQ 200000000
|
||||
#define FPGA0_FREQ 100000000
|
||||
#define FPGA1_FREQ 100000000
|
||||
#define FPGA2_FREQ 33333336
|
||||
#define FPGA3_FREQ 50000000
|
||||
|
||||
|
||||
/* For delay calculation using global registers*/
|
||||
#define SCU_GLOBAL_TIMER_COUNT_L32 0xF8F00200
|
||||
#define SCU_GLOBAL_TIMER_COUNT_U32 0xF8F00204
|
||||
#define SCU_GLOBAL_TIMER_CONTROL 0xF8F00208
|
||||
#define SCU_GLOBAL_TIMER_AUTO_INC 0xF8F00218
|
||||
|
||||
int ps7_config( unsigned long*);
|
||||
int ps7_init();
|
||||
int ps7_post_config();
|
||||
char* getPS7MessageInfo(unsigned key);
|
||||
|
||||
void perf_start_clock(void);
|
||||
void perf_disable_clock(void);
|
||||
void perf_reset_clock(void);
|
||||
void perf_reset_and_start_timer();
|
||||
int get_number_of_cycles_for_delay(unsigned int delay);
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
|
@ -14,7 +14,7 @@
|
|||
*
|
||||
*****************************************************************************/
|
||||
|
||||
#include "ps7_init_gpl.h"
|
||||
#include <asm/arch/ps7_init_gpl.h>
|
||||
|
||||
unsigned long ps7_pll_init_data_3_0[] = {
|
||||
// START: top
|
||||
|
|
@ -12924,139 +12924,6 @@ unsigned long ps7_post_config_1_0[] = {
|
|||
|
||||
|
||||
#include "xil_io.h"
|
||||
#define PS7_MASK_POLL_TIME 100000000
|
||||
|
||||
char*
|
||||
getPS7MessageInfo(unsigned key) {
|
||||
|
||||
char* err_msg = "";
|
||||
switch (key) {
|
||||
case PS7_INIT_SUCCESS: err_msg = "PS7 initialization successful"; break;
|
||||
case PS7_INIT_CORRUPT: err_msg = "PS7 init Data Corrupted"; break;
|
||||
case PS7_INIT_TIMEOUT: err_msg = "PS7 init mask poll timeout"; break;
|
||||
case PS7_POLL_FAILED_DDR_INIT: err_msg = "Mask Poll failed for DDR Init"; break;
|
||||
case PS7_POLL_FAILED_DMA: err_msg = "Mask Poll failed for PLL Init"; break;
|
||||
case PS7_POLL_FAILED_PLL: err_msg = "Mask Poll failed for DMA done bit"; break;
|
||||
default: err_msg = "Undefined error status"; break;
|
||||
}
|
||||
|
||||
return err_msg;
|
||||
}
|
||||
|
||||
unsigned long
|
||||
ps7GetSiliconVersion () {
|
||||
// Read PS version from MCTRL register [31:28]
|
||||
unsigned long mask = 0xF0000000;
|
||||
unsigned long *addr = (unsigned long*) 0XF8007080;
|
||||
unsigned long ps_version = (*addr & mask) >> 28;
|
||||
return ps_version;
|
||||
}
|
||||
|
||||
void mask_write (unsigned long add , unsigned long mask, unsigned long val ) {
|
||||
unsigned long *addr = (unsigned long*) add;
|
||||
*addr = ( val & mask ) | ( *addr & ~mask);
|
||||
//xil_printf("MaskWrite : 0x%x--> 0x%x \n \r" ,add, *addr);
|
||||
}
|
||||
|
||||
|
||||
int mask_poll(unsigned long add , unsigned long mask ) {
|
||||
volatile unsigned long *addr = (volatile unsigned long*) add;
|
||||
int i = 0;
|
||||
while (!(*addr & mask)) {
|
||||
if (i == PS7_MASK_POLL_TIME) {
|
||||
return -1;
|
||||
}
|
||||
i++;
|
||||
}
|
||||
return 1;
|
||||
//xil_printf("MaskPoll : 0x%x --> 0x%x \n \r" , add, *addr);
|
||||
}
|
||||
|
||||
unsigned long mask_read(unsigned long add , unsigned long mask ) {
|
||||
unsigned long *addr = (unsigned long*) add;
|
||||
unsigned long val = (*addr & mask);
|
||||
//xil_printf("MaskRead : 0x%x --> 0x%x \n \r" , add, val);
|
||||
return val;
|
||||
}
|
||||
|
||||
|
||||
|
||||
int
|
||||
ps7_config(unsigned long * ps7_config_init)
|
||||
{
|
||||
unsigned long *ptr = ps7_config_init;
|
||||
|
||||
unsigned long opcode; // current instruction ..
|
||||
unsigned long args[16]; // no opcode has so many args ...
|
||||
int numargs; // number of arguments of this instruction
|
||||
int j; // general purpose index
|
||||
|
||||
volatile unsigned long *addr; // some variable to make code readable
|
||||
unsigned long val,mask; // some variable to make code readable
|
||||
|
||||
int finish = -1 ; // loop while this is negative !
|
||||
int i = 0; // Timeout variable
|
||||
|
||||
while( finish < 0 ) {
|
||||
numargs = ptr[0] & 0xF;
|
||||
opcode = ptr[0] >> 4;
|
||||
|
||||
for( j = 0 ; j < numargs ; j ++ )
|
||||
args[j] = ptr[j+1];
|
||||
ptr += numargs + 1;
|
||||
|
||||
|
||||
switch ( opcode ) {
|
||||
|
||||
case OPCODE_EXIT:
|
||||
finish = PS7_INIT_SUCCESS;
|
||||
break;
|
||||
|
||||
case OPCODE_CLEAR:
|
||||
addr = (unsigned long*) args[0];
|
||||
*addr = 0;
|
||||
break;
|
||||
|
||||
case OPCODE_WRITE:
|
||||
addr = (unsigned long*) args[0];
|
||||
val = args[1];
|
||||
*addr = val;
|
||||
break;
|
||||
|
||||
case OPCODE_MASKWRITE:
|
||||
addr = (unsigned long*) args[0];
|
||||
mask = args[1];
|
||||
val = args[2];
|
||||
*addr = ( val & mask ) | ( *addr & ~mask);
|
||||
break;
|
||||
|
||||
case OPCODE_MASKPOLL:
|
||||
addr = (unsigned long*) args[0];
|
||||
mask = args[1];
|
||||
i = 0;
|
||||
while (!(*addr & mask)) {
|
||||
if (i == PS7_MASK_POLL_TIME) {
|
||||
finish = PS7_INIT_TIMEOUT;
|
||||
break;
|
||||
}
|
||||
i++;
|
||||
}
|
||||
break;
|
||||
case OPCODE_MASKDELAY:
|
||||
addr = (unsigned long*) args[0];
|
||||
mask = args[1];
|
||||
int delay = get_number_of_cycles_for_delay(mask);
|
||||
perf_reset_and_start_timer();
|
||||
while ((*addr < delay)) {
|
||||
}
|
||||
break;
|
||||
default:
|
||||
finish = PS7_INIT_CORRUPT;
|
||||
break;
|
||||
}
|
||||
}
|
||||
return finish;
|
||||
}
|
||||
|
||||
unsigned long *ps7_mio_init_data = ps7_mio_init_data_3_0;
|
||||
unsigned long *ps7_pll_init_data = ps7_pll_init_data_3_0;
|
||||
|
|
@ -13140,45 +13007,3 @@ ps7_init()
|
|||
//xil_printf ("\n PCW Silicon Version : %d.0", pcw_ver);
|
||||
return PS7_INIT_SUCCESS;
|
||||
}
|
||||
|
||||
|
||||
|
||||
|
||||
/* For delay calculation using global timer */
|
||||
|
||||
/* start timer */
|
||||
void perf_start_clock(void)
|
||||
{
|
||||
*(volatile unsigned int*)SCU_GLOBAL_TIMER_CONTROL = ((1 << 0) | // Timer Enable
|
||||
(1 << 3) | // Auto-increment
|
||||
(0 << 8) // Pre-scale
|
||||
);
|
||||
}
|
||||
|
||||
/* stop timer and reset timer count regs */
|
||||
void perf_reset_clock(void)
|
||||
{
|
||||
perf_disable_clock();
|
||||
*(volatile unsigned int*)SCU_GLOBAL_TIMER_COUNT_L32 = 0;
|
||||
*(volatile unsigned int*)SCU_GLOBAL_TIMER_COUNT_U32 = 0;
|
||||
}
|
||||
|
||||
/* Compute mask for given delay in miliseconds*/
|
||||
int get_number_of_cycles_for_delay(unsigned int delay)
|
||||
{
|
||||
// GTC is always clocked at 1/2 of the CPU frequency (CPU_3x2x)
|
||||
return (APU_FREQ*delay/(2*1000));
|
||||
|
||||
}
|
||||
|
||||
/* stop timer */
|
||||
void perf_disable_clock(void)
|
||||
{
|
||||
*(volatile unsigned int*)SCU_GLOBAL_TIMER_CONTROL = 0;
|
||||
}
|
||||
|
||||
void perf_reset_and_start_timer()
|
||||
{
|
||||
perf_reset_clock();
|
||||
perf_start_clock();
|
||||
}
|
||||
|
|
|
|||
|
|
@ -1,116 +0,0 @@
|
|||
|
||||
/******************************************************************************
|
||||
*
|
||||
* (c) Copyright 2010-2014 Xilinx, Inc. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*
|
||||
*
|
||||
*******************************************************************************/
|
||||
/****************************************************************************/
|
||||
/**
|
||||
*
|
||||
* @file ps7_init.h
|
||||
*
|
||||
* This file can be included in FSBL code
|
||||
* to get prototype of ps7_init() function
|
||||
* and error codes
|
||||
*
|
||||
*****************************************************************************/
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
|
||||
//typedef unsigned int u32;
|
||||
|
||||
|
||||
/** do we need to make this name more unique ? **/
|
||||
//extern u32 ps7_init_data[];
|
||||
extern unsigned long * ps7_ddr_init_data;
|
||||
extern unsigned long * ps7_mio_init_data;
|
||||
extern unsigned long * ps7_pll_init_data;
|
||||
extern unsigned long * ps7_clock_init_data;
|
||||
extern unsigned long * ps7_peripherals_init_data;
|
||||
|
||||
|
||||
|
||||
#define OPCODE_EXIT 0U
|
||||
#define OPCODE_CLEAR 1U
|
||||
#define OPCODE_WRITE 2U
|
||||
#define OPCODE_MASKWRITE 3U
|
||||
#define OPCODE_MASKPOLL 4U
|
||||
#define OPCODE_MASKDELAY 5U
|
||||
#define NEW_PS7_ERR_CODE 1
|
||||
|
||||
/* Encode number of arguments in last nibble */
|
||||
#define EMIT_EXIT() ( (OPCODE_EXIT << 4 ) | 0 )
|
||||
#define EMIT_CLEAR(addr) ( (OPCODE_CLEAR << 4 ) | 1 ) , addr
|
||||
#define EMIT_WRITE(addr,val) ( (OPCODE_WRITE << 4 ) | 2 ) , addr, val
|
||||
#define EMIT_MASKWRITE(addr,mask,val) ( (OPCODE_MASKWRITE << 4 ) | 3 ) , addr, mask, val
|
||||
#define EMIT_MASKPOLL(addr,mask) ( (OPCODE_MASKPOLL << 4 ) | 2 ) , addr, mask
|
||||
#define EMIT_MASKDELAY(addr,mask) ( (OPCODE_MASKDELAY << 4 ) | 2 ) , addr, mask
|
||||
|
||||
/* Returns codes of PS7_Init */
|
||||
#define PS7_INIT_SUCCESS (0) // 0 is success in good old C
|
||||
#define PS7_INIT_CORRUPT (1) // 1 the data is corrupted, and slcr reg are in corrupted state now
|
||||
#define PS7_INIT_TIMEOUT (2) // 2 when a poll operation timed out
|
||||
#define PS7_POLL_FAILED_DDR_INIT (3) // 3 when a poll operation timed out for ddr init
|
||||
#define PS7_POLL_FAILED_DMA (4) // 4 when a poll operation timed out for dma done bit
|
||||
#define PS7_POLL_FAILED_PLL (5) // 5 when a poll operation timed out for pll sequence init
|
||||
|
||||
|
||||
/* Silicon Versions */
|
||||
#define PCW_SILICON_VERSION_1 0
|
||||
#define PCW_SILICON_VERSION_2 1
|
||||
#define PCW_SILICON_VERSION_3 2
|
||||
|
||||
/* This flag to be used by FSBL to check whether ps7_post_config() proc exixts */
|
||||
#define PS7_POST_CONFIG
|
||||
|
||||
/* Freq of all peripherals */
|
||||
|
||||
#define APU_FREQ 666666687
|
||||
#define DDR_FREQ 533333374
|
||||
#define DCI_FREQ 10158731
|
||||
#define QSPI_FREQ 200000000
|
||||
#define SMC_FREQ 10000000
|
||||
#define ENET0_FREQ 25000000
|
||||
#define ENET1_FREQ 10000000
|
||||
#define USB0_FREQ 60000000
|
||||
#define USB1_FREQ 60000000
|
||||
#define SDIO_FREQ 50000000
|
||||
#define UART_FREQ 50000000
|
||||
#define SPI_FREQ 10000000
|
||||
#define I2C_FREQ 111111115
|
||||
#define WDT_FREQ 111111115
|
||||
#define TTC_FREQ 50000000
|
||||
#define CAN_FREQ 23809523
|
||||
#define PCAP_FREQ 200000000
|
||||
#define TPIU_FREQ 200000000
|
||||
#define FPGA0_FREQ 50000000
|
||||
#define FPGA1_FREQ 50000000
|
||||
#define FPGA2_FREQ 50000000
|
||||
#define FPGA3_FREQ 50000000
|
||||
|
||||
|
||||
/* For delay calculation using global registers*/
|
||||
#define SCU_GLOBAL_TIMER_COUNT_L32 0xF8F00200
|
||||
#define SCU_GLOBAL_TIMER_COUNT_U32 0xF8F00204
|
||||
#define SCU_GLOBAL_TIMER_CONTROL 0xF8F00208
|
||||
#define SCU_GLOBAL_TIMER_AUTO_INC 0xF8F00218
|
||||
|
||||
int ps7_config( unsigned long*);
|
||||
int ps7_init();
|
||||
int ps7_post_config();
|
||||
char* getPS7MessageInfo(unsigned key);
|
||||
|
||||
void perf_start_clock(void);
|
||||
void perf_disable_clock(void);
|
||||
void perf_reset_clock(void);
|
||||
void perf_reset_and_start_timer();
|
||||
int get_number_of_cycles_for_delay(unsigned int delay);
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
|
@ -14,7 +14,7 @@
|
|||
*
|
||||
*****************************************************************************/
|
||||
|
||||
#include "ps7_init_gpl.h"
|
||||
#include <asm/arch/ps7_init_gpl.h>
|
||||
|
||||
unsigned long ps7_pll_init_data_3_0[] = {
|
||||
// START: top
|
||||
|
|
@ -12831,139 +12831,6 @@ unsigned long ps7_post_config_1_0[] = {
|
|||
|
||||
|
||||
#include "xil_io.h"
|
||||
#define PS7_MASK_POLL_TIME 100000000
|
||||
|
||||
char*
|
||||
getPS7MessageInfo(unsigned key) {
|
||||
|
||||
char* err_msg = "";
|
||||
switch (key) {
|
||||
case PS7_INIT_SUCCESS: err_msg = "PS7 initialization successful"; break;
|
||||
case PS7_INIT_CORRUPT: err_msg = "PS7 init Data Corrupted"; break;
|
||||
case PS7_INIT_TIMEOUT: err_msg = "PS7 init mask poll timeout"; break;
|
||||
case PS7_POLL_FAILED_DDR_INIT: err_msg = "Mask Poll failed for DDR Init"; break;
|
||||
case PS7_POLL_FAILED_DMA: err_msg = "Mask Poll failed for PLL Init"; break;
|
||||
case PS7_POLL_FAILED_PLL: err_msg = "Mask Poll failed for DMA done bit"; break;
|
||||
default: err_msg = "Undefined error status"; break;
|
||||
}
|
||||
|
||||
return err_msg;
|
||||
}
|
||||
|
||||
unsigned long
|
||||
ps7GetSiliconVersion () {
|
||||
// Read PS version from MCTRL register [31:28]
|
||||
unsigned long mask = 0xF0000000;
|
||||
unsigned long *addr = (unsigned long*) 0XF8007080;
|
||||
unsigned long ps_version = (*addr & mask) >> 28;
|
||||
return ps_version;
|
||||
}
|
||||
|
||||
void mask_write (unsigned long add , unsigned long mask, unsigned long val ) {
|
||||
unsigned long *addr = (unsigned long*) add;
|
||||
*addr = ( val & mask ) | ( *addr & ~mask);
|
||||
//xil_printf("MaskWrite : 0x%x--> 0x%x \n \r" ,add, *addr);
|
||||
}
|
||||
|
||||
|
||||
int mask_poll(unsigned long add , unsigned long mask ) {
|
||||
volatile unsigned long *addr = (volatile unsigned long*) add;
|
||||
int i = 0;
|
||||
while (!(*addr & mask)) {
|
||||
if (i == PS7_MASK_POLL_TIME) {
|
||||
return -1;
|
||||
}
|
||||
i++;
|
||||
}
|
||||
return 1;
|
||||
//xil_printf("MaskPoll : 0x%x --> 0x%x \n \r" , add, *addr);
|
||||
}
|
||||
|
||||
unsigned long mask_read(unsigned long add , unsigned long mask ) {
|
||||
unsigned long *addr = (unsigned long*) add;
|
||||
unsigned long val = (*addr & mask);
|
||||
//xil_printf("MaskRead : 0x%x --> 0x%x \n \r" , add, val);
|
||||
return val;
|
||||
}
|
||||
|
||||
|
||||
|
||||
int
|
||||
ps7_config(unsigned long * ps7_config_init)
|
||||
{
|
||||
unsigned long *ptr = ps7_config_init;
|
||||
|
||||
unsigned long opcode; // current instruction ..
|
||||
unsigned long args[16]; // no opcode has so many args ...
|
||||
int numargs; // number of arguments of this instruction
|
||||
int j; // general purpose index
|
||||
|
||||
volatile unsigned long *addr; // some variable to make code readable
|
||||
unsigned long val,mask; // some variable to make code readable
|
||||
|
||||
int finish = -1 ; // loop while this is negative !
|
||||
int i = 0; // Timeout variable
|
||||
|
||||
while( finish < 0 ) {
|
||||
numargs = ptr[0] & 0xF;
|
||||
opcode = ptr[0] >> 4;
|
||||
|
||||
for( j = 0 ; j < numargs ; j ++ )
|
||||
args[j] = ptr[j+1];
|
||||
ptr += numargs + 1;
|
||||
|
||||
|
||||
switch ( opcode ) {
|
||||
|
||||
case OPCODE_EXIT:
|
||||
finish = PS7_INIT_SUCCESS;
|
||||
break;
|
||||
|
||||
case OPCODE_CLEAR:
|
||||
addr = (unsigned long*) args[0];
|
||||
*addr = 0;
|
||||
break;
|
||||
|
||||
case OPCODE_WRITE:
|
||||
addr = (unsigned long*) args[0];
|
||||
val = args[1];
|
||||
*addr = val;
|
||||
break;
|
||||
|
||||
case OPCODE_MASKWRITE:
|
||||
addr = (unsigned long*) args[0];
|
||||
mask = args[1];
|
||||
val = args[2];
|
||||
*addr = ( val & mask ) | ( *addr & ~mask);
|
||||
break;
|
||||
|
||||
case OPCODE_MASKPOLL:
|
||||
addr = (unsigned long*) args[0];
|
||||
mask = args[1];
|
||||
i = 0;
|
||||
while (!(*addr & mask)) {
|
||||
if (i == PS7_MASK_POLL_TIME) {
|
||||
finish = PS7_INIT_TIMEOUT;
|
||||
break;
|
||||
}
|
||||
i++;
|
||||
}
|
||||
break;
|
||||
case OPCODE_MASKDELAY:
|
||||
addr = (unsigned long*) args[0];
|
||||
mask = args[1];
|
||||
int delay = get_number_of_cycles_for_delay(mask);
|
||||
perf_reset_and_start_timer();
|
||||
while ((*addr < delay)) {
|
||||
}
|
||||
break;
|
||||
default:
|
||||
finish = PS7_INIT_CORRUPT;
|
||||
break;
|
||||
}
|
||||
}
|
||||
return finish;
|
||||
}
|
||||
|
||||
unsigned long *ps7_mio_init_data = ps7_mio_init_data_3_0;
|
||||
unsigned long *ps7_pll_init_data = ps7_pll_init_data_3_0;
|
||||
|
|
@ -13051,41 +12918,3 @@ ps7_init()
|
|||
|
||||
|
||||
|
||||
/* For delay calculation using global timer */
|
||||
|
||||
/* start timer */
|
||||
void perf_start_clock(void)
|
||||
{
|
||||
*(volatile unsigned int*)SCU_GLOBAL_TIMER_CONTROL = ((1 << 0) | // Timer Enable
|
||||
(1 << 3) | // Auto-increment
|
||||
(0 << 8) // Pre-scale
|
||||
);
|
||||
}
|
||||
|
||||
/* stop timer and reset timer count regs */
|
||||
void perf_reset_clock(void)
|
||||
{
|
||||
perf_disable_clock();
|
||||
*(volatile unsigned int*)SCU_GLOBAL_TIMER_COUNT_L32 = 0;
|
||||
*(volatile unsigned int*)SCU_GLOBAL_TIMER_COUNT_U32 = 0;
|
||||
}
|
||||
|
||||
/* Compute mask for given delay in miliseconds*/
|
||||
int get_number_of_cycles_for_delay(unsigned int delay)
|
||||
{
|
||||
// GTC is always clocked at 1/2 of the CPU frequency (CPU_3x2x)
|
||||
return (APU_FREQ*delay/(2*1000));
|
||||
|
||||
}
|
||||
|
||||
/* stop timer */
|
||||
void perf_disable_clock(void)
|
||||
{
|
||||
*(volatile unsigned int*)SCU_GLOBAL_TIMER_CONTROL = 0;
|
||||
}
|
||||
|
||||
void perf_reset_and_start_timer()
|
||||
{
|
||||
perf_reset_clock();
|
||||
perf_start_clock();
|
||||
}
|
||||
|
|
|
|||
|
|
@ -1,116 +0,0 @@
|
|||
|
||||
/******************************************************************************
|
||||
*
|
||||
* (c) Copyright 2010-2014 Xilinx, Inc. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*
|
||||
*
|
||||
*******************************************************************************/
|
||||
/****************************************************************************/
|
||||
/**
|
||||
*
|
||||
* @file ps7_init.h
|
||||
*
|
||||
* This file can be included in FSBL code
|
||||
* to get prototype of ps7_init() function
|
||||
* and error codes
|
||||
*
|
||||
*****************************************************************************/
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
|
||||
//typedef unsigned int u32;
|
||||
|
||||
|
||||
/** do we need to make this name more unique ? **/
|
||||
//extern u32 ps7_init_data[];
|
||||
extern unsigned long * ps7_ddr_init_data;
|
||||
extern unsigned long * ps7_mio_init_data;
|
||||
extern unsigned long * ps7_pll_init_data;
|
||||
extern unsigned long * ps7_clock_init_data;
|
||||
extern unsigned long * ps7_peripherals_init_data;
|
||||
|
||||
|
||||
|
||||
#define OPCODE_EXIT 0U
|
||||
#define OPCODE_CLEAR 1U
|
||||
#define OPCODE_WRITE 2U
|
||||
#define OPCODE_MASKWRITE 3U
|
||||
#define OPCODE_MASKPOLL 4U
|
||||
#define OPCODE_MASKDELAY 5U
|
||||
#define NEW_PS7_ERR_CODE 1
|
||||
|
||||
/* Encode number of arguments in last nibble */
|
||||
#define EMIT_EXIT() ( (OPCODE_EXIT << 4 ) | 0 )
|
||||
#define EMIT_CLEAR(addr) ( (OPCODE_CLEAR << 4 ) | 1 ) , addr
|
||||
#define EMIT_WRITE(addr,val) ( (OPCODE_WRITE << 4 ) | 2 ) , addr, val
|
||||
#define EMIT_MASKWRITE(addr,mask,val) ( (OPCODE_MASKWRITE << 4 ) | 3 ) , addr, mask, val
|
||||
#define EMIT_MASKPOLL(addr,mask) ( (OPCODE_MASKPOLL << 4 ) | 2 ) , addr, mask
|
||||
#define EMIT_MASKDELAY(addr,mask) ( (OPCODE_MASKDELAY << 4 ) | 2 ) , addr, mask
|
||||
|
||||
/* Returns codes of PS7_Init */
|
||||
#define PS7_INIT_SUCCESS (0) // 0 is success in good old C
|
||||
#define PS7_INIT_CORRUPT (1) // 1 the data is corrupted, and slcr reg are in corrupted state now
|
||||
#define PS7_INIT_TIMEOUT (2) // 2 when a poll operation timed out
|
||||
#define PS7_POLL_FAILED_DDR_INIT (3) // 3 when a poll operation timed out for ddr init
|
||||
#define PS7_POLL_FAILED_DMA (4) // 4 when a poll operation timed out for dma done bit
|
||||
#define PS7_POLL_FAILED_PLL (5) // 5 when a poll operation timed out for pll sequence init
|
||||
|
||||
|
||||
/* Silicon Versions */
|
||||
#define PCW_SILICON_VERSION_1 0
|
||||
#define PCW_SILICON_VERSION_2 1
|
||||
#define PCW_SILICON_VERSION_3 2
|
||||
|
||||
/* This flag to be used by FSBL to check whether ps7_post_config() proc exixts */
|
||||
#define PS7_POST_CONFIG
|
||||
|
||||
/* Freq of all peripherals */
|
||||
|
||||
#define APU_FREQ 666666687
|
||||
#define DDR_FREQ 533333374
|
||||
#define DCI_FREQ 10158731
|
||||
#define QSPI_FREQ 200000000
|
||||
#define SMC_FREQ 10000000
|
||||
#define ENET0_FREQ 25000000
|
||||
#define ENET1_FREQ 10000000
|
||||
#define USB0_FREQ 60000000
|
||||
#define USB1_FREQ 60000000
|
||||
#define SDIO_FREQ 50000000
|
||||
#define UART_FREQ 50000000
|
||||
#define SPI_FREQ 10000000
|
||||
#define I2C_FREQ 111111115
|
||||
#define WDT_FREQ 111111115
|
||||
#define TTC_FREQ 50000000
|
||||
#define CAN_FREQ 10000000
|
||||
#define PCAP_FREQ 200000000
|
||||
#define TPIU_FREQ 200000000
|
||||
#define FPGA0_FREQ 50000000
|
||||
#define FPGA1_FREQ 50000000
|
||||
#define FPGA2_FREQ 50000000
|
||||
#define FPGA3_FREQ 50000000
|
||||
|
||||
|
||||
/* For delay calculation using global registers*/
|
||||
#define SCU_GLOBAL_TIMER_COUNT_L32 0xF8F00200
|
||||
#define SCU_GLOBAL_TIMER_COUNT_U32 0xF8F00204
|
||||
#define SCU_GLOBAL_TIMER_CONTROL 0xF8F00208
|
||||
#define SCU_GLOBAL_TIMER_AUTO_INC 0xF8F00218
|
||||
|
||||
int ps7_config( unsigned long*);
|
||||
int ps7_init();
|
||||
int ps7_post_config();
|
||||
char* getPS7MessageInfo(unsigned key);
|
||||
|
||||
void perf_start_clock(void);
|
||||
void perf_disable_clock(void);
|
||||
void perf_reset_clock(void);
|
||||
void perf_reset_and_start_timer();
|
||||
int get_number_of_cycles_for_delay(unsigned int delay);
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
|
@ -14,7 +14,7 @@
|
|||
*
|
||||
*****************************************************************************/
|
||||
|
||||
#include "ps7_init_gpl.h"
|
||||
#include <asm/arch/ps7_init_gpl.h>
|
||||
|
||||
unsigned long ps7_pll_init_data_3_0[] = {
|
||||
// START: top
|
||||
|
|
@ -12489,139 +12489,6 @@ unsigned long ps7_post_config_1_0[] = {
|
|||
|
||||
|
||||
#include "xil_io.h"
|
||||
#define PS7_MASK_POLL_TIME 100000000
|
||||
|
||||
char*
|
||||
getPS7MessageInfo(unsigned key) {
|
||||
|
||||
char* err_msg = "";
|
||||
switch (key) {
|
||||
case PS7_INIT_SUCCESS: err_msg = "PS7 initialization successful"; break;
|
||||
case PS7_INIT_CORRUPT: err_msg = "PS7 init Data Corrupted"; break;
|
||||
case PS7_INIT_TIMEOUT: err_msg = "PS7 init mask poll timeout"; break;
|
||||
case PS7_POLL_FAILED_DDR_INIT: err_msg = "Mask Poll failed for DDR Init"; break;
|
||||
case PS7_POLL_FAILED_DMA: err_msg = "Mask Poll failed for PLL Init"; break;
|
||||
case PS7_POLL_FAILED_PLL: err_msg = "Mask Poll failed for DMA done bit"; break;
|
||||
default: err_msg = "Undefined error status"; break;
|
||||
}
|
||||
|
||||
return err_msg;
|
||||
}
|
||||
|
||||
unsigned long
|
||||
ps7GetSiliconVersion () {
|
||||
// Read PS version from MCTRL register [31:28]
|
||||
unsigned long mask = 0xF0000000;
|
||||
unsigned long *addr = (unsigned long*) 0XF8007080;
|
||||
unsigned long ps_version = (*addr & mask) >> 28;
|
||||
return ps_version;
|
||||
}
|
||||
|
||||
void mask_write (unsigned long add , unsigned long mask, unsigned long val ) {
|
||||
unsigned long *addr = (unsigned long*) add;
|
||||
*addr = ( val & mask ) | ( *addr & ~mask);
|
||||
//xil_printf("MaskWrite : 0x%x--> 0x%x \n \r" ,add, *addr);
|
||||
}
|
||||
|
||||
|
||||
int mask_poll(unsigned long add , unsigned long mask ) {
|
||||
volatile unsigned long *addr = (volatile unsigned long*) add;
|
||||
int i = 0;
|
||||
while (!(*addr & mask)) {
|
||||
if (i == PS7_MASK_POLL_TIME) {
|
||||
return -1;
|
||||
}
|
||||
i++;
|
||||
}
|
||||
return 1;
|
||||
//xil_printf("MaskPoll : 0x%x --> 0x%x \n \r" , add, *addr);
|
||||
}
|
||||
|
||||
unsigned long mask_read(unsigned long add , unsigned long mask ) {
|
||||
unsigned long *addr = (unsigned long*) add;
|
||||
unsigned long val = (*addr & mask);
|
||||
//xil_printf("MaskRead : 0x%x --> 0x%x \n \r" , add, val);
|
||||
return val;
|
||||
}
|
||||
|
||||
|
||||
|
||||
int
|
||||
ps7_config(unsigned long * ps7_config_init)
|
||||
{
|
||||
unsigned long *ptr = ps7_config_init;
|
||||
|
||||
unsigned long opcode; // current instruction ..
|
||||
unsigned long args[16]; // no opcode has so many args ...
|
||||
int numargs; // number of arguments of this instruction
|
||||
int j; // general purpose index
|
||||
|
||||
volatile unsigned long *addr; // some variable to make code readable
|
||||
unsigned long val,mask; // some variable to make code readable
|
||||
|
||||
int finish = -1 ; // loop while this is negative !
|
||||
int i = 0; // Timeout variable
|
||||
|
||||
while( finish < 0 ) {
|
||||
numargs = ptr[0] & 0xF;
|
||||
opcode = ptr[0] >> 4;
|
||||
|
||||
for( j = 0 ; j < numargs ; j ++ )
|
||||
args[j] = ptr[j+1];
|
||||
ptr += numargs + 1;
|
||||
|
||||
|
||||
switch ( opcode ) {
|
||||
|
||||
case OPCODE_EXIT:
|
||||
finish = PS7_INIT_SUCCESS;
|
||||
break;
|
||||
|
||||
case OPCODE_CLEAR:
|
||||
addr = (unsigned long*) args[0];
|
||||
*addr = 0;
|
||||
break;
|
||||
|
||||
case OPCODE_WRITE:
|
||||
addr = (unsigned long*) args[0];
|
||||
val = args[1];
|
||||
*addr = val;
|
||||
break;
|
||||
|
||||
case OPCODE_MASKWRITE:
|
||||
addr = (unsigned long*) args[0];
|
||||
mask = args[1];
|
||||
val = args[2];
|
||||
*addr = ( val & mask ) | ( *addr & ~mask);
|
||||
break;
|
||||
|
||||
case OPCODE_MASKPOLL:
|
||||
addr = (unsigned long*) args[0];
|
||||
mask = args[1];
|
||||
i = 0;
|
||||
while (!(*addr & mask)) {
|
||||
if (i == PS7_MASK_POLL_TIME) {
|
||||
finish = PS7_INIT_TIMEOUT;
|
||||
break;
|
||||
}
|
||||
i++;
|
||||
}
|
||||
break;
|
||||
case OPCODE_MASKDELAY:
|
||||
addr = (unsigned long*) args[0];
|
||||
mask = args[1];
|
||||
int delay = get_number_of_cycles_for_delay(mask);
|
||||
perf_reset_and_start_timer();
|
||||
while ((*addr < delay)) {
|
||||
}
|
||||
break;
|
||||
default:
|
||||
finish = PS7_INIT_CORRUPT;
|
||||
break;
|
||||
}
|
||||
}
|
||||
return finish;
|
||||
}
|
||||
|
||||
unsigned long *ps7_mio_init_data = ps7_mio_init_data_3_0;
|
||||
unsigned long *ps7_pll_init_data = ps7_pll_init_data_3_0;
|
||||
|
|
@ -12709,41 +12576,3 @@ ps7_init()
|
|||
|
||||
|
||||
|
||||
/* For delay calculation using global timer */
|
||||
|
||||
/* start timer */
|
||||
void perf_start_clock(void)
|
||||
{
|
||||
*(volatile unsigned int*)SCU_GLOBAL_TIMER_CONTROL = ((1 << 0) | // Timer Enable
|
||||
(1 << 3) | // Auto-increment
|
||||
(0 << 8) // Pre-scale
|
||||
);
|
||||
}
|
||||
|
||||
/* stop timer and reset timer count regs */
|
||||
void perf_reset_clock(void)
|
||||
{
|
||||
perf_disable_clock();
|
||||
*(volatile unsigned int*)SCU_GLOBAL_TIMER_COUNT_L32 = 0;
|
||||
*(volatile unsigned int*)SCU_GLOBAL_TIMER_COUNT_U32 = 0;
|
||||
}
|
||||
|
||||
/* Compute mask for given delay in miliseconds*/
|
||||
int get_number_of_cycles_for_delay(unsigned int delay)
|
||||
{
|
||||
// GTC is always clocked at 1/2 of the CPU frequency (CPU_3x2x)
|
||||
return (APU_FREQ*delay/(2*1000));
|
||||
|
||||
}
|
||||
|
||||
/* stop timer */
|
||||
void perf_disable_clock(void)
|
||||
{
|
||||
*(volatile unsigned int*)SCU_GLOBAL_TIMER_CONTROL = 0;
|
||||
}
|
||||
|
||||
void perf_reset_and_start_timer()
|
||||
{
|
||||
perf_reset_clock();
|
||||
perf_start_clock();
|
||||
}
|
||||
|
|
|
|||
|
|
@ -1,116 +0,0 @@
|
|||
|
||||
/******************************************************************************
|
||||
*
|
||||
* (c) Copyright 2010-2014 Xilinx, Inc. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*
|
||||
*
|
||||
*******************************************************************************/
|
||||
/****************************************************************************/
|
||||
/**
|
||||
*
|
||||
* @file ps7_init.h
|
||||
*
|
||||
* This file can be included in FSBL code
|
||||
* to get prototype of ps7_init() function
|
||||
* and error codes
|
||||
*
|
||||
*****************************************************************************/
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
|
||||
//typedef unsigned int u32;
|
||||
|
||||
|
||||
/** do we need to make this name more unique ? **/
|
||||
//extern u32 ps7_init_data[];
|
||||
extern unsigned long * ps7_ddr_init_data;
|
||||
extern unsigned long * ps7_mio_init_data;
|
||||
extern unsigned long * ps7_pll_init_data;
|
||||
extern unsigned long * ps7_clock_init_data;
|
||||
extern unsigned long * ps7_peripherals_init_data;
|
||||
|
||||
|
||||
|
||||
#define OPCODE_EXIT 0U
|
||||
#define OPCODE_CLEAR 1U
|
||||
#define OPCODE_WRITE 2U
|
||||
#define OPCODE_MASKWRITE 3U
|
||||
#define OPCODE_MASKPOLL 4U
|
||||
#define OPCODE_MASKDELAY 5U
|
||||
#define NEW_PS7_ERR_CODE 1
|
||||
|
||||
/* Encode number of arguments in last nibble */
|
||||
#define EMIT_EXIT() ( (OPCODE_EXIT << 4 ) | 0 )
|
||||
#define EMIT_CLEAR(addr) ( (OPCODE_CLEAR << 4 ) | 1 ) , addr
|
||||
#define EMIT_WRITE(addr,val) ( (OPCODE_WRITE << 4 ) | 2 ) , addr, val
|
||||
#define EMIT_MASKWRITE(addr,mask,val) ( (OPCODE_MASKWRITE << 4 ) | 3 ) , addr, mask, val
|
||||
#define EMIT_MASKPOLL(addr,mask) ( (OPCODE_MASKPOLL << 4 ) | 2 ) , addr, mask
|
||||
#define EMIT_MASKDELAY(addr,mask) ( (OPCODE_MASKDELAY << 4 ) | 2 ) , addr, mask
|
||||
|
||||
/* Returns codes of PS7_Init */
|
||||
#define PS7_INIT_SUCCESS (0) // 0 is success in good old C
|
||||
#define PS7_INIT_CORRUPT (1) // 1 the data is corrupted, and slcr reg are in corrupted state now
|
||||
#define PS7_INIT_TIMEOUT (2) // 2 when a poll operation timed out
|
||||
#define PS7_POLL_FAILED_DDR_INIT (3) // 3 when a poll operation timed out for ddr init
|
||||
#define PS7_POLL_FAILED_DMA (4) // 4 when a poll operation timed out for dma done bit
|
||||
#define PS7_POLL_FAILED_PLL (5) // 5 when a poll operation timed out for pll sequence init
|
||||
|
||||
|
||||
/* Silicon Versions */
|
||||
#define PCW_SILICON_VERSION_1 0
|
||||
#define PCW_SILICON_VERSION_2 1
|
||||
#define PCW_SILICON_VERSION_3 2
|
||||
|
||||
/* This flag to be used by FSBL to check whether ps7_post_config() proc exixts */
|
||||
#define PS7_POST_CONFIG
|
||||
|
||||
/* Freq of all peripherals */
|
||||
|
||||
#define APU_FREQ 666666687
|
||||
#define DDR_FREQ 533333374
|
||||
#define DCI_FREQ 10158731
|
||||
#define QSPI_FREQ 200000000
|
||||
#define SMC_FREQ 10000000
|
||||
#define ENET0_FREQ 125000000
|
||||
#define ENET1_FREQ 10000000
|
||||
#define USB0_FREQ 60000000
|
||||
#define USB1_FREQ 60000000
|
||||
#define SDIO_FREQ 50000000
|
||||
#define UART_FREQ 50000000
|
||||
#define SPI_FREQ 10000000
|
||||
#define I2C_FREQ 111111115
|
||||
#define WDT_FREQ 111111115
|
||||
#define TTC_FREQ 50000000
|
||||
#define CAN_FREQ 10000000
|
||||
#define PCAP_FREQ 200000000
|
||||
#define TPIU_FREQ 200000000
|
||||
#define FPGA0_FREQ 100000000
|
||||
#define FPGA1_FREQ 142857132
|
||||
#define FPGA2_FREQ 50000000
|
||||
#define FPGA3_FREQ 50000000
|
||||
|
||||
|
||||
/* For delay calculation using global registers*/
|
||||
#define SCU_GLOBAL_TIMER_COUNT_L32 0xF8F00200
|
||||
#define SCU_GLOBAL_TIMER_COUNT_U32 0xF8F00204
|
||||
#define SCU_GLOBAL_TIMER_CONTROL 0xF8F00208
|
||||
#define SCU_GLOBAL_TIMER_AUTO_INC 0xF8F00218
|
||||
|
||||
int ps7_config( unsigned long*);
|
||||
int ps7_init();
|
||||
int ps7_post_config();
|
||||
char* getPS7MessageInfo(unsigned key);
|
||||
|
||||
void perf_start_clock(void);
|
||||
void perf_disable_clock(void);
|
||||
void perf_reset_clock(void);
|
||||
void perf_reset_and_start_timer();
|
||||
int get_number_of_cycles_for_delay(unsigned int delay);
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
|
@ -4,7 +4,7 @@
|
|||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#include "ps7_init_gpl.h"
|
||||
#include <asm/arch/ps7_init_gpl.h>
|
||||
|
||||
unsigned long ps7_pll_init_data_3_0[] = {
|
||||
/* START: top */
|
||||
|
|
@ -12666,145 +12666,6 @@ unsigned long ps7_post_config_1_0[] = {
|
|||
|
||||
|
||||
#include "xil_io.h"
|
||||
#define PS7_MASK_POLL_TIME 100000000
|
||||
|
||||
char *getPS7MessageInfo(unsigned key)
|
||||
{
|
||||
char *err_msg = "";
|
||||
switch (key) {
|
||||
case PS7_INIT_SUCCESS:
|
||||
err_msg = "PS7 initialization successful";
|
||||
break;
|
||||
case PS7_INIT_CORRUPT:
|
||||
err_msg = "PS7 init Data Corrupted";
|
||||
break;
|
||||
case PS7_INIT_TIMEOUT:
|
||||
err_msg = "PS7 init mask poll timeout";
|
||||
break;
|
||||
case PS7_POLL_FAILED_DDR_INIT:
|
||||
err_msg = "Mask Poll failed for DDR Init";
|
||||
break;
|
||||
case PS7_POLL_FAILED_DMA:
|
||||
err_msg = "Mask Poll failed for PLL Init";
|
||||
break;
|
||||
case PS7_POLL_FAILED_PLL:
|
||||
err_msg = "Mask Poll failed for DMA done bit";
|
||||
break;
|
||||
default:
|
||||
err_msg = "Undefined error status";
|
||||
break;
|
||||
}
|
||||
|
||||
return err_msg;
|
||||
}
|
||||
|
||||
unsigned long ps7GetSiliconVersion(void)
|
||||
{
|
||||
/* Read PS version from MCTRL register [31:28] */
|
||||
unsigned long mask = 0xF0000000;
|
||||
unsigned long *addr = (unsigned long *)0XF8007080;
|
||||
unsigned long ps_version = (*addr & mask) >> 28;
|
||||
return ps_version;
|
||||
}
|
||||
|
||||
void mask_write(unsigned long add, unsigned long mask, unsigned long val)
|
||||
{
|
||||
unsigned long *addr = (unsigned long *)add;
|
||||
*addr = (val & mask) | (*addr & ~mask);
|
||||
}
|
||||
|
||||
int mask_poll(unsigned long add, unsigned long mask)
|
||||
{
|
||||
volatile unsigned long *addr = (volatile unsigned long *)add;
|
||||
int i = 0;
|
||||
while (!(*addr & mask)) {
|
||||
if (i == PS7_MASK_POLL_TIME)
|
||||
return -1;
|
||||
i++;
|
||||
}
|
||||
return 1;
|
||||
}
|
||||
|
||||
unsigned long mask_read(unsigned long add, unsigned long mask)
|
||||
{
|
||||
unsigned long *addr = (unsigned long *)add;
|
||||
unsigned long val = (*addr & mask);
|
||||
return val;
|
||||
}
|
||||
|
||||
int ps7_config(unsigned long *ps7_config_init)
|
||||
{
|
||||
unsigned long *ptr = ps7_config_init;
|
||||
|
||||
unsigned long opcode; /* current instruction .. */
|
||||
unsigned long args[16]; /* no opcode has so many args ... */
|
||||
int numargs; /* number of arguments of this instruction */
|
||||
int j; /* general purpose index */
|
||||
|
||||
volatile unsigned long *addr; /* some variable to make code readable */
|
||||
unsigned long val, mask; /* some variable to make code readable */
|
||||
|
||||
int finish = -1; /* loop while this is negative ! */
|
||||
int i = 0; /* Timeout variable */
|
||||
|
||||
while (finish < 0) {
|
||||
numargs = ptr[0] & 0xF;
|
||||
opcode = ptr[0] >> 4;
|
||||
|
||||
for (j = 0; j < numargs; j++)
|
||||
args[j] = ptr[j + 1];
|
||||
ptr += numargs + 1;
|
||||
|
||||
switch (opcode) {
|
||||
case OPCODE_EXIT:
|
||||
finish = PS7_INIT_SUCCESS;
|
||||
break;
|
||||
|
||||
case OPCODE_CLEAR:
|
||||
addr = (unsigned long *)args[0];
|
||||
*addr = 0;
|
||||
break;
|
||||
|
||||
case OPCODE_WRITE:
|
||||
addr = (unsigned long *)args[0];
|
||||
val = args[1];
|
||||
*addr = val;
|
||||
break;
|
||||
|
||||
case OPCODE_MASKWRITE:
|
||||
addr = (unsigned long *)args[0];
|
||||
mask = args[1];
|
||||
val = args[2];
|
||||
*addr = (val & mask) | (*addr & ~mask);
|
||||
break;
|
||||
|
||||
case OPCODE_MASKPOLL:
|
||||
addr = (unsigned long *)args[0];
|
||||
mask = args[1];
|
||||
i = 0;
|
||||
while (!(*addr & mask)) {
|
||||
if (i == PS7_MASK_POLL_TIME) {
|
||||
finish = PS7_INIT_TIMEOUT;
|
||||
break;
|
||||
}
|
||||
i++;
|
||||
}
|
||||
break;
|
||||
case OPCODE_MASKDELAY:
|
||||
addr = (unsigned long *)args[0];
|
||||
mask = args[1];
|
||||
int delay = get_number_of_cycles_for_delay(mask);
|
||||
perf_reset_and_start_timer();
|
||||
while ((*addr < delay))
|
||||
;
|
||||
break;
|
||||
default:
|
||||
finish = PS7_INIT_CORRUPT;
|
||||
break;
|
||||
}
|
||||
}
|
||||
return finish;
|
||||
}
|
||||
|
||||
unsigned long *ps7_mio_init_data = ps7_mio_init_data_3_0;
|
||||
unsigned long *ps7_pll_init_data = ps7_pll_init_data_3_0;
|
||||
|
|
@ -12892,40 +12753,3 @@ int ps7_init(void)
|
|||
return PS7_INIT_SUCCESS;
|
||||
}
|
||||
|
||||
/* For delay calculation using global timer */
|
||||
|
||||
/* start timer */
|
||||
void perf_start_clock(void)
|
||||
{
|
||||
*(volatile unsigned int *)SCU_GLOBAL_TIMER_CONTROL = ((1 << 0) | /* Timer Enable */
|
||||
(1 << 3) | /* Auto-increment */
|
||||
(0 << 8) /* Pre-scale */
|
||||
);
|
||||
}
|
||||
|
||||
/* stop timer and reset timer count regs */
|
||||
void perf_reset_clock(void)
|
||||
{
|
||||
perf_disable_clock();
|
||||
*(volatile unsigned int *)SCU_GLOBAL_TIMER_COUNT_L32 = 0;
|
||||
*(volatile unsigned int *)SCU_GLOBAL_TIMER_COUNT_U32 = 0;
|
||||
}
|
||||
|
||||
/* Compute mask for given delay in miliseconds*/
|
||||
int get_number_of_cycles_for_delay(unsigned int delay)
|
||||
{
|
||||
/* GTC is always clocked at 1/2 of the CPU frequency (CPU_3x2x) */
|
||||
return APU_FREQ * delay / (2 * 1000);
|
||||
}
|
||||
|
||||
/* stop timer */
|
||||
void perf_disable_clock(void)
|
||||
{
|
||||
*(volatile unsigned int *)SCU_GLOBAL_TIMER_CONTROL = 0;
|
||||
}
|
||||
|
||||
void perf_reset_and_start_timer(void)
|
||||
{
|
||||
perf_reset_clock();
|
||||
perf_start_clock();
|
||||
}
|
||||
|
|
|
|||
|
|
@ -1,97 +0,0 @@
|
|||
/*
|
||||
* Copyright (c) Xilinx, Inc.
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/*typedef unsigned int u32; */
|
||||
|
||||
/** do we need to make this name more unique ? **/
|
||||
/*extern u32 ps7_init_data[]; */
|
||||
extern unsigned long *ps7_ddr_init_data;
|
||||
extern unsigned long *ps7_mio_init_data;
|
||||
extern unsigned long *ps7_pll_init_data;
|
||||
extern unsigned long *ps7_clock_init_data;
|
||||
extern unsigned long *ps7_peripherals_init_data;
|
||||
|
||||
#define OPCODE_EXIT 0U
|
||||
#define OPCODE_CLEAR 1U
|
||||
#define OPCODE_WRITE 2U
|
||||
#define OPCODE_MASKWRITE 3U
|
||||
#define OPCODE_MASKPOLL 4U
|
||||
#define OPCODE_MASKDELAY 5U
|
||||
#define NEW_PS7_ERR_CODE 1
|
||||
|
||||
/* Encode number of arguments in last nibble */
|
||||
#define EMIT_EXIT() ((OPCODE_EXIT << 4) | 0)
|
||||
#define EMIT_CLEAR(addr) ((OPCODE_CLEAR << 4) | 1) , addr
|
||||
#define EMIT_WRITE(addr, val) ((OPCODE_WRITE << 4) | 2) , addr, val
|
||||
#define EMIT_MASKWRITE(addr, mask, val) ((OPCODE_MASKWRITE << 4) | 3) , addr, mask, val
|
||||
#define EMIT_MASKPOLL(addr, mask) ((OPCODE_MASKPOLL << 4) | 2) , addr, mask
|
||||
#define EMIT_MASKDELAY(addr, mask) ((OPCODE_MASKDELAY << 4) | 2) , addr, mask
|
||||
|
||||
/* Returns codes of PS7_Init */
|
||||
#define PS7_INIT_SUCCESS (0) /* 0 is success in good old C */
|
||||
#define PS7_INIT_CORRUPT (1) /* 1 the data is corrupted, and slcr reg are in corrupted state now */
|
||||
#define PS7_INIT_TIMEOUT (2) /* 2 when a poll operation timed out */
|
||||
#define PS7_POLL_FAILED_DDR_INIT (3) /* 3 when a poll operation timed out for ddr init */
|
||||
#define PS7_POLL_FAILED_DMA (4) /* 4 when a poll operation timed out for dma done bit */
|
||||
#define PS7_POLL_FAILED_PLL (5) /* 5 when a poll operation timed out for pll sequence init */
|
||||
|
||||
/* Silicon Versions */
|
||||
#define PCW_SILICON_VERSION_1 0
|
||||
#define PCW_SILICON_VERSION_2 1
|
||||
#define PCW_SILICON_VERSION_3 2
|
||||
|
||||
/* This flag to be used by FSBL to check whether ps7_post_config() proc exixts */
|
||||
#define PS7_POST_CONFIG
|
||||
|
||||
/* Freq of all peripherals */
|
||||
|
||||
#define APU_FREQ 650000000
|
||||
#define DDR_FREQ 525000000
|
||||
#define DCI_FREQ 10096154
|
||||
#define QSPI_FREQ 200000000
|
||||
#define SMC_FREQ 10000000
|
||||
#define ENET0_FREQ 125000000
|
||||
#define ENET1_FREQ 10000000
|
||||
#define USB0_FREQ 60000000
|
||||
#define USB1_FREQ 60000000
|
||||
#define SDIO_FREQ 50000000
|
||||
#define UART_FREQ 100000000
|
||||
#define SPI_FREQ 10000000
|
||||
#define I2C_FREQ 108333336
|
||||
#define WDT_FREQ 108333336
|
||||
#define TTC_FREQ 50000000
|
||||
#define CAN_FREQ 10000000
|
||||
#define PCAP_FREQ 200000000
|
||||
#define TPIU_FREQ 200000000
|
||||
#define FPGA0_FREQ 100000000
|
||||
#define FPGA1_FREQ 142857132
|
||||
#define FPGA2_FREQ 200000000
|
||||
#define FPGA3_FREQ 50000000
|
||||
|
||||
|
||||
/* For delay calculation using global registers*/
|
||||
#define SCU_GLOBAL_TIMER_COUNT_L32 0xF8F00200
|
||||
#define SCU_GLOBAL_TIMER_COUNT_U32 0xF8F00204
|
||||
#define SCU_GLOBAL_TIMER_CONTROL 0xF8F00208
|
||||
#define SCU_GLOBAL_TIMER_AUTO_INC 0xF8F00218
|
||||
|
||||
int ps7_config(unsigned long *);
|
||||
int ps7_init(void);
|
||||
int ps7_post_config(void);
|
||||
char *getPS7MessageInfo(unsigned key);
|
||||
|
||||
void perf_start_clock(void);
|
||||
void perf_disable_clock(void);
|
||||
void perf_reset_clock(void);
|
||||
void perf_reset_and_start_timer(void);
|
||||
int get_number_of_cycles_for_delay(unsigned int delay);
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
Loading…
Reference in a new issue