Commit graph

21 commits

Author SHA1 Message Date
Tom Rini
83d290c56f SPDX: Convert all of our single license tags to Linux Kernel style
When U-Boot started using SPDX tags we were among the early adopters and
there weren't a lot of other examples to borrow from.  So we picked the
area of the file that usually had a full license text and replaced it
with an appropriate SPDX-License-Identifier: entry.  Since then, the
Linux Kernel has adopted SPDX tags and they place it as the very first
line in a file (except where shebangs are used, then it's second line)
and with slightly different comment styles than us.

In part due to community overlap, in part due to better tag visibility
and in part for other minor reasons, switch over to that style.

This commit changes all instances where we have a single declared
license in the tag as both the before and after are identical in tag
contents.  There's also a few places where I found we did not have a tag
and have introduced one.

Signed-off-by: Tom Rini <trini@konsulko.com>
2018-05-07 09:34:12 -04:00
Masahiro Yamada
00ed0e3ee3 ARM: uniphier: compile pll-base-ld20.c for PXs3
Fix the link error for the combination of
  CONFIG_ARCH_UNIPHIER_LD11=n
  CONFIG_ARCH_UNIPHIER_LD20=n
  CONFIG_ARCH_UNIPHIER_PXS3=y

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-12-12 00:35:59 +09:00
Masahiro Yamada
00aa453ebf ARM: uniphier: remove sLD3 SoC support
This SoC is too old.  It is difficult to maintain any longer.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-08-20 23:05:39 +09:00
Masahiro Yamada
ee8d037ce7 ARM: uniphier: remove SPL support for ARMv8 SoCs
It has been a while since ARM Trusted Firmware supported UniPhier SoC
family.  U-Boot SPL was intended as a temporary loader that runs in
secure world.  It is a maintenance headache to support two different
boot mechanisms.  Secure firmware is realm of ARM Trusted Firmware
and now U-Boot only serves as a non-secure boot loader for UniPhier
ARMv8 SoCs.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-07-26 22:27:15 +09:00
Masahiro Yamada
81afa9c9a3 ARM: uniphier: add more init code for PXs3
Add the boot device table and reset deassertion for eMMC.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-05-17 21:56:17 +09:00
Masahiro Yamada
c21f58548c ARM: uniphier: deassert RST_n of eMMC device for LD11/LD20
For LD11 and LD20 SoCs, the RST_n pin is asserted by default.  If
the EXT_CSD[162], bit[1:0] (RST_n_ENABLE) is fused, the eMMC device
would stay in the reset state until its RST_n pin is deasserted by
software.

Currently, this is cared by an ad-hoc way because the eMMC hardware
reset provider is not supported in U-Boot for now.  This code should
be re-written once the "mmc-pwrseq-emmc" binding is supported.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-02-23 08:37:56 +09:00
Masahiro Yamada
2c2ab3d495 ARM: uniphier: add PXs3 SoC support
Initial support for PXs3 SoC.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-01-22 16:49:34 +09:00
Masahiro Yamada
a8e6300d48 ARM: uniphier: refactor spl_init_board()
Merge init-*.c into a single file using a table of callbacks because
the initialization flow is almost common among SoCs.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-01-18 01:22:30 +09:00
Masahiro Yamada
b61664e230 ARM: uniphier: refactor board_init()
The code here is cluttered due to the switch statement.  Introduce a
table of callbacks to clean up the initialization code across SoCs.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-01-18 01:22:30 +09:00
Masahiro Yamada
78c627cf1f ARM: uniphier: split out UMC clock enable
The clock enable bits for UMC are more SoC-specific than for
the other hardware blocks.  Separate the UMC clocks and the other
clocks for better code reuse across SoCs.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-01-17 09:00:40 +09:00
Masahiro Yamada
c72f4d4c2e ARM: uniphier: add PLL init code for LD11 SoC
- Initialize PLLs (SPL initializes only DPLL to save the precious
   SPL memory footprint)
 - Adjust CPLL/MPLL to the final tape-out frequency
 - Set the Cortex-A53 clock to the maximum frequency since it is
   running at 500MHz (SPLL/4) on startup

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-09-23 01:00:23 +09:00
Masahiro Yamada
682e09ff9f ARM: uniphier: add PLL init code for LD20 SoC
Initialize the DPLL (PLL for DRAM) in SPL, and others in U-Boot
proper.  Split the common code into pll-base-ld20.c for easier
re-use.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-09-19 00:12:26 +09:00
Masahiro Yamada
fcc238baee ARM: uniphier: collect clock/PLL init code into a single directory
Now PLLs for DRAM controller are initialized in SPL, and the others
in U-Boot proper.  Setting up all of them in a single directory will
be helpful when we want to share code between SPL and U-Boot proper.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-09-19 00:06:47 +09:00
Masahiro Yamada
6a3e4274e4 ARM: uniphier: move PLL init code to U-Boot proper where possible
The PLL for the DRAM interface must be initialized in SPL, but the
others can be delayed until U-Boot proper.  Move them from SPL to
U-Boot proper to save the precious SPL memory footprint.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-09-19 00:06:44 +09:00
Masahiro Yamada
667dbcd01d ARM: uniphier: add PH1-LD11 SoC support
This is a low-cost ARMv8 SoC from Socionext Inc.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-05-26 00:37:13 +09:00
Masahiro Yamada
9d0c2ceb35 ARM: uniphier: add PH1-LD20 SoC support
This is the first ARMv8 SoC from Socionext Inc.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-04-24 09:54:08 +09:00
Masahiro Yamada
ea65c98050 ARM: uniphier: drop PH1- prefix from CONFIG options and file names
The current CONFIG names like "CONFIG_ARCH_UNIPHIER_PH1_PRO4" is too
long.  It would not hurt to drop "PH1_" because "UNIPHIER_" already
well specifies the SoC family.  Also, rename files for consistency.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-03-24 01:42:13 +09:00
Tom Rini
da58dec866 Various Makefiles: Add SPDX-License-Identifier tags
After consulting with some of the SPDX team, the conclusion is that
Makefiles are worth adding SPDX-License-Identifier tags too, and most of
ours have one.  This adds tags to ones that lack them and converts a few
that had full (or in one case, very partial) license blobs into the
equivalent tag.

Cc: Kate Stewart <kstewart@linuxfoundation.org>
Signed-off-by: Tom Rini <trini@konsulko.com>
2015-11-10 09:19:52 -05:00
Masahiro Yamada
019df879a9 ARM: uniphier: add ProXstream2 and PH1-LD6b support
The DDR SDRAM initialization code has not been mainlined yet, but
U-Boot proper should work.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2015-09-25 00:59:33 +09:00
Masahiro Yamada
28f40d4a4d ARM: uniphier: add PH1-Pro5 support
The DDR SDRAM initialization code has not been mainlined yet, but
U-Boot proper should work.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2015-09-25 00:59:28 +09:00
Masahiro Yamada
323d1f9d5b ARM: uniphier: allow to enable multiple SoCs
Before this commit, the Kconfig menu in mach-uniphier only allowed us
to choose one SoC to be compiled.  Each SoC has its own defconfig file
for the build-test coverage.  Consequently, some defconfig files are
duplicated with only the difference in CONFIG_DEFAULT_DEVICE_TREE and
CONFIG_{SOC_NAME}=y.

Now, most of board-specific parameters have been moved to device trees,
so it makes sense to include init code of multiple SoCs into a single
image as long as the SoCs have similar architecture.  In fact, some
SoCs of UniPhier family are very similar:
 - PH1-LD4 and PH1-sLD8
 - PH1-LD6b and ProXstream2 (will be added in the upcoming commit)

This commit will be helpful to merge some defconfig files for better
maintainability.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2015-09-25 00:58:38 +09:00