Commit graph

53 commits

Author SHA1 Message Date
Kumar Gala
32049b4048 fsl_pci: Move prototypes into fsl_pci.h and remove explicit externs
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-04-04 10:21:30 -05:00
Kumar Gala
c8514622e2 fsl_pci: Renamed immap_fsl_pci.h to fsl_pci.h
Rename the pci header for FSL HW so we can move some prototypes
in there and stop doing explicit externs

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-04-04 10:21:29 -05:00
Trent Piepho
f62fb99941 Fix all linker script to handle all rodata sections
A recent gcc added a new unaligned rodata section called '.rodata.str1.1',
which needs to be added the the linker script.  Instead of just adding this
one section, we use a wildcard ".rodata*" to get all rodata linker section
gcc has now and might add in the future.

However, '*(.rodata*)' by itself will result in sub-optimal section
ordering.  The sections will be sorted by object file, which causes extra
padding between the unaligned rodata.str.1.1 of one object file and the
aligned rodata of the next object file.  This is easy to fix by using the
SORT_BY_ALIGNMENT command.

This patch has not be tested one most of the boards modified.  Some boards
have a linker script that looks something like this:

*(.text)
. = ALIGN(16);
*(.rodata)
*(.rodata.str1.4)
*(.eh_frame)

I change this to:

*(.text)
. = ALIGN(16);
*(.eh_frame)
*(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))

This means the start of rodata will no longer be 16 bytes aligned.
However, the boundary between text and rodata/eh_frame is still aligned to
16 bytes, which is what I think the real purpose of the ALIGN call is.

Signed-off-by: Trent Piepho <xyzzy@speakeasy.org>
2009-03-20 22:39:12 +01:00
Andy Fleming
feede8b070 Fixup SGMII PHY ids in the device tree
The device tree's PHY addresses need to be fixed up if we're using the
SGMII Riser Card.

The 8572, 8536, and 8544 DS boards were modified to call this function.

Code idea taken from Liu Yu <yu.liu@freescale.com>

Signed-off-by: Andy Fleming <afleming@freescale.com>
2009-02-16 18:05:54 -06:00
Dave Liu
b4983e16d1 fsl-ddr: use the 1T timing as default configuration
For light loaded system, we use the 1T timing to gain better
memory performance, but for some heavily loaded system,
you have to add the 2T timing options to board files.

Signed-off-by: Dave Liu <daveliu@freescale.com>
Acked-by: Andy Fleming <afleming@freescale.com>
2009-01-23 17:03:14 -06:00
Kumar Gala
5af0fdd81c 85xx: Introduce CONFIG_SYS_PCI*_MEM_VIRT for FSL boards
Introduce a new define to seperate out the virtual address that PCI
memory is at from the physical address.  In most situations these are
mapped 1:1.  However any code accessing the bus should use VIRT.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Acked-by: Andy Fleming <afleming@freescale.com>
2009-01-23 17:03:13 -06:00
Kumar Gala
5f91ef6acd 85xx: Convert CONFIG_SYS_PCI*_IO_BASE to _IO_BUS for FSL boards
Use CONFIG_SYS_PCI*_IO_BUS for the bus relative address instead
of _IO_BASE so we are more explicit.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-01-23 17:03:13 -06:00
Kumar Gala
10795f42cb 85xx: Convert CONFIG_SYS_{PCI*,RIO*}_MEM_BASE to _MEM_BUS for FSL boards
Use CONFIG_SYS_{PCI,RIO}_MEM_BUS for the bus relative address instead
of _MEM_BASE so we are more explicit.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Acked-by: Andy Fleming <afleming@freescale.com>
2009-01-23 17:03:13 -06:00
Roy Zang
6d3a10f73e Change PCIE1&2 deciide logic on MPC8544DS board more readable
The IO port selection for MPC8544DS board:
 Port			cfg_io_ports
 PCIE1		0x2, 0x3, 0x4, 0x5, 0x6, 0x7
 PCIE2		0x4, 0x5, 0x6, 0x7
 PCIE3		0x6, 0x7
 This patch changes the PCIE12 and PCIE2 logic more readable.
Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
2009-01-13 16:32:53 -06:00
Roy Zang
9afc2ef030 Fix IO port selection issue on MPC8544DS and MPC8572DS boards
The IO port selection is not correct on MPC8572DS and MPC8544DS board.
 This patch fixes this issue.
 For MPC8572
 Port			cfg_io_ports
 PCIE1		0x2, 0x3, 0x7, 0xb, 0xc, 0xf
 PCIE2		0x3, 0x7
 PCIE3		0x7

For MPC8544
Port			cfg_io_ports
PCIE1		0x2, 0x3, 0x4, 0x5, 0x6, 0x7
PCIE2		0x4, 0x5, 0x6, 0x7
PCIE3		0x6, 0x7
Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
2009-01-13 16:32:52 -06:00
Dave Liu
9b0ad1b1c7 85xx: remove the unused ddr_enable_ecc in the board file
The DDR controller of 8548/8544/8568/8572/8536 processors
have the ECC data init feature, and the new DDR code is
using the feature, and we don't need the way with DMA to
init memory any more.

Signed-off-by: Dave Liu <daveliu@freescale.com>
Acked-by: Andy Fleming <afleming@freescale.com>
2008-12-03 22:44:48 -06:00
Wolfgang Denk
3cbd823116 Coding Style cleanup, update CHANGELOG
Signed-off-by: Wolfgang Denk <wd@denx.de>
2008-11-02 16:14:22 +01:00
Kumar Gala
2dba0dea98 85xx: Convert all fsl_pci_init users to new APIs
Converted ATUM8548, MPC8536DS, MPC8544DS, MPC8548CDS, MPC8568MDS,
MPC8572DS, TQM85xx, and SBC8548 to use fsl_pci_setup_inbound_windows()
and ft_fsl_pci_setup().

With these changes the board code is a bit smaller and we get dma-ranges
set in the device tree for these boards.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Signed-off-by: Andrew Fleming-AFLEMING <afleming@freescale.com>
2008-10-24 17:35:12 -05:00
Haiying Wang
dfb49108e4 Pass dimm parameters to populate populate controller options
Because some dimm parameters like n_ranks needs to be used with the board
frequency to choose the board parameters like clk_adjust etc. in the
board_specific_paramesters table of the board ddr file, we need to pass
the dimm parameters to the board file.

* move ddr dimm parameters header file from /cpu to /include directory.
* add ddr dimm parameters to populate board specific options.
* Fix fsl_ddr_board_options() for all the 8xxx boards which call this function.

Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
2008-10-18 21:54:04 +02:00
Jean-Christophe PLAGNIOL-VILLARD
6d0f6bcf33 rename CFG_ macros to CONFIG_SYS
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
2008-10-18 21:54:03 +02:00
Ben Warren
0b252f50ae Moved initialization of RTL8139 Ethernet controller to board_eth_init()
Affected boards:
	hidden_dragon
	MPC8544DS
	MPC8610HPCN
	R2DPLUS
	TB0229

Removed initialization of the driver from net/eth.c

Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
2008-09-02 21:18:16 -07:00
Andy Fleming
216f2a7156 Add SGMII support for the 8544 DS
The 8544 DS has an optional SGMII Riser card, which uses different PHY
addresses.  Check if we are in SGMII mode, and invoke the SGMII Riser
setup code if so.

Signed-off-by: Andy Fleming <afleming@freescale.com>
Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
2008-09-02 21:18:15 -07:00
Kumar Gala
1167a2fd56 FSL DDR: Convert MPC8544DS to new DDR code.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2008-08-27 11:43:50 -05:00
Kumar Gala
c11528083e mpc85xx: workaround old binutils bug
The recent change to move the .bss outside of the image gives older
binutils (ld from eldk4.1/binutils-2.16) some headache:

ppc_85xx-ld: u-boot: Not enough room for program headers (allocated 3, need 4)
ppc_85xx-ld: final link failed: Bad value

We workaround it by being explicit about the program headers and not
assigning the .bss to a program header.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2008-08-10 22:41:12 +02:00
Kumar Gala
f0ff885ca6 mpc85xx: Update linker scripts for Freescale boards
* Move to using absolute addressing always.  Makes the scripts a bit more
  portable and common
* Moved .bss after the end of the image.  These allows us to have more
  room in the resulting binary image for code and data.
* Removed .text object files that aren't really needed
* Make sure _end is 4-byte aligned as the .bss init code expects this.
  (Its possible that the end of .bss isn't 4-byte aligned)

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2008-07-31 11:33:23 +02:00
Kumar Gala
630d9bfcb5 MPC8544DS: Add ATI Video card support
Add support for using a PCIe ATI Video card on PCIe2.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2008-07-14 20:21:11 -05:00
Kumar Gala
e5852787f0 MPC8544DS: Report board id, board version and fpga version.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2008-07-14 20:15:22 -05:00
Andy Fleming
ab5cda9f88 Remove LBC_CACHE_BASE from 8544 DS
The 8544 DS doesn't have any cacheable Local Bus memories set up.  By mapping
space for some anyway, we were allowing speculative loads into unmapped space,
which would cause an exception (annoying, even if ultimately harmless).
Removing LBC_CACHE_BASE, and using LBC_NONCACHE_BASE for the LBC LAW solves the
problem.

Signed-off-by: Andy Fleming <afleming@freescale.com>
2008-07-14 11:21:33 -05:00
Wolfgang Denk
9b55a25369 Fix some more print() format errors.
Signed-off-by: Wolfgang Denk <wd@denx.de>
2008-07-11 01:16:00 +02:00
Wolfgang Denk
c8a3b109f0 Cleanup out-or-tree building for some boards (.depend)
Signed-off-by: Wolfgang Denk <wd@denx.de>
2008-07-02 23:49:18 +02:00
Becky Bruce
9973e3c614 Change initdram() return type to phys_size_t
This patch changes the return type of initdram() from long int to phys_size_t.
This is required for a couple of reasons: long int limits the amount of dram
to 2GB, and u-boot in general is moving over to phys_size_t to represent the
size of physical memory.  phys_size_t is defined as an unsigned long on almost
all current platforms.

This patch *only* changes the return type of the initdram function (in
include/common.h, as well as in each board's implementation of initdram).  It
does not actually modify the code inside the function on any of the platforms;
platforms which wish to support more than 2GB of DRAM will need to modify
their initdram() function code.

Build tested with MAKEALL for ppc, arm, mips, mips-el. Booted on powerpc
MPC8641HPCN.

Signed-off-by: Becky Bruce <becky.bruce@freescale.com>
2008-06-12 08:50:18 +02:00
Kumar Gala
859a86a25c 85xx/86xx: Move to dynamic mgmt of LAWs
With the new LAW interface (set_next_law) we can move to letting the
system allocate which LAWs are used for what purpose.  This makes life
a bit easier going forward with the new DDR code.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Signed-off-by: Andy Fleming <afleming@freescale.com>
Acked-by: Jon Loeliger <jdl@freescale.com>
Acked-by: Becky Bruce <becky.bruce@freescale.com>
2008-06-11 01:52:23 -05:00
Kumar Gala
ddde74a159 85xx: remove dummy board_early_init_f
A number of board ports have empty version of board_early_init_f
for no reason since we control its via CONFIG_BOARD_EARLY_INIT_F.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2008-06-11 00:36:02 -05:00
Kumar Gala
978e81604c 85xx: Remove unused and unconfigured memory test code.
Remove unused and unconfigured DDR test code from FSL 85xx boards.
Besides, other common code exists.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2008-06-11 00:35:52 -05:00
Wolfgang Denk
53677ef18e Big white-space cleanup.
This commit gets rid of a huge amount of silly white-space issues.
Especially, all sequences of SPACEs followed by TAB characters get
removed (unless they appear in print statements).

Also remove all embedded "vim:" and "vi:" statements which hide
indentation problems.

Signed-off-by: Wolfgang Denk <wd@denx.de>
2008-05-21 00:14:08 +02:00
Ed Swarthout
f97abbfb47 MPC8544DS: decode pcie3 end-point configuration correctly.
Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2008-04-26 00:25:30 +02:00
Jason Wessel
3d36be0300 Remove all the search paths from the .lds files.
The cross compiler is responsible for providing the correct libraries
and the logic to find the linking libraries.

Signed-off-by: Jason Wessel <jason.wessel@windriver.com>
2008-04-17 23:57:32 -07:00
Kumar Gala
f69766e4b5 85xx: Add the concept of CFG_CCSRBAR_PHYS
When we go to 36-bit physical addresses we need to keep the concept of
the physical CCSRBAR address seperate from the virtual one.

For the majority of boards CFG_CCSBAR_PHYS == CFG_CCSRBAR

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2008-03-26 11:43:03 -05:00
Jon Loeliger
a30a549a35 Remove erroneous or extra spd.h #includers.
Many of the spd.h #includers don't need it,
and wanted to have spd_sdram() declared instead.
Since they didn't get that, some also had open
coded extern declarations of it instead or as well.
Fix it all up by using spd_sdram.h where needed.

Signed-off-by: Jon Loeliger <jdl@freescale.com>
2008-03-05 00:17:43 +01:00
Kumar Gala
0f7a3dc95c 85xx: Convert MPC8544 DS to new TLB setup
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2008-01-17 02:05:35 -06:00
Kumar Gala
4bcae9c92a 85xx: convert MPC8544 DS over to use new LAW init code
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2008-01-16 23:21:55 -06:00
Wolfgang Denk
89967841e3 MPC8544DS: fix board Makefile for silent build (with -s)
Signed-off-by: Wolfgang Denk <wd@denx.de>
2008-01-13 19:57:08 +01:00
Wolfgang Denk
64134f0112 Fix linker scripts: add NOLOAD atribute to .bss/.sbss sections
With recent toolchain versions, some boards would not build because
or errors like this one (here for ocotea board when building with
ELDK 4.2 beta):
ppc_4xx-ld: section .bootpg [fffff000 -> fffff23b] overlaps section .bss [fffee900 -> fffff8ab]

For many boards, the .bss section is big enough that it wraps around
at the end of the address space (0xFFFFFFFF), so the problem will not
be visible unless you use a 64 bit tool chain for development. On
some boards however, changes to the code size (due to different
optimizations) we bail out with section overlaps like above.

The fix is to add the NOLOAD attribute to the .bss and .sbss
sections, telling the linker that .bss does not consume any space in
the image.

Signed-off-by: Wolfgang Denk <wd@denx.de>
2008-01-12 20:31:39 +01:00
Kumar Gala
2146cf5682 Reworked FSL Book-E TLB macros to be more readable
The old macros made it difficult to know what WIMGE and perm bits
were set for a TLB entry.  Actually use the bit masks for these items
since they are only a single bit.

Also moved the macros into mmu.h out of e500.h since they aren't specific
to e500.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2008-01-09 16:25:03 -06:00
Kumar Gala
a853d56c59 Use standard LAWAR_TRGT_IF_* defines for LAW setup on 85xx
We already had defines for LAWAR_TRGT_IF_* that we should use
rather than creating new ones.  Also, added some missing defines for
PCIE targets.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2007-12-11 22:34:20 -06:00
Kumar Gala
04db400892 Stop using immap_t on 85xx
In the future the offsets to various blocks may not be in same location.
Move to using CFG_MPC85xx_*_ADDR as the base of the registers
instead of getting it via &immap.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2007-12-11 22:34:20 -06:00
Kumar Gala
f59b55a5b8 Stop using immap_t for guts offset on 85xx
In the future the offsets to various blocks may not be in same location.
Move to using CFG_MPC85xx_GUTS_ADDR as the base of the guts registers
instead of getting it via &immap->im_gur.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2007-12-11 22:34:19 -06:00
Kumar Gala
addce57e2e Update MPC8544DS to use libfdt
Updated the MPC8544DS config to use libfdt and assume use of aliases for
ethernet, pci, and serial for the various fixups that are done.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2007-12-11 22:34:19 -06:00
Wolfgang Denk
409ecdc0bb Fix compiler warnings for PPC systems. Update CHANGELOG.
Signed-off-by: Wolfgang Denk <wd@denx.de>
2007-11-18 16:36:27 +01:00
Kumar Gala
56a9270521 Fix ULI RTC support on MPC8544 DS
The RTC on the M1575 ULI chipset requires a dummy read before
we are able to talk to the RTC.  We accomplish this by adding a
second memory region to the PHB the ULI is on and read from it.

The second region is added to maintain compatiabilty with Linux's
view of the PCI memory map.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2007-09-04 16:00:48 -05:00
Ed Swarthout
f75e89e9b5 ft_board_setup update 85xx/86xx of pci/pcie bus-range property.
pcie is now differentiated from pci.  Add 8641 bus-range updates.

Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com>
2007-09-04 16:00:41 -05:00
Kim Phillips
7608d75f9c support board vendor-common makefiles
if a board/$(VENDOR)/common/Makefile exists, build it.

also add the first such case, board/freescale/common/Makefile, to
handle building board-shared EEPROM, PIXIS, and MDS-PIB code, as
dictated by board configuration.

thusly get rid of alternate build dir errors such as:

FATAL: can't create /work/wd/tmp/u-boot-ppc/board/freescale/mpc8360emds/../common/pq-mds-pib.o: No such file or directory

by putting the common/ mkdir command in its proper place (the common
Makefile). Common bits from existing individual board Makefiles have
been removed.

Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2007-08-29 02:15:46 +02:00
Kumar Gala
d64ee908a1 Update MPC8544 DS PCI memory map
The PCIe bus that the ULI M1575 is connected to has no possible way of
needing more than the fixed amount of IO & Memory space needed by the ULI.

So make it use far less IO & memory space and have it use the shared LAW.  This
free's up a LAW for PCIe1 IO space.  Also reduce the amount of IO space needed
by each bus.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2007-08-16 16:18:45 -05:00
Kumar Gala
ea5877e31e Fix up some fdt issues on 8544DS
It looks like we had a merge issue that duplicated a bit of code
in ft_board_setup.  Also, we need to set CONFIG_HAS_ETH0 to get
the MAC address properly set in the device tree on boot for TSEC1

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2007-08-16 16:18:21 -05:00
Ed Swarthout
837f1ba05c 8544ds PCIE support
PCI1 LAW mapping should use CFG_PCI1_MEM_PHY and not _BASE address.

Enable LBC and ECM errors and clear error registers.

Add tftpflash env var to get uboot from tftp server and flash it.

Add pci/pcie convenience env vars to display register space:
  "run pcie3regs" to see all pcie3 ccsr registers
  "run pcie3cfg" to see all cfg registers
Whitespace cleanup and MPC8544DS.h

Enable CONFIG_INTERRUPTS.

Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com>
Acked-by: Andy Fleming <afleming@freescale.com>
2007-08-14 01:38:40 -05:00