Currently, uniphier_get_soc_type() converts the SoC ID (this is
read from the revision register) to an enum symbol to use it for SoC
identification. Come to think of it, there is no need for the
conversion in the first place. Using the SoC ID from the register
as-is a straightforward way.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
This supports the system reset via PSCI for ARMv7 SoCs.
Because the system reset is not supported on PSCI 0.1, let's define
CONFIG_ARMV7_PSCI_1_0. (it is supported since PSCI 0.2, but there
is no CONFIG to enable it in U-Boot for now.)
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
This outer cache allows to control active ways independently for
each CPU, so this function will be useful to set up active ways
for a specific CPU.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Move this option to Kconfig, renaming it into CONFIG_CACHE_UNIPHIER.
The new option name makes sense enough, and the same as Linux has.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Now, all of these macros are only used in cache-uniphier.c, so
there is no need to export them in a header file.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
The DRAM is available at this point, so setup the temporary stack
and call the C function to reduce the code duplication a bit.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
The System Cache (outer cache) is used not only as L2 cache,
but also as locked SRAM. The functions for turning on/off it
is necessary whether the L2 cache is enabled or not.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
As the sLD3 Boot ROM has a complex page table, it is difficult to
set up the debug UART with enabling it. It will be much easier to
initialize the UART port after switching over to the straight-mapped
page table.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Commit 4b50369fb5 ("ARM: uniphier: create early page table at
run-time") broke the ROM boot mode for PH1-sLD3 SoC, because the
run-time page table creation requires the outer cache register
access but the page table in the sLD3 Boot ROM does not straight-map
virtual/physical addresses.
The idea here is to check the current page table to determine if
it is a straight map table. If not, adjust the outer cache register
base.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Here, the ldr pseudo-instruction falls into the ldr + data set.
The register access by [r1, #offset] produces shorter code.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
If CONFIG_UNIPHIER_L2CACHE_ON is undefined, the L2 cache is never
enabled, so there is no need for v7_outer_cache_disable(). The weak
stub avoids the compile error anyway.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
The UniPhier outer cache (L2 cache on ARMv7 SoCs) can be used as
SRAM by locking ways.
These functions will be used to transfer the trampoline code for SMP
into the locked SRAM.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Unify the range/all operation routines into the common function,
uniphier_cache_maint_common(), and sync code with Linux a bit more.
This reduces the code duplication.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Sync register macros with Linux code. This will be helpful to
develop the counterpart of Linux.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
v7_maint_dcache_all() does not work reliable when build with gcc6,
see: https://bugzilla.redhat.com/show_bug.cgi?id=1318788
While debugging this I learned that v7_maint_dcache_all() is unreliable
when build with gcc5 too when it is marked as noinline.
This commit fixes the reliability issues by replacing the C-code with
the ready to use asm implementation from the kernel.
Given that this code when written as C-code clearly is quite fragile
(also see the existing comments about the C-code being the way it is
to get optimal assembly) and that we have a proven asm alternative,
I believe that this is the best solution.
Note that we actually already had a copy of the kernel's
v7_flush_dcache_all() before this commit in
arch/arm/mach-uniphier/arm32/lowlevel_init.S.
This commit moves that code arch/arm/cpu/armv7/cache_v7_asm.S, renames
it to __v7_flush_dcache_all(), and adds a v7_flush_dcache_all() wrapper
which saves / restores the clobbered registers for use from C-code.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Eliminate the "ph1"_ prefixes from function names because "uniphier_"
describes the SoC familiy better.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
The current CONFIG names like "CONFIG_ARCH_UNIPHIER_PH1_PRO4" is too
long. It would not hurt to drop "PH1_" because "UNIPHIER_" already
well specifies the SoC family. Also, rename files for consistency.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
This function should just return for unknown SoCs rather than writing
unexpected values to registers.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Before adding ARMv8 support, this commit refactors the directory
structure. Move ARMv7 specific files to arch/arm/mach-uniphier/arm32
to avoid a mess by mixture of ARMv7 and ARMv8 code. Also move the
"select CPU_V7" to the lower-level menu because we will have to
select ARM64 instead of CPU_V7 for ARMv8 SoCs.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
