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7 commits

Author SHA1 Message Date
Stefan Roese
f31d38b9ee ppc4xx: Enable 405EX PCIe UTL register configuration
Till now the UTL registers on 405EX were not initialized but left with
their default values. This patch new initializes some of the UTL
registers on 405EX.

Signed-off-by: Stefan Roese <sr@denx.de>
2007-11-16 14:16:54 +01:00
Stefan Roese
5cb4af4791 ppc4xx: Add PCIe endpoint support on Kilauea (405EX)
This patch adds endpoint support for the AMCC Kilauea eval board. It can
be tested by connecting a reworked PCIe cable (only 1x lane singles
connected) to another root-complex.

In this test setup, a 64MB inbound window is configured at BAR0 which maps
to 0 on the PLB side. So accessing this BAR0 from the root-complex will
access the first 64MB of the SDRAM on the PPC side.

Signed-off-by: Stefan Roese <sr@denx.de>
2007-10-31 21:20:50 +01:00
Stefan Roese
d4cb2d1794 ppc4xx: Dynamic configuration of 4xx PCIe mode as root or endpoint mode
This patch adds support for dynamic configuration of PCIe ports for the
AMCC PPC4xx boards equipped with PCIe interfaces. These are the PPC440SPe
boards Yucca & Katmai and the 405EX board Kilauea.

This dynamic configuration is done via the "pcie_mode" environement
variable. This variable can be set to "EP" or "RP" for endpoint or
rootpoint mode. Multiple values can be joined via the ":" delimiter.
Here an example:

pcie_mode=RP:EP:EP

This way, PCIe port 0 will be configured as rootpoint, PCIe port 1 and 2
as endpoint.

Per default Yucca will be configured as:
pcie_mode=RP:EP:EP

Per default Katmai will be configured as:
pcie_mode=RP:RP:REP

Per default Kilauea will be configured as:
pcie_mode=RP:RP

Signed-off-by: Tirumala R Marri <tmarri@amcc.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2007-10-31 21:20:50 +01:00
Stefan Roese
97923770cb ppc4xx: 4xx_pcie: More general cleanup and 405EX PCIe support added
Signed-off-by: Stefan Roese <sr@denx.de>
2007-10-31 21:20:49 +01:00
Stefan Roese
03d344bb6a ppc4xx: Make 440SPe PCIe code more generic to use on different 4xx PPCs (3)
(3) This patch introduces macros like SDRN_PESDR_DLPSET(port) to access
    the SDR registers of the PCIe ports. This makes the overall design
    clearer, since it removed a lot of switch statements which are not
    needed anymore.

    Also, the functions ppc4xx_init_pcie_rootport() and
    ppc4xx_init_pcie_entport() are merged into a single function
    ppc4xx_init_pcie_port(), since most of the code was duplicated.
    This makes maintainance and porting to other 4xx platforms
    easier.

Signed-off-by: Stefan Roese <sr@denx.de>
2007-10-31 21:20:49 +01:00
Stefan Roese
026f711068 ppc4xx: Make 440SPe PCIe code more generic to use on different 4xx PPCs (2)
This patch is the first patch of a series to make the 440SPe PCIe code
usable on different 4xx PPC platforms. In preperation for the new 405EX
which is also equipped with PCIe interfaces.

(2) This patch renames the functions from 440spe_ to 4xx_ with a
    little additional cleanup

Signed-off-by: Stefan Roese <sr@denx.de>
2007-10-31 21:20:49 +01:00
Stefan Roese
c7c6da2302 ppc4xx: Make 440SPe PCIe code more generic to use on different 4xx PPCs (1)
This patch is the first patch of a series to make the 440SPe PCIe code
usable on different 4xx PPC platforms. In preperation for the new 405EX
which is also equipped with PCIe interfaces.

(1) This patch renames the files from 440spe_pcie to 4xx_pcie

Signed-off-by: Stefan Roese <sr@denx.de>
2007-10-31 21:20:48 +01:00
Renamed from cpu/ppc4xx/440spe_pcie.h (Browse further)