Commit graph

88175 commits

Author SHA1 Message Date
Tom Rini
f26c54ddde doc/sphinx/requirements.txt: Bump certifi up
Upgrade certifi to the latest version, to remove e-Tugra from the root
store.

Link: https://groups.google.com/a/mozilla.org/g/dev-security-policy/c/C-HrP1SEq1A?pli=1
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
2023-08-15 18:21:17 +02:00
Tom Rini
832148f675 Merge tag 'u-boot-rockchip-20230814' of https://source.denx.de/u-boot/custodians/u-boot-rockchip
- Add board: rk3568 EmbedFire Lubancat 2
- Fixes for rk3568 clock and pinctrl;
- Fixes for rk3308 clock and uart;
- rk3328 rock64 updates;
- Video fix on veyron board;
2023-08-14 09:11:09 -04:00
Tom Rini
70c45244d9 - fix NULL dereference in vidconsole_measure()
- fix simplefb format for raspberrypi-4b
  - fix typo in Kconfig
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Merge tag 'video-20230814' of https://source.denx.de/u-boot/custodians/u-boot-video

 - fix NULL dereference in vidconsole_measure()
 - fix simplefb format for raspberrypi-4b
 - fix typo in Kconfig
2023-08-14 09:09:23 -04:00
Jonas Karlman
d7009faa09 pinctrl: rockchip: Fix drive and input schmitt on RK3568
On RK3568 most pins have a configurable drive strength of level 0-5 and
some pins level 0-11. When rk3568_set_drive is called with a strength
value above 7 the drv value written to reg may overflow into the write
enable bits, resulting in a bad configuration.

This cause e.g. ethernet PHY on Radxa CM3-IO board not to work after
drive is configured according to the device tree.

  Could not get PHY for ethernet@fe010000: addr 0

Level 6-11 can be configured using a second reg for some pins, however
the drv value is reused resulting in lower 6 bits being written to reg.

Input schmitt is configured in 2-bit fields on RK3568 compared to
earlier generation and 2'b10 should be used to enable input schmitt.

Change to use regmap_update_bits with a rmask to fix the overflow issue
and closer match the linux driver. Bit shift the drv value used for the
second reg to configure drive strength level 6-11. Also write correct
values for input schmitt setting.

Fixes: 1977d746aa ("rockchip: rk3568: add rk3568 pinctrl driver")
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-08-14 11:07:27 +08:00
Meng Li
04cc66c047 rpi: set the correct parameter for simple framebuffer node
When raspberrpi-4b platform  boots up, there are 2 sets of same bootup
log displayed on HDMI monitor screen, it looks like the screen is split
into 2 parts. The root cause is that video format of u-boot is different
from kernel. The fixing "a8r8g8b8" video format is used in u-boot, but
"r5g6b5" video format from framebuffer node is used in kernel image. In
order to avoid weird display status on screen, it needs to set the correct
parameter for simple framebuffer node even if it has existed.

Signed-off-by: Meng Li <Meng.Li@windriver.com>
2023-08-13 23:57:46 +02:00
Jason Wessel
28cd244e84 bcm2835: Add simiple-framebuffer for use with fkms
When the fkms dtb overlay is used only the simple-framebuffer is
presented as a usable video display. So, add "simple-framebuffer"
compatible to enable video driver bcm2835.

Signed-off-by: Jason Wessel <jason.wessel@windriver.com>
Signed-off-by: Meng Li <Meng.Li@windriver.com>
2023-08-13 23:55:57 +02:00
Bin Meng
aba6776a71 video: kconfig: Fix a typo in SPL_VIDEO_REMOVE
Add one space between 'before' and 'loading'.

Signed-off-by: Bin Meng <bmeng@tinylab.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
2023-08-13 23:09:23 +02:00
Bin Meng
01c76f1a64 video: vidconsole: Fix null dereference of ops->measure
At present vidconsole_measure() tests ops->select_font before calling
ops->measure, which would result in a null dereference when the console
driver provides no ops for measure.

Fixes: b828ed7d79 ("console: Allow measuring the bounding box of text")
Signed-off-by: Bin Meng <bmeng@tinylab.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
2023-08-13 23:08:15 +02:00
FUKAUMI Naoki
a73a28b329 rockchip: MAINTAINERS: fix board name for Radxa ROCK 4C+
align with other ROCK series.

Fixes: 2b506407c8 ("rockchip: Add MAINTAINERS entry for Radxa Rock 4C+")
Signed-off-by: FUKAUMI Naoki <naoki@radxa.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-08-12 10:39:51 +08:00
Massimo Pegorer
c71321c7c6 dts: rockchip: rk3308: Avoid warning for serial probe on prereloc
Make device tree complete and consistent for pre relocation phase. Some
nodes are missing, causing warnings to be issued on serial port probing
during pre relocation phase (uclass_get_device_by_phandle_id fails when
called by pinctrl_select_state_full: none of these failures is fatal
nor causing issues). Add to *-u-boot.dtsi all required nodes with the
'bootph-some-ram' attribute.

Signed-off-by: Massimo Pegorer <massimo.pegorer+oss@gmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-08-12 10:37:57 +08:00
Massimo Pegorer
0cd87aac5c clk: rockchip: rk3308: Support reading UART rate and clock registers
Add support to read RK3308 registers used to configure UART clocks, and
thus to get UART rate and baudrate. This fixes clock_get_rate returning
error on serial device probing. Moreover, there is no need anymore to
use 'clock-frequency' property for UART nodes in *-u-boot.dtsi files
for all cases where UART is not inited by U-Boot proper or by SPL o by
TPL code but by a preliminary external boot phase (for Rock PI S, UART
is inited by external TPL).

Signed-off-by: Massimo Pegorer <massimo.pegorer+oss@gmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-08-12 10:37:57 +08:00
Massimo Pegorer
e4c6ccc687 clk: rockchip: rk3308: Fix ordering between masking and shifting
As per definitions of masks and shift offsets in cru_rk3308.h, values
read from registers must be first masked and then shifted. By the way,
this fix is binary invariant, because in all of fixed cases the shift
offset is zero.

Signed-off-by: Massimo Pegorer <massimo.pegorer+oss@gmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-08-12 10:37:57 +08:00
Massimo Pegorer
36adce7372 rockchip: spl: Drop out of scope debug message related to uart init
Debug uart is no more inited in board_init_f function: remove this
debug message from board_init_f. If an earliest-as-possible message
after debug uart initialization is needed, enable DEBUG_UART_ANNOUNCE
Kconfig option, instead.

Signed-off-by: Massimo Pegorer <massimo.pegorer+oss@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-08-12 10:37:32 +08:00
Massimo Pegorer
08e74ac3d9 rockchip: spl: Drop useless call to debug_uart_init
Since commit 0dba45864b ("arm: Init the debug UART") function
debug_uart_init is called in crt files _main before calling
board_init_f. Therefore, there is no need to call it again
inside board_init_f implementation in arm/mach-rockchip/spl.c.

Signed-off-by: Massimo Pegorer <massimo.pegorer+oss@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-08-12 10:37:32 +08:00
Jonas Karlman
520fece4ca rockchip: rk356x-u-boot: Set max-frequency prop in sdhci node
Most board device trees for RK356x set max-frequency = <200000000> in
the sdhci node, some boards like Quartz64 do not. This result in an
error message due to sdhci driver trying to set a clock rate of 0
instead of the max-frequency value.

  rockchip_sdhci_probe clk set rate fail!

Fix this by setting a common max-frequency in rk356x-u-boot.dtsi. A
patch to set default max-frequency of sdhci node in linux is planned.

Also remove the forced status = "okay" for the sdhci and sdmmc0 nodes,
boards already set correct state for these nodes.

Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-08-12 10:35:35 +08:00
Jonas Karlman
9296f9a8d7 clk: rockchip: rk3568: Add dummy support for GMAC speed clocks
Pine64 Quartz64 boards DT reference SCLK_GMAC1_RGMII_SPEED in the
assigned-clocks property of the gmac1 node. This result in a ENOENT
error when driver core tries to set a parent for this clock.

The clock speed in rgmii/rmii mode is changed using clk_set_rate of the
tx_rx clock and not using clk_set_parent of the speed clock.

Add dummy support for SCLK_GMAC1_RGMII_SPEED and similar clocks to clk
driver to allow a driver for gmac node to probe.

Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-08-12 10:35:35 +08:00
Jonas Karlman
ff46cd5631 clk: rockchip: rk3568: Include UART clocks in SPL
The clock driver for RK3568 does not include support for UART clocks in
SPL. This result in the following message with high enough loglevel.

  ns16550_serial serial@fe660000: pinctrl_select_state_full: uclass_get_device_by_phandle_id: err=-19

Fix this by including support for UART clocks in SPL.

Fixes: 4a262feba3 ("rockchip: rk3568: add clock driver")
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Eugen Hristev <eugen.hristev@collabora.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-08-12 10:35:35 +08:00
Jonas Karlman
6da8400d7a clk: rockchip: rk3568: Fix mask for clk_cpll_div_25m_div
The field for clk_cpll_div_25m_div in CRU_CLKSEL_CON81 is 6 bits wide,
not 5 bits wide as currently defined in CPLL_25M_DIV_MASK.

Fix this and the assert so that CPLL_25M can be assigned a 25 MHz rate.

Fixes: 4a262feba3 ("rockchip: rk3568: add clock driver")
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-08-12 10:35:35 +08:00
Damon Ding
acb9812034 clk: rockchip: rk3568: Fix clk selection in rk3568_pwm_get_clk
Fix use of wrong clk selection for CLK_PWM1 on RK3568.

Fixes: 4a262feba3 ("rockchip: rk3568: add clock driver")
Signed-off-by: Damon Ding <damon.ding@rock-chips.com>
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-08-12 10:35:35 +08:00
Anton
6e710897aa rockchip: cru: Enable cpu info support for rk3568
Add cru structure definition in head file to support cpu_info driver.

Series-version: 2
Series-changes: 2
Format the patch header, add commit message and signature.

Signed-off-by: Anton <vao@asu-vei.ru>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2023-08-12 10:28:30 +08:00
Alvaro Fernando García
8300cebcd6 video: avoid build failure on veyron board
533ad9dc avoided an overflow but causes compilation
failure on 32bit boards (eg. veyron speedy)

this commit uses div_u64 which has a fallback codepath
for 32bit platforms

Signed-off-by: Alvaro Fernando García <alvarofernandogarcia@gmail.com>
Tested-by: Simon Glass <sjg@chromium.org>  # chromebook_jerry
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-08-12 10:18:12 +08:00
Andy Yan
bb38db086c rockchip: rk3568: Add EmbedFire Lubancat 2 support
LubanCat2 is a rk3568 based SBC from EmbedFire.

Specification:
- Rockchip rk3568
- LPDDR4/4X 1/2/4/8 GB
- TF scard slot
- eMMC 8/32/64/128 GB
- Gigabit ethernet x 2
- HDMI out
- USB 2.0 Host x 1
- USB 2.0 Type-C OTG x 1
- USB 3.0 Host x 1
- Mini PCIE interface for WIFI/BT module
- M.2 key for 2280 NVME
- 40 pin header

The dts file is sync from linux mainline.

Signed-off-by: Andy Yan <andyshrk@163.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-08-12 10:17:59 +08:00
Jagan Teki
2fa09b455a rockchip: rv1126: Enable fdtoverlay support
Add fdtoverlay_addr_r and enable OF_LIBFDT_OVERLAY for the
use of DT overlay in RV1126.

Signed-off-by: Jagan Teki <jagan@edgeble.ai>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-08-12 10:14:51 +08:00
Peter Robinson
10e38327f0 rockchip: dts: rk3328: rock64: Align spi flash entry
Align the SPI flash entry with upstream. There's no need
to diverge here.

Signed-off-by: Peter Robinson <pbrobinson@gmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-08-12 10:13:44 +08:00
Peter Robinson
080030f276 rockchip: dts: rk3328: Add rng details to u-boot.dtsi
Add the rk3328 rng details to the u-boot.dtsi and
enable the RNG on the Rock64 to be able to provide
a random seed via UEFI.

Signed-off-by: Peter Robinson <pbrobinson@gmail.com>
(Fix typo message)
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2023-08-12 10:13:14 +08:00
Peter Robinson
a13a7a0b45 config: rock64: enable efuse for stable mac addr
Enable the rockchip efuse driver on the Rock64 to
provide a stable ethernet address on the device.

Signed-off-by: Peter Robinson <pbrobinson@gmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-08-12 10:13:06 +08:00
Jonas Karlman
0e2474f550 pci: rockchip: Release resources on failing probe
The PCIe driver for RK3399 is affected by a similar issue that was fixed
for RK35xx in the commit e04b67a7f4 ("pci: pcie_dw_rockchip: release
resources on failing probe").

Resources are not released on failing probe, e.g. regulators may be left
enabled and the ep-gpio may be left in a requested state.

Change to use regulator_set_enable_if_allowed and disable regulators
after failure to keep regulator enable count balanced, ep-gpio is also
released on regulator failure.

Also add support for the vpcie12v-supply, remove unused include and
check return value from dev_read_addr_name.

Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-08-12 09:59:18 +08:00
Quentin Schulz
e5422ea512 rockchip: rk3399: remove duplicate call to regulators_enable_boot_on
An earlier commit makes the common SPL code call
regulators_enable_boot_on and regulators_enable_boot_off before
iterating over possible boot media for U-Boot proper. There is therefore
no need to do this in the rk3399-specific code, so let's remove it.

Cc: Quentin Schulz <foss+uboot@0leil.net>
Tested-by: Xavier Drudis Ferran <xdrudis@tinet.cat>
Signed-off-by: Quentin Schulz <quentin.schulz@theobroma-systems.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2023-08-12 09:58:55 +08:00
Tom Rini
a5899cc69a Merge https://source.denx.de/u-boot/custodians/u-boot-watchdog
- cmd: cyclic: Remove duplicate command name in help text (Alexander)
- ftwdt010: need to reset watchdog in ftwdt010_wdt_start() (Sergei)
2023-08-10 11:40:09 -04:00
Tom Rini
824f104422 Merge https://source.denx.de/u-boot/custodians/u-boot-riscv
+ Add USB host support on VisionFive2 board
+ Enable SPI flash support on VisionFive2 board
+ Enable Random Number Generator in RISC-V QEMU board
+ Display new SBI extension
+ Add SPL_ZERO_MEM_BEFORE_USE Kconfig for jh7110 L2 LIM
  (Loosely-Integrated Memory)
2023-08-10 10:36:43 -04:00
Sergei Antonov
160984ed3a watchdog: ftwdt010: need to reset watchdog in ftwdt010_wdt_start()
ftwdt010_wdt_start() has to call ftwdt010_wdt_reset() after setting-up
the timeout in the same fashion ftwdt010_wdt_expire_now() does it.

Without this patch the "wdt start <ms>" command does not actually start
the watchdog timer until the "wdt reset" command is executed.

Signed-off-by: Sergei Antonov <saproj@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
2023-08-10 08:39:16 +02:00
Alexander Dahl
8ba4eae01d cmd: cyclic: Remove duplicate command name in help text
Function 'cmd_usage()' already prints one command in usage before
printing out the help text given to the U_BOOT_CMD_WITH_SUBCMDS macro.

Wrong previous output:

    Usage:
    cyclic cyclic demo <cycletime_ms> <delay_us> - register cyclic demo function
    cyclic list - list cyclic functions

Signed-off-by: Alexander Dahl <ada@thorsis.com>
Reviewed-by: Stefan Roese <sr@denx.de>
2023-08-10 08:39:11 +02:00
Shengyu Qu
47ed15125c riscv: cpu: jh7110: Select SPL_ZERO_MEM_BEFORE_USE
Add Kconfig item for Starfive JH7110 to select SPL_ZERO_MEM_BEFORE_USE.

Signed-off-by: Bo Gan <ganboing@gmail.com>
Signed-off-by: Shengyu Qu <wiagn233@outlook.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2023-08-10 10:58:55 +08:00
Shengyu Qu
6419f8e9fd riscv: Add SPL_ZERO_MEM_BEFORE_USE implementation
Add the actual support code for SPL_ZERO_MEM_BEFORE_USE and remove
existing Starfive JH7110's L2 LIM clean code, since existing code has
following issues:
 1. Each hart (in the middle of a function call) overwriting its own
    stack and other harts' stacks.
    (data-race and data-corruption)
 2. Lottery winner hart can be doing "board_init_f_init_reserve",
    while other harts are in the middle of zeroing L2 LIM.
    (data-race)

Signed-off-by: Bo Gan <ganboing@gmail.com>
Signed-off-by: Shengyu Qu <wiagn233@outlook.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2023-08-10 10:58:12 +08:00
Shengyu Qu
d365f6646a riscv: Kconfig: Add SPL_ZERO_MEM_BEFORE_USE
Add a Kconfig item to allow SPL to clear stack/GD/malloc area before
using them.

Signed-off-by: Bo Gan <ganboing@gmail.com>
Signed-off-by: Shengyu Qu <wiagn233@outlook.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2023-08-10 10:58:12 +08:00
Shengyu Qu
7d79bed00c configs: starfive: Enable environment in SPI flash support
On Starfive Visionfive 2, the u-boot environment settings are saved to
on-board SPI flash. Enable relative configs by default and set offset
and size according to upstream linux dts.

Signed-off-by: Shengyu Qu <wiagn233@outlook.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2023-08-10 10:58:07 +08:00
Minda Chen
0665621386 configs: riscv: starfive: Add VF2 PCIe USB3 XHCI support
Add XHCI_PCI to enable usb3-host functions.
Also add usb command and keyboard config.

Signed-off-by: Minda Chen <minda.chen@starfivetech.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2023-08-10 10:58:01 +08:00
Minda Chen
eca2d41c68 riscv: starfive: Add SYS_CACHE_SHIFT_6 to enable SYS_CACHELINE_SIZE
Some device driver need SYS_CACHELINE_SIZE macro. Add StarFive
SYS_CACHE_SHIFT_6 to enable it.

Signed-off-by: Minda Chen <minda.chen@starfivetech.com>
Reviewed-by: Bin Meng <bmeng@tinylab.org>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2023-08-10 10:58:01 +08:00
Minda Chen
1037c5ba37 riscv: dts: starfive: Enable pcie0 dts node
In StarFive VF2 board. pcie0 connect to VTI usb controller.
Enable it to support usb host.

Signed-off-by: Minda Chen <minda.chen@starfivetech.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2023-08-10 10:58:01 +08:00
Minda Chen
8d184d4b65 pci: plda: Get correct ECAM offset in multiple PCIe RC case
Get the correct ECAM offset and record the secondary bus
number in Multiple RC case.

Signed-off-by: Minda Chen <minda.chen@starfivetech.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2023-08-10 10:58:01 +08:00
Heinrich Schuchardt
6982e6b046 cmd/sbi: display new extensions
The SBI specification v2.0-rc2 defines new extensions:

* Nested Acceleration Extension (NACL)
* Steal Time Accounting (STA)

Allow the sbi command to display these.

Add missing implementation IDs.

Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2023-08-10 10:57:56 +08:00
Heinrich Schuchardt
1b7de4f9ef riscv: qemu: imply CONFIG_DM_RNG
The EFI_RNG_PROTOCOL is needed for Linux' KASLR.

QEMU can provide a virtio-rng device to emulate a hardware random number
generator which is supported by our virtio_rng driver.

Enabling CONFIG_DM_RNG will enable CONFIG_VIRTIO_RNG and
CONFIG_EFI_RNG_PROTOCOL by default too.

Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2023-08-10 10:57:36 +08:00
Tom Rini
ec58228830 - x86: Fixes for distro booting
- x86: Move some boards to text environment
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Merge tag 'x86-pull-20230809' of https://source.denx.de/u-boot/custodians/u-boot-x86

- x86: Fixes for distro booting
- x86: Move some boards to text environment
2023-08-09 13:17:34 -04:00
Simon Glass
9234b77b9d x86: qemu-x86: Convert to text environment
Use the common include.

Drop everything from the config.h file.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> # Intel Edison
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2023-08-09 23:31:12 +08:00
Simon Glass
3cc4095362 x86: qemu: Add required linux/sizes.h include
These files rely on the config.h file provided this include. Add it
explictily so we can move to a text environment.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> # Intel Edison
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2023-08-09 23:31:12 +08:00
Simon Glass
17b2398534 x86: efi-x86_payload: Convert to text environment
Use the common include.

Drop everything from the config.h file.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> # Intel Edison
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2023-08-09 23:31:12 +08:00
Simon Glass
6ed1cb3552 x86: efi-x86_app: Convert to text environment
Use the common include. Drop the unnecessary changes, since missing
stdio drivers will be ignored.

Drop everything from the config.h file.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> # Intel Edison
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2023-08-09 23:31:12 +08:00
Simon Glass
2d6ebda756 x86: slimbootloader: Convert to text environment
Use the common include along with some additions.

Drop everything from the config.h file.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> # Intel Edison
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
[Drop common env from slimbootloader.env]
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2023-08-09 23:31:12 +08:00
Simon Glass
d9e6318ce9 x86: minnowmax: Convert to text environment
Use the common include along with some additions.

Drop everything from the config.h file.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> # Intel Edison
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2023-08-09 23:31:12 +08:00
Simon Glass
c166298ed2 x86: cougarcanyon2: Convert to text environment
Use the common include. The existing environment includes "vga" but that
is not valid anymore, so let it use vidconsole

Drop everything from the config.h file.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> # Intel Edison
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2023-08-09 23:31:12 +08:00