This commit adds a dump command of DDR PHY parameters of UniPhier
SoC family. It might not be used very often for the regular operation
but it would be useful when something goes wrong with DDR memories.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
This training code provides run-time adjustment of DDR PHY parameters
for stable DDR operation.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
USB is a pretty common feature on exynos 5 board, so it seems sensible
to configure it directly from exynos5-common. As a side-effect this
makes USB available from u-boot on exynos 5420 based boards.
While there enable support for common USB ethernet cards to make it more
likely the default config allows booting for network and enable XHCI on
SMDK5420 which has it defined in the dts but not in its config.
Signed-off-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Fix issue in parse_verify_sum() which swaps handling of env-var and *address.
Move hash_command() argc check earlier.
Cosmetic change on do_hash() variable declaration.
Improved help message for "hash" command.
Signed-off-by: Nikolay Dimitrov <picmaster@mail.bg>
Reviewed-by: Simon Glass <sjg@chromium.org>
When CONFIG_TRACE is disabled, linking fails with:
common/built-in.o:(.data.init_sequence_f+0x8): undefined reference to `trace_early_init'
To fix, wrap the call to trace_early_init() with #ifdef CONFIG_TRACE.
Cc: Simon Glass <sjg@chromium.org>
Cc: Tom Rini <trini@ti.com>
Signed-off-by: Kevin Hilman <khilman@linaro.org>
enable this clock with the following:
clk_usb_otg_enable((void *)HSOTG_BASE_ADDR)
Signed-off-by: Steve Rae <srae@broadcom.com>
Reviewed-by: Felipe Balbi <balbi@ti.com>
Commit "initcall: Improve debugging support" makes sense and indeed
simplifies process of matching initcalls executed with static
disassembly.
Until you are debugging relocation functionality.
Existign output may make you think that at some point execution somehow
returned back to non-relocated area. And there're many reasons/problems
that may provoke this behavior.
In order to make things clear let's add explicit mention in case initall
was actually relocated like this:
--->---
initcall: 810015f8
Relocation Offset is: 0efcf000
Relocating to 8ffcf000, new gd at 8fdced3c, sp at 8fdced20
initcall: 810015b8
initcall: 8ffd093c
initcall: 8ffd0a14
initcall: 81001940 (relocated to 8ffd0940)
initcall: 81001958 (relocated to 8ffd0958)
--->---
Note "unexpected" jump from 0x8f... area to 0x81... area.
Without explanation this raises many questions: execution jumped in
relocated area right as expected and then for some reason returned back?
But I hope comment in brackets will save some time for those curious
developers who are careful enough to catch "unexpected jump to pre-reloc
area" or those unlucky ones who'll have to deal with relocation
debugging.
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Minkyu Kang <mk7.kang@samsung.com>
The current binutils-version.sh expects the version string at the end
of the first line. It turned out to not work with Linaro toolchain:
It has "Linaro 2014.09" at the back.
To fix this issue, let's parse the word right after the close
parenthesis.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Reported-by: York Sun <yorksun@freescale.com>
Acked-by: Dirk Behme <dirk.behme@gmail.com>
Create a fake model table entry with default values, so we can error
check the board rev value once when querying it from the firmware, rather
than error-checking for invalid board rev values every time the model
table is used.
Signed-off-by: Stephen Warren <swarren@wwwdotorg.org>
Add a board rev entry for the new model A+, and augment the board
rev error handling code to be a bit more verbose.
Signed-off-by: Stephen Warren <swarren@wwwdotorg.org>
Model A and CM RPis don't have an on-board USB Ethernet device. Hence,
there's no point setting $usbethaddr based on the device fuses. Use the
model detection code to gate this. Note that the fuses are actually
programmed even on those devices though.
Signed-off-by: Stephen Warren <swarren@wwwdotorg.org>
The few Versatile Express ARMv8 platforms we have may just as
well be switched to generic board from the beginning.
Tested on the ARM foundation model and the in progress support
for the ARMv8 Juno board.
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Acked-by: Steve Rae <srae@broadcom.com>
As agreed with Steve Rae I'm taking over maintenance of the
semihosted, emulated FVP/foundation model Versatile Express
64 bit board variant.
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Acked-by: Steve Rae <srae@broadcom.com>
By rearranging the functions in the semihosting code we can
avoid forward-declaration of the internal static functions.
This puts the stuff in a logical order: read/open/close/len
and then higher-order functions follow at the end.
Cc: Darwin Rambo <drambo@broadcom.com>
Cc: AKASHI Takahiro <takahiro.akashi@linaro.org>
Cc: Mark Hambleton <mark.hambleton@arm.com>
Cc: Tom Rini <trini@ti.com>
Acked-by: Steve Rae <srae@broadcom.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
There is currently a regression when using newer ARM64 compilers
for semihosting: the way long types are inferred from context
is no longer the same.
The semihosting runtime uses long and size_t, so use this
explicitly in the semihosting code and interface, and voila:
the code now works again.
Tested with aarch64-linux-gnu-gcc: Linaro GCC 4.9-2014.09.
Cc: Darwin Rambo <drambo@broadcom.com>
Cc: AKASHI Takahiro <takahiro.akashi@linaro.org>
Cc: Mark Hambleton <mark.hambleton@arm.com>
Cc: Tom Rini <trini@ti.com>
Acked-by: Steve Rae <srae@broadcom.com>
Suggested-by: Mark Hambleton <mark.hambleton@arm.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
The semihosting code exposes internal file handle handling
functions to read(), open(), close() and get the length of
a certain file handle.
However the code using it is only interested in either
reading and entire named file into memory or getting the
file length of a file referred by name. No file handles
are used.
Thus make the file handle code internal to this file by
removing these functions from the semihosting header file
and staticize them.
This gives us some freedom to rearrange the semihosting
code without affecting the external interface.
Cc: Darwin Rambo <drambo@broadcom.com>
Cc: AKASHI Takahiro <takahiro.akashi@linaro.org>
Cc: Mark Hambleton <mark.hambleton@arm.com>
Cc: Tom Rini <trini@ti.com>
Acked-by: Steve Rae <srae@broadcom.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
'+S' is unnecessary because boards of rmobile do not use SPL.
This removes from armadillo-800eva and kzm9g.
Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
MMC of exynos5420 can select SPLL as source clock, so add to support
SPLL in exynos5420_get_mmc_clk(). It was tested on Odroid-XU3 board.
Signed-off-by: Joonyoung Shim <jy0922.shim@samsung.com>
Acked-by: Jaehoon Chung <jh80.chung@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Since commit 4a271cb1b4 (exynos: usb: Switch USB VBUS GPIOs to be
device tree configured) it's not needed for the board specific files to
turn on the VBUS GPIO by hand as that gets done based on device tree. So
drop the redundant code from the SMDK5420 board file.
Signed-off-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Add samsung,vbus-gpio information for the XU3. This allows the usage of
the EHCI controller on the XU3, which is connected to the SMSC LAN9514
chip (usb hub + network).
Signed-off-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Not all exynos 5420 based devices with an LCD also have a parade LVDS
bridge. So make sure compilation doesn't break if CONFIG_LCD is enabled
and CONFIG_VIDEO_PARADE is not.
As a side-effect move the parade functions from the exynos system header
file to its own file.
Signed-off-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Unlike the Peach-Pit board, there is no parade edp to lvds bridge on the
Pi. So drop it from device-tree
Signed-off-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
This patch adds documentation for Odroid-XU3. This documentation is
based on that of Odroid (doc/README-odroid) made by Przemyslaw Marczak.
The documentation includes basic information about boot media layout,
environment, partition layout, and the instruction to burn the u-boot
image to boot media.
Signed-off-by: Hyungwon Hwang <human.hwang@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Kevin Hilman <khilman@linaro.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
This patch adds support for Odroid-XU3.
Signed-off-by: Hyungwon Hwang <human.hwang@samsung.com>
Reviewed-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk>
Tested-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Kevin Hilman <khilman@linaro.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
The media for boot and environment is a board-specific feature, not a
processor-specific. This is same to console port number and some
other addresses. This patch moves the that kinds of configs to each
board-specific files from the common config file for Exynos5420.
Signed-off-by: Hyungwon Hwang <human.hwang@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Kevin Hilman <khilman@linaro.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Intel delivers microcode updates in a microcode.dat file which must be
split up into individual files for each CPU. Add a tool which performs
this task. It can list available microcode updates for each model and
produce a new microcode update in U-Boot's .dtsi format.
Signed-off-by: Simon Glass <sjg@chromium.org>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
This is the follow-on patch to clean up the FSP support codes:
- Remove the _t suffix on the structures defines
- Use __packed for structure defines
- Use U-Boot's assert()
- Use standard bool true/false
- Remove read_unaligned64()
- Use memcmp() in the compare_guid()
- Remove the cast in the memset() call
- Replace some magic numbers with macros
- Use panic() when no valid FSP image header is found
- Change some FSP utility routines to use an fsp_ prefix
- Add comment blocks for asm_continuation and fsp_init_done
- Remove some casts in find_fsp_header()
- Change HOB access macros to static inline routines
- Add comments to mention find_fsp_header() may be called in a
stackless environment
- Add comments to mention init(¶ms) in fsp_init() cannot
be removed
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
(Use 'Link' as the name for the Chromebook Pixel consistently)
Change-Id: I158c88653978ff212334f6d4ffeaf49fa81baefe
There are two standard SD card slots on the Crown Bay board, which
are connected to the Topcliff PCH SDIO controllers. Enable the SDHC
support so that we can use them.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
We don't have driver for the Intel Topcliff PCH Gigabit Ethernet
controller for now, so enable the Intle E1000 NIC support, which
can be plugged into any PCIe slot on the Crown Bay board.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
The Crown Bay board has an SST25VF016B flash connected to the Tunnel
Creek processor SPI controller used as the BIOS media where U-Boot
is stored. Enable this flash support.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Intel Tunnel Creek GPIO register block is compatible with current
ich6-gpio driver, except the offset and content of GPIO block base
address register in the LPC PCI configuration space are different.
Use u16 instead of u32 to store the 16-bit I/O address of the GPIO
registers so that it could support both Ivybridge and Tunnel Creek.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
To avoid having two microcode formats, adjust the build system to support
obtaining the microcode from the device tree, even in the case where it
must be made available before the device tree can be accessed.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Implement minimum required functions for the basic support to
queensbay platform and crownbay board.
Currently the implementation is to call fsp_init() in the car_init().
We may move that call to cpu_init_f() in the future.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Integrate the processor microcode version 1.05 for Tunnel Creek,
CPUID device 20661h.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
There are several problems in the code. The device tree decode is incorrect
in ways that are masked due to a matching bug. Both are fixed. Also
microcode_read_rev() should be inline and called before the microcode is
written.
Note: microcode writing does not work correctly on ivybridge for me. Further
work is needed to resolve this. But this patch tidies up the existing code
so that will be easier.
Signed-off-by: Simon Glass <sjg@chromium.org>
There are new microcode revisions available. Update them. Also change
the format so that the first 48 bytes are not omitted from the device tree
data.
Signed-off-by: Simon Glass <sjg@chromium.org>
