Current Cortina phy driver assumes that firmware upload
is required during initialization and is dependent
on presence of corresponding macros like CONFIG_CORTINA_FW_ADDR
for compilation.
But Cortina phy has provision to store phy firmware in
attached dedicated EEPROM. And boards designed with such
EEPROM does not require firmware upload.
Add CORTINA_NO_FW_UPLOAD option in cortina.c to support
such boards.
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Update get_phy_id() implementation in cortina.c to check
for Cortina_phy by comparing device phy_id with cortina phy_id
instead of relying on presence of CORTINA macros.
This will allow get_phy_id to work with non-cortina phy devices
which might have same phy address as Cortina device but on
different bus.
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
With CONFIG_DM_ETH enabled, aquantia driver compilation fails with
below error. This patch fixes the issue by including dm.h.
drivers/net/phy/aquantia.c: In function ‘aquantia_startup’:
drivers/net/phy/aquantia.c:73:21: error: dereferencing pointer to
incomplete
type ‘struct udevice’
phydev->dev->name);
^~
Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Setting PHY_RTL8211E_PINE64_GIGABIT_FIX forces internal rx/tx delays off
on the PHY, as well as flipping some magical undocumented bits. The
magic number comes from the Pine64 engineering team, presumably as a
proxy from Realtek. This configuration fixes the throughput on some
Pine64 models. Packet loss of up to 60-70% has been observed without
this.
Signed-off-by: Kyle Evans <kevans@FreeBSD.org>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
CONFIG_PHY_ADDR is used for old-style configuration. This makes
impossible changing the PHY address, if multiple boards share a same
config header file (for example include/configs/sunxi-common.h).
Moving this to Kconfig helps overcoming this issue. It's defined
as entry inside PHYLIB section.
After the implemention, moveconfig was run. The issues are:
- edb9315a - CONFIG_PHYLIB is not enabled. Entry is
deleted.
- ds414 - CONFIG_PHYLIB is in incompatible format:
{ 0x1, 0x0 }. This entry is also deleted.
- devkit3250 - The PHY_ADDR is in hex format (0x1F).
Manually CONFIG_PHY_ADDR=31 is added in
the defconfig.
After the changes the suspicious defconfigs passes building.
Signed-off-by: Stefan Mavrodiev <stefan@olimex.com>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
[jagan: rebased on master]
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Fix some style violations in the generic PHY management code.
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Signed-off-by: Mario Six <mario.six@gdsys.cc>
Commit 68e6ecadc5 ("net: phy: marvell 88e151x: Fix handling of RGMII
interface types") fixed the initialization of 88e151x phys, but made it
so that interfaces of type PHY_INTERFACE_MODE_RGMII had both RX and TX
delay bits cleared. The default (like in m88e1111s_config) is to have
both bits set.
Hence, this patch changes the behavior in the PHY_INTERFACE_MODE_RGMII
case so that both bits are set.
Signed-off-by: Mario Six <mario.six@gdsys.cc>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Fix some style violations (mostly wrong indentions) in the Marvell PHY
driver.
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Signed-off-by: Mario Six <mario.six@gdsys.cc>
There is no value to enable phylib without networking support.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Add a b53_reg read/write command which allows inspecting the switch
registers. Because the Broadcom BCM53xx registers have different sizes,
we need to split the accesses in 8, 16, 32, 48 or 64 bits to obtain
expected results.
Reviewed-by: Stefan Roese <sr@denx.de>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
Add a minimalistic Broadcom BCM53xx (roboswitch) switch driver similar
to the Marvell MV88E617x. This takes care of configuring the minimum
amount out of the switch hardware such that each user visible port
(configurable) and the CPU port can forward packets between each other
while preserving isolation with other ports.
This is useful for e.g: the Lamobo R1 board featuring a Broadcom
BCM53125 switch.
Reviewed-by: Stefan Roese <sr@denx.de>
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
Since the return value is a signed int, if the leading MSB of rdreg is a 1,
it will get signed extended and will return a negative value which is an
error even though we read the correct value.
Fixes: dfcc496ed7 ("net: mii: Changes not made by spatch")
Signed-off-by: Chris Brandt <chris.brandt@renesas.com>
Acked-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
This commit allows extended Marvell registers to be read with:
foo > mdio rx FEC 3.10
Reading from bus FEC
PHY at address 0:
3.16 - 0x1063
foo > mdio wx FEC 3.10 0x1011
The above code changes the way ETH connector LEDs blink.
Signed-off-by: Lukasz Majewski <lukma@denx.de>
Reviewed-by: York Sun <york.sun@nxp.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
This patch is ported from the Linux patch posted at [1] and applied to
net tree as commit f1e2400a80ff.
The purpose of this change is to fix the incorrect detection of the link
partner (LP) advertised capabilities which sometimes happens with this PHY
(roughly 1 time in a dozen)
This issue may cause the link to be negotiated at 10Mbps/Full or
10Mbps/Half when 100MBps/Full is actually possible. In some case, the link
is even completely broken and no communication is possible.
To detect the corruption, we must look for a magic undocumented bit in the
WOL bank (hint given by the SoC vendor kernel) but this is not enough to
cover all cases. We also have to look at the LPA ack. If the LP supports
Aneg but did not ack our base code when aneg is completed, we assume
something went wrong.
The detection of a corrupted LPA triggers a restart of the aneg process.
This solves the problem but may take up to 6 retries to complete.
[1] https://lkml.kernel.org/r/20171208110811.30789-1-jbrunet@baylibre.com
Fixes: 8995a96d1d ("net: phy: Add Amlogic Meson GXL Internal PHY support")
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
The Amlogic Meson GXL/GXM families embeds an internal RMII Ethernet PHY.
The PHY acts as a generic PHY but needs a slight configuration right
before it's configuration.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Update the Micrel KSZ90x1 driver for a live tree.
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
All these places seem to inherit the codes from the MMC driver where
a FIXME was put in the comment. However the correct operation after
read should be cache invalidate, not flush.
The underlying drivers should be responsible for the cache operation.
Remove these codes completely.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Reviewed-by: York Sun <york.sun@nxp.com>
Reviewed-by: Joe Hershberger <joe.hershberger@ni.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: York Sun <york.sun@nxp.com>
The old logic always enabled the TX-delay when the phy-mode was set to
PHY_INTERFACE_MODE_RGMII. With this patch we enable the TX delay for
PHY_INTERFACE_MODE_RGMII_ID and PHY_INTERFACE_MODE_RGMII_TXID and
disable it for PHY_INTERFACE_MODE_RGMII.
Based on a similar change made in the Linux Realtek PHY driver
by Martin Blumenstingl <martin.blumenstingl@googlemail.com>.
Signed-off-by: Madalin Bucur <madalin.bucur@nxp.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Acked-by: York Sun <york.sun@nxp.com>
We are now using an env_ prefix for environment functions. Rename these
two functions for consistency. Also add function comments in common.h.
Quite a few places use getenv() in a condition context, provoking a
warning from checkpatch. These are fixed up in this patch also.
Suggested-by: Wolfgang Denk <wd@denx.de>
Signed-off-by: Simon Glass <sjg@chromium.org>
The environment variable "disable_giga" can now be used to disable
1000baseTx on the Micrel's KSZ9031.
Signed-off-by: Sebastien Bourdelin <sebastien.bourdelin@savoirfairelinux.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Added the AFE (Analog Front End) settings for stability to the
Broadcom Cygnus phy. This improves the time take to perform
auto negotiation.
Signed-off-by: Arun Parameswaran <arun.parameswaran@broadcom.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
The correct option is PHY_MICREL_KSZ90X1, but some configs still
select the 9021 and 9031 options, which are deprecated.
Signed-off-by: Alexandru Gagniuc <alex.g@adaptrum.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
There should be no longer be any ksz9000 users that pick up the PHY
driver from ksz8xxx, so remove ksz9000 remnants from there.
Signed-off-by: Alexandru Gagniuc <alex.g@adaptrum.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
The KS8721BL and KSZ9021 PHYs are software-incompatible, yet they
share the same ID. Drivers for bothe PHYs cannot safely coexist, so
the solution was to use #ifdefs to select between the two drivers.
As a result KSZ9031, which has a unique ID, is now caught in the
crossfire. Unless CONFIG_PHY_MICREL_KSZ9031 is defined, the KSZ9031
will not function properly, as some essential configuration code is
ifdef'd-out.
To prevent such situations, move the KSZ9000 drivers to a separate
file, and place them under a separate Kconfig option. While it is
possible to enable both KSZ8000 and KSZ9000 drivers at the same time,
the assumption is that it is highly unlikely for a system to contain
both a KSZ8000 and a KSZ9000 PHY, and that only one of the drivers
will be enabled at any given time.
Signed-off-by: Alexandru Gagniuc <alex.g@adaptrum.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Signed-off-by: Alexandru Gagniuc <alex.g@adaptrum.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
phy_device_create(..) sets the addr of phy_device with a sane value.
There is no need overwrite it.
Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-by: Hannes Schmelzer <oe5hpm@oevsv.at>
Tested-by: Hannes Schmelzer <oe5hpm@oevsv.at>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
As part of preparation for nand DM conversion the new API has been
introduced to remove direct access to nand_info array. So, use it here
instead of accessing to nand_info array directly
Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
Reviewed-by: Joe Hershberger <joe.hershberger@ni.com>
Commit a058052c changed the generic phy_reset() to clear all bits in
BMCR. This inevitably clears the ANEG bit. m88e1145 requires any
change to ANEG bit to be followed by a software reset. This seems to
be different from other PHYs. Implement read-modify-write procedure
for this PHY init.
Signed-off-by: York Sun <york.sun@nxp.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
The 88E1518 code is programming the wrong registers for rgmii-id,
rgmii-txid and rgmii-rxid interfaces.
Since the PHY defaults to rgmii-id, it would appear that the code
was previously only used with sgmii and rgmii-id interfaces.
Tested on 88E1512 PHY in rgmii-id mode which is from the same family
as 88E1518.
Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
This change migrate the following configuration options for Kconfig:
* PHY_GIGE, indicates that a controller (with an appropriate PHY) is
Gigabit capable and enables extra support in the miiutil for
parsing the status of Gigabit PHYs
* adds configuration options for Micrel KSZ9021 and KSZ9031 GbE PHYs,
which previously had to enabled through a board-specific config file
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
At present devices use a simple integer offset to record the device tree
node associated with the device. In preparation for supporting a live
device tree, which uses a node pointer instead, refactor existing code to
access this field through an inline function.
Signed-off-by: Simon Glass <sjg@chromium.org>
The variable 'res' may be unused uninitialized if our call to
mv88e61xx_port_read (register read) fails and we goto the error
handling section. In this case we set 'res' to -EIO to indicate why we
failed.
Cc: Joe Hershberger <joe.hershberger@ni.com>
Cc: Chris Packham <judge.packham@gmail.com>
Cc: Kevin Smith <kevin.smith@elecsyscorp.com>
Cc: Prafulla Wadaskar <prafulla@marvell.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
This patch adds support for having a "fixed-link" to some other MAC
(like some embedded switch-device).
For this purpose we introduce a new phy-driver, called "Fixed PHY".
Fixed PHY works only with CONFIG_DM_ETH enabled, since the fixed-link is
described with a subnode below ethernet interface.
Most ethernet drivers (unfortunately not all are following same scheme
for searching/attaching phys) are calling "phy_connect(...)" for getting
a phy-device.
At this point we link in, we search here for a subnode called "fixed-
link", once found we start phy_device_create(...) with the special phy-
id PHY_FIXED_ID (0xa5a55a5a).
During init the "Fixed PHY" driver has registered with this id and now
gets probed, during probe we get all the details about fixed-link out of
dts, later on the phy reports this values.
Signed-off-by: Hannes Schmelzer <hannes.schmelzer@br-automation.com>
Signed-off-by: Hannes Schmelzer <oe5hpm@oevsv.at>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
At present devices use a simple integer offset to record the device tree
node associated with the device. In preparation for supporting a live
device tree, which uses a node pointer instead, refactor existing code to
access this field through an inline function.
Signed-off-by: Simon Glass <sjg@chromium.org>
Provide the necessary Kconfig symbols so that PHYLIB support may be
enabled in Kconfig, as opposed to needing to #define these symbols in
C source headers.
BITBANGMII and MV88E6352_SWITCH are left out of the PHYLIB submenu as
they don't seem to explicitly depend on it (i.e. they do not use the
phy_driver class).
Signed-off-by: Alexandru Gagniuc <alex.g@adaptrum.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Add support for programmable MAC impedance configuration and
fix typo in DT impedance parameters names.
Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
Tested-by: Lokesh Vutla <lokeshvutla@ti.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Commit 79e86ccb37 "vitesse: remove duplicated
argument to ||" correctly removed a redundant check.
However, I believe that the original code was simply wrong, and should have
been checking against RGMII_ID.
To fix this and avoid similar problems in the future, use the
phy_interface_is_rgmii helper function.
Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
This device also works with the 88E1518 code, so we just adjust
the UID mask accordingly.
Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
The mask for the 88E1510 meant that the 88E1518 code would never be
used.
Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
There is code that is specifically for RGMII_TXID interface, but this
will never get used because the code checks that the RGMII interface
is RGMII_ID to RGMII_RXID; RGMII_TXID is after this.
To fix this and avoid similar problems in the future, use the
phy_interface_is_rgmii helper function.
Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Add support for Marvell 88E1680 Integrated Octal
10/100/1000 Mbps Energy Efficient Ethernet Transceiver.
Signed-off-by: Dirk Eibach <dirk.eibach@gdsys.cc>
Signed-off-by: Mario Six <mario.six@gdsys.cc>
Reviewed-by: Stefan Roese <sr@denx.de>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Signed-off-by: Stefan Roese <sr@denx.de>
This patch adds support for SMSC LAN8742 in phylib
Signed-off-by: Michael Kurz <michi.kurz@gmail.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
This patch fixes incorrect pointer on offset device in device tree blob.
When using with the component "Ethernet 1G/2.5G BASE-X PCS/PMA or SGMII"
it does not understand what type is XAE_PHY_TYPE_1000BASE_X and trying
to change frequency.
Signed-off-by: Kamensky Ivan <kamensky.ivan@mail.ru>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
The VSC8601 config tried to add an RGMII skew based on #defines that
no config defines. That's quite an ugly way to do it. Since the skew
is only needed on RGMII interfaces, check the interface mode at
runtime, and apply the settings accordingly.
Tested on custom board with AM3352 SOC and VSC801 PHY.
Signed-off-by: Alexandru Gagniuc <alex.g@adaptrum.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Commit 525d187af ("net: phy: Optionally force master mode for RTL PHY")
added the define to force the PHY into master mode. Unfortunatly this is
an all or nothing switch. So it applies to either all PHY's or no PHY's.
The bug that define tried to solve was a buggy PLL in the RTL8211C only.
The Olimex OLinuXino Lime2 has gotten an upgrade where the PHY was
replaced with an RTL8211E. With this define however, both lime2 boards
are either forced to master mode or not. We could of course have a
binary for each board, but the following patch fixes this by adding a
'quirk' to the flags to the rtl8211b and rtl8211c only. It is now
possible to force master mode, but only have it apply to the rtl8211b
and rtl8211c.
Signed-off-by: Olliver Schinagl <oliver@schinagl.nl>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
All internal defines in the realtek phy are with a small X,
except MIIM_RTL8211X_CTRL1000T_MASTER. Make this more consistent
Signed-off-by: Olliver Schinagl <oliver@schinagl.nl>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
The BIT macro is the preferred method to set bits.
This patch adds the bit macro and converts bit invocations.
Signed-off-by: Olliver Schinagl <oliver@schinagl.nl>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Fix the following error, the $ret variable handling must
be part of the loop, while due to the missing parenthesis
it was not.
drivers/net/phy/micrel.c: In function ‘ksz9021_of_config’:
drivers/net/phy/micrel.c:303:2: warning: this ‘for’ clause does not guard... [-Wmisleading-indentation]
for (i = 0; i < ARRAY_SIZE(ofcfg); i++)
^~~
drivers/net/phy/micrel.c:305:3: note: ...this statement, but the latter is misleadingly indented as if it is guarded by the ‘for’
if (ret)
^~
drivers/net/phy/micrel.c: In function ‘ksz9031_of_config’:
drivers/net/phy/micrel.c:411:2: warning: this ‘for’ clause does not guard... [-Wmisleading-indentation]
for (i = 0; i < ARRAY_SIZE(ofcfg); i++)
^~~
drivers/net/phy/micrel.c:413:3: note: ...this statement, but the latter is misleadingly indented as if it is guarded by the ‘for’
if (ret)
^~
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Like [1], reset the FLP burst timing for the KSZ9031 to the 16ms
specified by the IEEE802.3 standard from the chip's default of 8ms.
For more details, see the "Auto-Negotiation Timing" section of the
KSZ9031RNX datasheet.
[1] https://patchwork.kernel.org/patch/6558371/
Signed-off-by: Ash Charles <ash.charles@savoirfairelinux.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
On some boards these switches are wired directly into a SERDES
interface on another Ethernet MAC. Add the ability to specify
these kinds of boards using CONFIG_MV88E61XX_FIXED_PORTS which defines
a bit mask of these fixed ports.
Signed-off-by: Chris Packham <judge.packham@gmail.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
The Marvell Link Street mv88e60xx is a series of FastEthernet switch
chips, some of which also support Gigabit ports. It is similar to the
mv88e61xx series which support Gigabit on all ports.
The main difference is the number of ports. Which affects the
PORT_COUNT define and the size of the mask passed to
mv88e61xx_port_set_vlan().
Other than that it's just a matter of adding the appropriate chip
IDs.
Signed-off-by: Chris Packham <judge.packham@gmail.com>
Cc: Joshua Scott <joshua.scott@alliedtelesis.co.nz>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
In the current driver implementation, config() callback is common
for AR8035 and AR8031 phy. In config() callback, driver tries to
configure MMD Access Control Register and MMD Access Address Data
Register unconditionally for both phy versions which leads to
auto negotiation failure in AM335x EVMsk second port which uses
AR8031 Giga bit RGMII phy. Fixing this by adding separate config
for AR8031 phy.
Reviewed-by: Sekhar Nori <nsekhar@ti.com>
Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
This adds support for internal delay on RX and TX on RGMII interface for the
AR8035 phy.
This is basically the same Linux driver do. Tested on a Zynq Zturn board (for
which u-boot support in is my tree; first patch waiting ML approval)
Signed-off-by: Andrea Merello <andrea.merello@gmail.com>
Reviewed-by: Marek Vasut <marex@denx.de>
Acked-by: Marek Vasut <marex@denx.de>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Now, arch/${ARCH}/include/asm/errno.h and include/linux/errno.h have
the same content. (both just wrap <asm-generic/errno.h>)
Replace all include directives for <asm/errno.h> with <linux/errno.h>.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
[trini: Fixup include/clk.]
Signed-off-by: Tom Rini <trini@konsulko.com>
If the functions passed to the registration function are not in the same
C file (extern) then spatch will not handle the dependent changes.
Make those changes manually.
Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
For the 4xx related files:
Acked-by: Stefan Roese <sr@denx.de>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
This patch adds support for aquantia AQR106/107 PHY.
Signed-off-by: Mingkai Hu <mingkai.hu@nxp.com>
Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Commit a058052c "net: phy: do not read configuration register on reset",
changes the behaviour of the phy_reset function such that the state of
the BMCR register is not preserved during reset.
Change the config function for the m88e1310 so that it does not do a
reset after configuring auto-negotiation.
Signed-off-by: Nathan Rossi <nathan@nathanrossi.com>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Cc: Michal Simek <michal.simek@xilinx.com>
Cc: Stefan Roese <sr@denx.de>
Acked-by: Michal Simek <michal.simek@xilinx.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Reviewed-by: Stefan Roese <sr@denx.de>
This patch adds a phy driver for the Micrel KSZ886x switches.
Similarly to the KSZ8895, SoC MAC is directly connected to the switch
MAC on the switch CPU port, so the link to the switch is always up.
KSZ886x switches can be used in the following configuration modes:
- Unmanaged mode with config stored in external EEPROM
- Managed mode over SPI
- Managed mode over I2C
- Managed mode over mdio/mdc (aka MIIM or SMI)
This patch supports only unmanaged and MIIM modes.
Based on Micrel KSZ886x driver from Linux kernel and
Micrel KSZ8895 driver from U-Boot.
Verified with the KSZ8863MLL.
Signed-off-by: Alexey Firago <alexey_firago@mentor.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
nand_info[] is now an array of pointers, with the actual mtd_info
instance embedded in struct nand_chip.
This is in preparation for syncing the NAND code with Linux 4.6,
which makes the same change to struct nand_chip. It's in a separate
commit due to the large amount of changes required to accommodate the
change to nand_info[].
Signed-off-by: Scott Wood <oss@buserror.net>
The code assumed that if the interface is not RGMII configured
then it must be SGMII configured. This device has the ability
to support most of the MII interfaces. Therefore add the
helper for SGMII and only configure the device if the interface is
configured for SGMII.
Signed-off-by: Dan Murphy <dmurphy@ti.com>
Reviewed-by: Mugunthan V N <mugunthanvnm@ti.com>
Reviewed-by: Michal Simek <michal.simek@xilinx.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Move the phy_interface_is_rgmii to the phy.h
file for all phy's to be able to use the API.
This now aligns with the Linux kernel based on
commit e463d88c36d42211aa72ed76d32fb8bf37820ef1
Signed-off-by: Dan Murphy <dmurphy@ti.com>
Reviewed-by: Mugunthan V N <mugunthanvnm@ti.com>
Reviewed-by: Michal Simek <michal.simek@xilinx.com>
Tested-by: Mugunthan V N <mugunthanvnm@ti.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Not all devices use the same internal delay or fifo depth.
Add the ability to set the internal delay for rx or tx and the
fifo depth via the devicetree. If the value is not set in the
devicetree then set the delay to the default.
If devicetree is not used then use the default defines within the
driver.
Signed-off-by: Dan Murphy <dmurphy@ti.com>
Tested-by: Mugunthan V N <mugunthanvnm@ti.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
The previous mv88e61xx driver was a driver for configuring the
switch, but did not integrate with the PHY/networking system, so
it could not be used as a PHY by U-boot. This is a complete
rework to support this device as a PHY.
Signed-off-by: Kevin Smith <kevin.smith@elecsyscorp.com>
Acked-by: Prafulla Wadaskar <prafulla@marvell.com>
Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Cc: Stefan Roese <sr@denx.de>
Cc: Marek Vasut <marex@denx.de>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
No boards are using this driver. Remove in preparation for a new
driver with integrated PHY support.
Signed-off-by: Kevin Smith <kevin.smith@elecsyscorp.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Cc: Prafulla Wadaskar <prafulla@marvell.com>
Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
Cc: Stefan Roese <sr@denx.de>
Cc: Marek Vasut <marex@denx.de>
The patch
"net: phy: do not read configuration register on reset"
(sha1: a058052c35)
was causing regression on zynq zc702 board where Marwell 88e1118
phy was resetted after negotiation was setup.
Phy reset is done pretty early in phy_connect_dev() and doens't need to
be called again in phy code.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Propagate error code from genphy_update_link() to phy startup().
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Acked-by: Stephen Warren <swarren@nvidia.com>
Add support of SGMII to TI phy dp838367
Enable the SGMII and PCS settings in phy
control, CFG2 and BIST registers
Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
The RTL8211B_driver structure in drivers/net/phy/realtek.c contains a
wrong PHY ID (0x1cc910 instead of 0x1cc912) in the uid field.
The lowest four bits of the PHY ID encode the chip revision (B+C/D/E/F)
of the RTL8211 and the code originally applied a mask of 0xfffff0 to
the PHY ID, so that matching the PHY ID to the appropriate driver code
was only done on the chip type (RTL8211), but not on a specific
revision.
After introduction of support for the RTL8211E, which needed another
startup function than the older chip revisions, commit
4220504767 changed the mask to 0xffffff
to make the chip revision relevant for the match, but didn't provide
the now-relevant lower bits of the uid field for the RTL8211B/C.
Fix this by setting the full PHY ID in the RTL8211B_driver uid field.
Fixes: 4220504767 ("net/phy: realtek: Fix the PHY ID mask to ensure the correct Realtek PHY is detected")
Signed-off-by: Karsten Merker <merker@debian.org>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
This patch introduces CONFIG_RTL8211X_PHY_FORCE_MASTER. If this
define is set, RTL8211x PHYs (except for the RTL8211F) will have their
1000BASE-T master/slave autonegotiation disabled and forced to master
mode.
This is helpful for PHYs like the RTL8211C which produce unstable links
in slave mode. Such problems have been found on the A20-Olimex-SOM-EVB
and A20-OLinuXino-Lime2.
There is no proper way to identify affected PHYs in software as the
RTL8211C shares its UID with the RTL8211B. Thus, this fix requires
the introduction of an #ifdef.
CC: fradav@gmail.com
CC: merker@debian.org
CC: hdegoede@redhat.com
CC: ijc@hellion.org.uk
CC: joe.hershberger@ni.com
Signed-off-by: Michael Haas <haas@computerlinguist.org>
Tested-by: Karsten Merker <merker@debian.org>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
In commit <a058052c358c> [net: phy: do not read configuration register on
reset], phy_reset() will clear the BMCR register. Bit 12(AUTO_NEGOTIATION)
is cleared too. It causes auto-negotiation timeout error on Atheros's
PHY AR8033.
To fix this problem, genphy_config_aneg() and genphy_restart_aneg()
needs to be called in ar8035_config() to enable and restart
auto-negotiation.
Signed-off-by: Alison Wang <alison.wang@nxp.com>
Acked-by: Stefan Agner <stefan@agner.ch>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
The problem with current implementation is that SPDDONE bit is 1
but link bit is zero. That's why phydev->link is setup to 0
which ending up in driver failure that link is not up.
Log:
Zynq> dhcp
ethernet@e000b000 Waiting for PHY auto negotiation to complete.......
done
ethernet@e000b000: No link.
There is at least 1ms delay between spddone bit and link up.
Use genphy_read_status() instead of realtek implemenation which is
working with page 11. Linux driver is also using generic implementation.
Signed-off-by: Michal Simek <monstr@monstr.eu>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
With commit a058052c [net: phy: do not read configuration register on
reset], phy_reset() will clear the BMCR register. Resulting in bit 12
being cleared (A/N enable). This leads to autonegotiation link problems,
at least on the Marvell Armada ClearFog board. I suspect that other
boards using this driver will be affected as well.
At the of m88e1111s_config(), phy_reset() is called. This is not needed
for the PHY to load the changed configuration, as phy_reset() is called
a few lines before already. So lets call genphy_restart_aneg() here
instead to start the AN correctly.
Tested on clearfog.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Stefan Agner <stefan@agner.ch>
Cc: Hao Zhang <hzhang@ti.com>
Cc: Michal Simek <monstr@monstr.eu>
Cc: Andy Fleming <afleming@gmail.com>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Instead of coding the soft PHY reset function multiple times in marvell.c,
lets call the common phy_reset() function from phy.c.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Stefan Agner <stefan@agner.ch>
Cc: Hao Zhang <hzhang@ti.com>
Cc: Michal Simek <monstr@monstr.eu>
Cc: Andy Fleming <afleming@gmail.com>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
When Micrel phy is selected without CONFIG_PHY_MICREL_KSZ9031 or
CONFIG_PHY_MICREL_KSZ9021 there is a build error. Fixing this
by adding proper ifdefs
drivers/net/phy/micrel.c:370:39: error: array type has incomplete element type
static const struct ksz90x1_reg_field ksz9031_ctl_grp[] =
^
drivers/net/phy/micrel.c:372:39: error: array type has incomplete element type
static const struct ksz90x1_reg_field ksz9031_clk_grp[] =
^
drivers/net/phy/micrel.c: In function ‘ksz9031_of_config’:
drivers/net/phy/micrel.c:377:23: error: array type has incomplete element type
struct ksz90x1_ofcfg ofcfg[] = {
^
drivers/net/phy/micrel.c:379:13: error: ‘ksz90x1_rxd_grp’ undeclared (first use in this function)
{ MII_KSZ9031_EXT_RGMII_RX_DATA_SKEW, 2, ksz90x1_rxd_grp, 4 },
^
drivers/net/phy/micrel.c:379:13: note: each undeclared identifier is reported only once for each function it appears in
drivers/net/phy/micrel.c:380:13: error: ‘ksz90x1_txd_grp’ undeclared (first use in this function)
{ MII_KSZ9031_EXT_RGMII_TX_DATA_SKEW, 2, ksz90x1_txd_grp, 4 },
^
drivers/net/phy/micrel.c:386:3: warning: implicit declaration of function ‘ksz90x1_of_config_group’ [-Wimplicit-function-declaration]
ret = ksz90x1_of_config_group(phydev, &(ofcfg[i]));
^
drivers/net/phy/micrel.c:377:23: warning: unused variable ‘ofcfg’ [-Wunused-variable]
struct ksz90x1_ofcfg ofcfg[] = {
^
drivers/net/phy/micrel.c: At top level:
drivers/net/phy/micrel.c:370:39: warning: ‘ksz9031_ctl_grp’ defined but not used [-Wunused-variable]
static const struct ksz90x1_reg_field ksz9031_ctl_grp[] =
^
drivers/net/phy/micrel.c:372:39: warning: ‘ksz9031_clk_grp’ defined but not used [-Wunused-variable]
static const struct ksz90x1_reg_field ksz9031_clk_grp[] =
^
scripts/Makefile.build:277: recipe for target 'drivers/net/phy/micrel.o' failed
make[1]: *** [drivers/net/phy/micrel.o] Error 1
Makefile:1201: recipe for target 'drivers/net/phy' failed
make: *** [drivers/net/phy] Error 2
make: *** Waiting for unfinished jobs....
Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Cortina phy cannot support soft reset, this commit implements probe
for Cortina PHY to tell phylib to skip phy soft reset by setting
PHY_FLAG_BROKEN_RESET in flags.
Signed-off-by: Shaohui Xie <Shaohui.Xie@nxp.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Current driver always performs a phy soft reset when connecting the phy
device, but soft reset is not always supported by a phy device, so
introduce a quirk PHY_FLAG_BROKEN_RESET to let such a phy device to skip
soft reset. This commit uses 'flags' of phy device structure to store the
quirk.
Signed-off-by: Shaohui Xie <Shaohui.Xie@nxp.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
The picoseconds to register value divisor(ps_to_regval) should be 60 and not
200. Linux has KSZ9031_PS_TO_REG defined to be 60 as well. 60 is the correct
divisor because the 4-bit skew values are defined from 0x0000(-420ps) to
0xffff(480ps), increments of 60.
For example, a DTS skew value of 420, represents 0ps delay, which should be 0x7.
With the previous divisor of 200, it would result in 0x2, which represents a
-300ps delay.
With this patch, ethernet on the SoCFPGA DE0 Atlas is now able to work with
1Gb ethernet.
References:
http://www.micrel.com/_PDF/Ethernet/datasheets/KSZ9031RNX.pdf -> page 26
Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
Acked-by: Marek Vasut <marex@denx.de>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Use the 'autoneg' flag available in phydev when checking if
autoneg is in use.
The previous implementation was checking directly in the PHY
if autoneg was supported. Some PHYs will report that autoneg
is supported, even when it is disabled. Thus it is not possible
to use that bit to determine if autoneg is currently in use or
not.
Signed-off-by: Alexandre Messier <amessier@tycoint.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
When configuring a PHY in fixed (forced) link mode, in order for
the changes to be applied, either one of these conditions must
be triggered:
1- PHY is reset
2- Autoneg is restarted
3- PHY transitions from power-down to power-up
Neither of these is currently done, so effectively the fixed link
configuration is not applied in the PHY.
Fix this by setting the Autoneg restart bit.
Signed-off-by: Alexandre Messier <amessier@tycoint.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Micrel PHYs KSZ8021/31 and KSZ8081 have a feature where MDIO address 0
is considered as a broadcast address; the PHY will respond even if it
is not its configured (pinstrapped) address. This feature is enabled
by default.
The Linux kernel disables that feature at initialisation, but not
before it probes the MDIO bus. This causes an issue, because a PHY
at address 3 will be discovered at addresses 0 and 3, but will then
only respond at address 3. Because Linux attaches the first PHY it
discovers on 'eth0', it will attach the PHY from address 0, which
will never answer again.
Fix the issue by disabling the broadcast feature in U-Boot, before
Linux is started.
Signed-off-by: Alexandre Messier <amessier@tycoint.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
This new function will allow MAC drivers to override supported
capabilities of the phy. It is required when MAC cannot handle all
speeds supported by phy.
For example phy supports up-to 1Gb connections while MAC may only work
in modes up to 100 or even 10 Mbit/sec.
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
of_set_phy_supported allows overwiting hardware capabilities of
a phy with values from the devicetree. This does not work with
the genphy driver though because the genphys config_init function
will overwrite all values adjusted by of_set_phy_supported. Fix
this by initialising the genphy features in the phy_driver struct
and in config_init just limit the features to the ones the hardware
can actually support. The resulting features are a subset of the
devicetree specified features and the hardware features.
This is a copy of the patch from Linux kernel, see
http://git.kernel.org/cgit/linux/kernel/git/torvalds/linux.git/commit/?id=c242a47238fa2a6a54af8a16e62b54e6e031d4bc
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
When a Gigabit PHY device is connected to a 10/100Mbits capable Ethernet
MAC, the driver will restrict the phydev->supported modes to mask off
Gigabit. If the Gigabit PHY comes out of reset with the Gigabit features
set by default in MII_CTRL1000, it will keep advertising these feature,
so by the time we call genphy_config_advert(), the condition on
phydev->supported having the Gigabit features on is false, and we do not
update MII_CTRL1000 with updated values, and we keep advertising Gigabit
features, eventually configuring the PHY for Gigabit whilst the Ethernet
MAC does not support that.
This patches fixes the problem by ensuring that the Gigabit feature bits
are always cleared in MII_CTRL1000, if the PHY happens to be a Gigabit
PHY, and then, if Gigabit features are supported, setting those and
updating MII_CTRL1000 accordingly.
This is a copy of patch from Linux kernel, see
http://git.kernel.org/cgit/linux/kernel/git/torvalds/linux.git/commit/?id=5273e3a5ca94fbeb8e07d31203069220d5e682aa
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
