Commit graph

1059 commits

Author SHA1 Message Date
Joe Hershberger
22f68524f8 sandbox: eth: Add support for using the 'lo' interface
The 'lo' interface on Linux doesn't support thinks like ARP or
link-layer access like we use to talk to a normal network interface.
A higher-level network API must be used to access localhost.

As written, this interface is limited to not supporting ICMP since the
API doesn't allow the socket to be opened for all IP traffic and be able
to receive at the same time. UDP is far more useful to test with, so it
was selected over ICMP. Ping won't work, but things like TFTP should
work.

Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2015-04-18 11:11:14 -06:00
Joe Hershberger
a346ca7902 sandbox: eth: Add a bridge to a real network for sandbox
Implement a bridge between U-Boot's network stack and Linux's raw packet
API allowing the sandbox to send and receive packets using the host
machine's network interface.

This raw Ethernet API requires elevated privileges.  You can either run
as root, or you can add the capability needed like so:

sudo /sbin/setcap "CAP_NET_RAW+ep" /path/to/u-boot

Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2015-04-18 11:11:13 -06:00
Joe Hershberger
2eede1f363 sandbox: eth: Add ability to disable ping reply in sandbox eth driver
This is needed to test the netretry functionality (make the command fail
on a sandbox eth device).

Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2015-04-18 11:11:13 -06:00
Joe Hershberger
d87a457be8 sandbox: eth: Add ARP and PING response to sandbox driver
The sandbox driver will now generate response traffic to exercise the
ping command even when no network exists.  This allows the basic data
pathways of the DM to be tested.

Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2015-04-18 11:11:12 -06:00
Joe Hershberger
3ea143abe9 sandbox: eth: Add network support to sandbox
Add basic network support to sandbox which includes a network driver.

Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2015-04-18 11:11:12 -06:00
Joe Hershberger
05c3e68f85 dm: eth: Add basic driver model support to Ethernet stack
First just add support for MAC drivers.

Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2015-04-18 11:11:12 -06:00
Joe Hershberger
d2eaec6006 net: Remove the bd* parameter from net stack functions
This value is not used by the network stack and is available in the
global data, so stop passing it around.  For the one legacy function
that still expects it (init op on old Ethernet drivers) pass in the
global pointer version directly to avoid changing that interface.

Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Reported-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
(Trival fix to remove an unneeded variable declaration in 4xx_enet.c)
2015-04-18 11:11:11 -06:00
Paul Kocialkowski
487b3277d4 sunxi: GPIO pin mux hardware-feature-specific function index defines
Each hardware feature exposed through the GPIO pin mux is usually using the same
function index (for a given port), so there is no need to define one value per
pin: one value per hardware feature per port is sufficient, avoids duplication
and makes everything easier to understand.

Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
Acked-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
2015-04-15 16:17:17 +02:00
Albert ARIBAUD \(3ADEV\)
ac2916a224 lpc32xx: add Ethernet support
Signed-off-by: Albert ARIBAUD (3ADEV) <albert.aribaud@3adev.fr>
2015-04-10 14:22:48 +02:00
Bin Meng
8ee443b8eb net: Add Intel Topcliff GMAC driver
Add a new driver for the Gigabit Ethernet MAC found on Intel Topcliff
Platform Controller Hub. Tested under 10/100 half/full duplex and 1000
full duplex modes using ping and tftpboot commands.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2015-03-24 21:22:37 -06:00
Bin Meng
a7c3d5e2a9 net: Add ethernet FCS length macro in net.h
Some ethernet drivers use their own version of ethernet FCS length
macro which is really common. We define ETH_FCS_LEN in net.h and
replace those custom versions in various places.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2015-03-24 21:22:37 -06:00
Bo Shen
c83cb5f665 Net: macb: reset GBE bit when fallback checking
If the GBE bit is set, when do next time autonegotiation,
if the result is not 1000Mbps, it will fallback to 100Mbps
checking. So, we need to clear the GBE bit.

Signed-off-by: Bo Shen <voice.shen@atmel.com>
2015-03-18 23:36:09 +01:00
Sonic Zhang
d227922150 net: Support DMA threshold mode in DWMAC driver
- DMA threshold mode can be selected in board config head file.

Signed-off-by: Sonic Zhang <sonic.zhang@analog.com>
2015-03-05 11:17:53 -05:00
Sonic Zhang
2ddaf13bd2 net: configure DWMAC DMA by default AXI burst length
Board can define its own AXI burst length to improve DWMAC DMA performance.

v2-changes:
- Avoid write burst len register when the Macro is not defined.

v3-changes:
- Add axi_bus register member to struct eth_dma_regs.

Signed-off-by: Sonic Zhang <sonic.zhang@analog.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2015-03-05 11:17:53 -05:00
Tom Rini
1606b34aa5 Merge branch 'master' of git://git.denx.de/u-boot-fsl-qoriq 2015-02-25 18:14:18 -05:00
Masahiro Yamada
a2f39e830e ARM: remove cm4008 and cm41xx board support
These are still non-generic boards.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Greg Ungerer <greg.ungerer@opengear.com>
Acked-by: Marek Vasut <marex@denx.de>
2015-02-24 17:07:11 -05:00
J. German Rivera
7b3bd9a798 drivers/mc: Migrated MC Flibs to 0.5.2
Upgrade Manage Complex (MC) flib API to 0.5.2. Rename directory
fsl_mc to fsl-mc. Change the fsl-mc node in Linux device tree
from "fsl,dprcr" to "fsl-mc". Print MC version info when
appropriate.

Signed-off-by: J. German Rivera <German.Rivera@freescale.com>
Signed-off-by: Lijun Pan <Lijun.Pan@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-02-24 13:10:20 -08:00
Vitaly Andrianov
312aca4e69 net: keystone_net: move serdes setup to initialization function
On Keystone2 devices serdes must be initialized before accessing MDIO bus.
This commit moves the keystone2_net_serdes_setup() from keystone2_eth_open
to keystone2_emac_initialize to meet that requirement.

This also eliminates unnecessary serdes initializatin every time when the
keystone2_eth_open is being called.

Signed-off-by: Vitaly Andrianov <vitalya@ti.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Tested-by: Nishanth Menon <nm@ti.com>
2015-02-16 12:41:41 -05:00
Tom Rini
6a608f20b9 Merge branch 'master' of git://git.denx.de/u-boot-net 2015-01-31 12:40:26 -05:00
Alexey Brodkin
875143f324 net/designware: add error message on DMA reset timeout
If for some reason DMA module fails to reset user oserves only this:
--->---
# dhcp
Trying dwmac.e0018000
FAIL
--->---

This message makes not much sense.
With proposed change error message will be more helpful:
--->---
# dhcp
Trying dwmac.e0018000
DMA reset timeout
FAIL
--->---

For example user may do power toggle to recover board functionality.

Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@altera.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Tom Rini <trini@ti.com>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Pavel Machek <pavel@denx.de>
Cc: Joe Hershberger <joe.hershberger@gmail.com>
Cc: Ian Campbell <ijc@hellion.org.uk>
Cc: Marek Vasut <marex@denx.de>
Reviewed-by: Tom Rini <trini@ti.com>
Acked-by: Pavel Machek <pavel@denx.de>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
2015-01-30 15:55:00 -06:00
Philippe De Muyter
b7a5b08438 net: phy: micrel: add support for KSZ8895 switch in SMI mode
This patch adds a phy driver for the Micrel KSZ8895 switch.  As the SoC MAC
is directly connected to the switch MAC the link to the switch is always up.

But the KSZ8895 switch can be hardwired in three configuration modes :
- not configurable with eventually an eeprom-stored configuration
- configurable by the mdio/mdc connection (SMI protocol)
- configurable by a SPI connection.

In not configurable mode, the switch starts automatically, but in the
other modes, it must be started programmatically, by writing 1 in
configuration register 1.
We only support the not configurable and mdio/mdc (aka SMI) modes here.

Signed-off-by: Philippe De Muyter <phdm@macqel.be>
Cc: Christian Gmeiner <christian.gmeiner@gmail.com>
Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
2015-01-30 15:55:00 -06:00
Yoshinori Sato
e9efe16da8 Add MS7206SE ethernet support
Signed-off-by: Yoshinori Sato <ysato@users.sourceforge.jp>
Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
2015-01-30 15:55:00 -06:00
Claudiu Manoil
7f233c0557 net: tsec: Fix NULL access in case init_phy() fails
If the PHY is not recognized don't access phydev (NULL)
and return 0 to signal failure.

Signed-off-by: Claudiu Manoil <claudiu.manoil@freescale.com>
Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
2015-01-30 15:55:00 -06:00
Minghuan Lian
06e07f65c7 drivers/net/e1000.c: fix compile warning under 64bit mode
Fix this:
warning: cast from pointer to integer of different size

Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com>
2015-01-30 09:19:16 -05:00
Luka Perkov
5aa2297da7 kirkwood: define empty CONFIG_MVGBE_PORTS by default
Each board with defines it's own set of values. If we do not define
CONFIG_MVGBE_PORTS we will hit following error:

mvgbe.c: In function 'mvgbe_initialize':
mvgbe.c:700:34: error: 'CONFIG_MVGBE_PORTS' undeclared (first use in this function)
  u8 used_ports[MAX_MVGBE_DEVS] = CONFIG_MVGBE_PORTS;

This patch fixes above described problem.

Signed-off-by: Luka Perkov <luka@openwrt.org>
Acked-by: Prafulla Wadaskar <prafulla@marvell.com>
2015-01-25 23:56:15 +01:00
Masahiro Yamada
ad734f7dc2 powerpc: mpc5xxx: remove Total5200 board support
This board is still a non-generic board.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2015-01-23 16:53:52 -05:00
Tom Rini
ec0cc98f2c Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx 2015-01-22 20:04:17 -05:00
Michal Simek
527cd43d75 net: ll_temac: Fix compilation warning because of phys_addr_t
This patch fix the compilation warning
w+../drivers/net/xilinx_ll_temac.c: In function 'll_temac_init':
w+../drivers/net/xilinx_ll_temac.c:235:3: warning: format '%X' expects
argument of type 'unsigned int', but argument 4 has type 'phys_addr_t'
[-Wformat]
introduced by
"net: Declare physical address as phys_addr_t unsigned type"
(sha1: 16ae782722).

Reported-by: Tom Rini <trini@ti.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2015-01-21 10:30:36 +01:00
Michal Simek
5840537879 net: gem: Use phys_addr_t instead of int for addresses
Use phys_addr_t for physical address declaration.
It is also unsigned type instead of sign.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2015-01-21 10:30:21 +01:00
Codrin Ciubotariu
6706b115a6 net/vsc9953: Add driver for Vitesse VSC9953 L2 Switch IP
This patch adds a driver for VSC9953 L2 Switch. This Vitesse IP
is integrated in Freescale T1040 and T1020 SoCs.
The L2 switch has 10 Ethernet ports: 2 internal fixed-links
(ports 8 and 9) at 2.5 Gbps and and 8 external ports at 1 Gbps.
The external ports may be connected to PHYs over QSGMII and SGMII.

Commands have also been added to enable/disable a port and to
check a port's link speed, duplexity and status. The commands are:

ethsw port <port_nr> enable|disable - enable/disable an l2 switch port
ethsw port <port_nr> show - show an l2 switch port's configuration

port_nr=0..9; use "all" for all ports

For more detailse please see doc/README.t1040-l2switch

Signed-off-by: Codrin Ciubotariu <codrin.ciubotariu@freescale.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-01-16 09:32:38 -08:00
Codrin Ciubotariu
27b5756954 net/fm: Enable FMAN ports if l2switch ports are connected over SGMII
If SerDes is configured to connect L2 Switch ports from T1040
over SGMII or QSGMII, the two FMAN fixed ports (FM1@DTSEC1 and FM2@DTSEC2)
that are connected to two L2 swtch ports must be enabled. These
ports don't have PHYs and must be treated accordingly.

Signed-off-by: Codrin Ciubotariu <codrin.ciubotariu@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-01-16 09:32:32 -08:00
Codrin Ciubotariu
6798c324ed net/fm: Fix error when FMAN MAC has no PHY
U-boot assumes that all FMAN ports have a PHY. Some SoCs (like T1040)
have fixed links. This means that the ports are connected MAC to MAc
and there is no Ethernet PHY attatched. This patch initializes a
FMAN MAC even if it doesn't have a PHY attached.

Signed-off-by: Codrin Ciubotariu <codrin.ciubotariu@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-01-16 09:32:16 -08:00
Shaohui Xie
f7c38cf827 phylib: add support for aquantia PHYs
This patch supports AQ1202, AQ2104, AQR105 PHY.

Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-01-16 09:32:11 -08:00
Masahiro Yamada
ceaf499b50 powerpc: manroland: remove uc100, uc101, mucmc52, hmi1001 support
These boards are still non-generic boards.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Heiko Schocher <hs@denx.de>
Cc: Stefan Roese <sr@denx.de>
2015-01-05 12:08:51 -05:00
Thierry Reding
cc0856cd14 net: rtl8169: Add support for RTL-8168/8111g
This network interface card is found on the NVIDIA Jetson TK1.

Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2014-12-18 13:21:41 -07:00
Thierry Reding
d58acdcbfb net: rtl8169: Use non-cached memory if available
To work around potential issues with explicit cache maintenance of the
RX and TX descriptor rings, allocate them from a pool of uncached memory
if the architecture supports it.

Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2014-12-18 13:21:41 -07:00
Thierry Reding
dad3ba0f0b net: rtl8169: Properly align buffers
RX and TX descriptor rings should be aligned to 256 byte boundaries. Use
the DEFINE_ALIGN_BUFFER() macro to define the buffers so that they don't
have to be manually aligned later on. Also make sure that the buffers do
align to cache-line boundaries in case the cache-line is higher than the
256 byte alignment requirements of the NIC.

Also add a warning if the cache-line size is larger than the descriptor
size, because the driver may discard changes to descriptors made by the
hardware when requeuing RX buffers.

Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2014-12-18 13:21:41 -07:00
Thierry Reding
c94bbfdf51 net: rtl8169: Honor CONFIG_SYS_RX_ETH_BUFFER
According to the top-level README file, this configuration setting can
be used to override the number of receive buffers that an ethernet NIC
uses.

Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2014-12-18 13:21:41 -07:00
Shengzhou Liu
24d827f526 net/fm: update ft_fixup_port to differentiate dual-role mac
we need to differentiate dual-role MACs into two types: MACs with
10GEC enumeration consistent with DTSEC enumeration(defined by
CONFIG_FSL_FM_10GEC_REGULAR_NOTATION) and other MACs without
CONFIG_FSL_FM_10GEC_REGULAR_NOTATION defined.

Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-12-15 09:15:55 -08:00
Shengzhou Liu
c18fc2c960 net/phy: enable serdes auto-negotiation for vsc8514 phy
VSC8514 QSGMII PHY requires enabling auto-negotiation,
otherwise it wouldn't work.

Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-12-05 08:06:15 -08:00
Shengzhou Liu
cc19c25e27 net/fman: update 10GEC to fit new SoC
fm_standard_init() initializes each 10G port by FM_TGEC_INFO_INITIALIZER.
but it needs different implementation of FM_TGEC_INFO_INITIALIZER on different SoCs.
on SoCs earlier(e.g. T4240, T2080), the notation between 10GEC and MAC as below:
	10GEC1->MAC9, 10GEC2->MAC10, 10GEC3->MAC1, 10GEC4->MAC2
on SoCs later(e.g. T1024, etc), the notation between 10GEC and MAC as below:
	10GEC1->MAC1, 10GEC2->MAC2

so we introduce CONFIG_FSL_FM_10GEC_REGULAR_NOTATION to fit the new SoCs on
which 10GEC enumeration is consistent with MAC enumeration.

Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-12-05 08:06:15 -08:00
Shengzhou Liu
f605079041 powerpc/mpc85xx: Add T1024/T1023 SoC support
Add support for Freescale T1024/T1023 SoC.

The T1024 SoC includes the following function and features:
- Two 64-bit Power architecture e5500 cores, up to 1.4GHz
- private 256KB L2 cache each core and shared 256KB CoreNet platform cache (CPC)
- 32-/64-bit DDR3L/DDR4 SDRAM memory controller with ECC and interleaving support
- Data Path Acceleration Architecture (DPAA) incorporating acceleration
- Four MAC for 1G/2.5G/10G network interfaces (RGMII, SGMII, QSGMII, XFI)
- High-speed peripheral interfaces
  - Three PCI Express 2.0 controllers
- Additional peripheral interfaces
  - One SATA 2.0 controller
  - Two USB 2.0 controllers with integrated PHY
  - Enhanced secure digital host controller (SD/eSDHC/eMMC)
  - Enhanced serial peripheral interface (eSPI)
  - Four I2C controllers
  - Four 2-pin UARTs or two 4-pin UARTs
  - Integrated Flash Controller supporting NAND and NOR flash
- Two 8-channel DMA engines
- Multicore programmable interrupt controller (PIC)
- LCD interface (DIU) with 12 bit dual data rate
- QUICC Engine block supporting TDM, HDLC, and UART
- Deep Sleep power implementaion (wakeup from GPIO/Timer/Ethernet/USB)
- Support for hardware virtualization and partitioning enforcement
- QorIQ Platform's Trust Architecture 2.0

Differences between T1024 and T1023:
  Feature         T1024  T1023
  QUICC Engine:   yes    no
  DIU:            yes    no
  Deep Sleep:     yes    no
  I2C controller: 4      3
  DDR:            64-bit 32-bit
  IFC:            32-bit 28-bit

Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-12-05 08:06:14 -08:00
Suresh Gupta
e2544e7a54 B4860QDS: Enable enet port as per fsl_b4860_serdes2 string in hwconfig
In B4860QDS board SerDes2 lanes EFGH either go to SFP or AMC riser card
slot2 so either DTSEC3/DTSEC4 or TGEC1/TGEC2 should be accessible. This
Patch enables DTSEC3/DTSEC4 or TGEC1/TGEC2 on bases of user specified
string fsl_b4860_serdes2:sfp_amc=amc or fsl_b4860_serdes2:sfp_amc=sfp
respectively in hwconfig.

Signed-off-by: Suresh Gupta <suresh.gupta@freescale.com>
Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-12-05 08:06:14 -08:00
Shaohui Xie
89b94d851d powerpc/b4860qds: add xfi support
We need following changes to make xfi work on B4:
1. set cross-point switch VSC3308 to use sfp config when running xfi;
2. add 10G interface check for xfi;
3. set phy address for xfi so the 10G ports can be registered by mdio;

Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-12-05 08:06:13 -08:00
Shengzhou Liu
9b18e5199e net/phy: Add support for CS4315/CS4340 PHY
Add support for Cortina CS4315/CS4340 10G PHY.
- This driver loads CS43xx firmware from NOR/NAND/SPI/SD device
  to initialize Cortina PHY.
- Cortina PHY has non-standard offset of PHY ID registers, thus
  we define own get_phy_id() to override default get_phy_id().
- To define macro CONFIG_PHY_CORTINA will enable this driver.

Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-12-05 08:06:11 -08:00
Joakim Tjernlund
bcb60cb9c4 Freescale t104x: Do not exclude SGMII
fman_port_enet_if() tests if FM1_DTSEC2 or FM1_DTSEC4 uses
RGMII or MII and if not returns PHY_INTERFACE_MODE_NONE.
This excludes testing for SGMII further down.

Remove the unconditional "else return PHY_INTERFACE_MODE_NONE"
so SGMII can be tested too.

Signed-off-by: Joakim Tjernlund <Joakim.Tjernlund@transmode.se>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-12-05 08:06:07 -08:00
Tom Rini
21008ad638 Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx
Conflicts:
	drivers/mmc/fsl_esdhc.c

Signed-off-by: Tom Rini <trini@ti.com>
2014-11-26 11:22:29 -05:00
Masahiro Yamada
b41411954d linux/kernel.h: sync min, max, min3, max3 macros with Linux
U-Boot has never cared about the type when we get max/min of two
values, but Linux Kernel does.  This commit gets min, max, min3, max3
macros synced with the kernel introducing type checks.

Many of references of those macros must be fixed to suppress warnings.
We have two options:
 - Use min, max, min3, max3 only when the arguments have the same type
   (or add casts to the arguments)
 - Use min_t/max_t instead with the appropriate type for the first
   argument

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Acked-by: Pavel Machek <pavel@denx.de>
Acked-by: Lukasz Majewski <l.majewski@samsung.com>
Tested-by: Lukasz Majewski <l.majewski@samsung.com>
[trini: Fixup arch/blackfin/lib/string.c]
Signed-off-by: Tom Rini <trini@ti.com>
2014-11-23 06:48:30 -05:00
Shengzhou Liu
c35f869394 net/fm: add 2.5G SGMII support
As auto-negotiation is not supported for 2.5G SGMII, we need
to add a new type PHY_INTERFACE_MODE_SGMII_2500 to differentiate
SGMII-1G and SGMII-2.5G with different setting for auto-negotiation.

Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-11-19 18:17:12 -08:00
Bo Shen
cabf61ce4b net: macb: enable GMAC IP without GE feature support
The User Register in GMAC IP is used to select interface type.
When with GE feature, it is used to select interface between
RGMII and GMII. If without GE feature, it is used to select
interface between MII and RMII.

Signed-off-by: Bo Shen <voice.shen@atmel.com>
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
2014-11-17 08:47:18 -05:00