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39808 commits

Author SHA1 Message Date
Tang Yuantian
f0beb49290 armv8: fsl-lsch2: adjust sata parameter
The default values for Port Phy2Cfg register and
Port Phy3Cfg register are better, no need to overwrite them.

Signed-off-by: Tang Yuantian <yuantian.tang@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2016-10-06 09:52:35 -07:00
Tom Rini
53fec16206 Prepare v2016.11-rc1
Signed-off-by: Tom Rini <trini@konsulko.com>
2016-10-03 09:28:13 -04:00
Tom Rini
51b4a639e4 Merge git://git.denx.de/u-boot-rockchip 2016-10-03 09:09:29 -04:00
Andrew F. Davis
e95b9b4437 ti_armv7_common: Disable Falcon Mode on HS devices
Authentication of images in Falcon Mode is not supported. Do not enable
SPL_OS_BOOT when TI_SECURE_DEVICE is enabled. This prevents attempting
to directly load kernel images which will fail, for security reasons,
on HS devices, the board is locked if a non-authenticatable image load
is attempted, so we disable attempting Falcon Mode.

Signed-off-by: Andrew F. Davis <afd@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Acked-by: Lokesh Vutla <lokeshvutla@ti.com>
2016-10-02 08:10:03 -04:00
Andrew F. Davis
2f450969de config: Remove usage of CONFIG_STORAGE_EMMC
This config option seems to be unused and is probably vestigial.
Remove it.

Signed-off-by: Andrew F. Davis <afd@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Acked-by: Lokesh Vutla <lokeshvutla@ti.com>
2016-10-02 08:10:03 -04:00
Andrew F. Davis
ba84e6ae1f ti: omap-common: Allow AM33xx devices to be built securely
Like OMAP54xx and AM43xx family SoCs, AM33xx based SoCs have high
security enabled models. Allow AM33xx devices to be built with
HS Device Type Support.

Signed-off-by: Andrew F. Davis <afd@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Acked-by: Lokesh Vutla <lokeshvutla@ti.com>
2016-10-02 08:10:02 -04:00
Andrew F. Davis
b0a4eea1a0 board: am33xx-hs: Allow post-processing of FIT image on AM33xx
When CONFIG_FIT_IMAGE_POST_PROCESS or CONFIG_SPL_FIT_IMAGE_POST_PROCESS
is enabled board_fit_image_post_process will be called, add this
function to am33xx boards when CONFIG_TI_SECURE_DEVICE is set to
verify the loaded image.

Signed-off-by: Andrew F. Davis <afd@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Acked-by: Lokesh Vutla <lokeshvutla@ti.com>
2016-10-02 08:10:01 -04:00
Andrew F. Davis
7e5a0bfbd2 am33xx: config.mk: Fix option used to enable SPI SPL image type
The option SPL_SPI_SUPPORT is used to enable support in SPL for loading
images from SPI flash, it should not be used to determine the build type
of the SPL image itself. The ability to read images from SPI flash does
not imply the SPL will be booted from SPI flash.

Unconditionally build SPI flash compatible SPL images.

Signed-off-by: Andrew F. Davis <afd@ti.com>
Acked-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2016-10-02 08:10:00 -04:00
Andrew F. Davis
f7160eac83 doc: Update info on using AM33xx secure devices from TI
Add a section describing the additional boot types used on AM33xx
secure devices.

Signed-off-by: Andrew F. Davis <afd@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Acked-by: Lokesh Vutla <lokeshvutla@ti.com>
2016-10-02 08:09:59 -04:00
Andrew F. Davis
9eda25181d am33xx: config.mk: Add support for additional secure boot image types
Depending on the boot media, different images are needed
for secure devices. The build generates u-boot*_HS_* files
as appropriate for the different boot modes.

For AM33xx devices additional image types are needed for
various SPL boot modes as the ROM checks for the name of
the boot mode in the file it loads.

Signed-off-by: Andrew F. Davis <afd@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Acked-by: Lokesh Vutla <lokeshvutla@ti.com>
2016-10-02 08:09:59 -04:00
Andrew F. Davis
b39a9ade5c Kconfig: Separate AM33XX SOC config from target board config
The config option AM33XX is used in several boards and should be
defined as a stand-alone option for this SOC. We break this out
from target boards that use this SoC and common headers then enable
AM33XX on in all the boards that used these targets to eliminate any
functional change with this patch.

This is similar to what has already been done in
9de852642cae ("arm: Kconfig: Add support for AM43xx SoC specific Kconfig")
and is done for the same reasons.

Signed-off-by: Andrew F. Davis <afd@ti.com>
Acked-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2016-10-02 08:09:58 -04:00
Daniel Allred
6696139409 ARM: omap5: add fdt secure dram reservation fixup
Adds a secure dram reservation fixup for secure
devices, when a region in the emif has been set aside
for secure world use. The size is defined by the
CONFIG_TI_SECURE_EMIF_TOTAL_REGION_SIZE config option.

Signed-off-by: Daniel Allred <d-allred@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2016-10-02 08:09:57 -04:00
Daniel Allred
32d333f2f0 ti_omap5_common: mark region of DRAM protected on HS parts
If the ending portion of the DRAM is reserved for secure
world use, then u-boot cannot use this memory for its relocation
purposes. To prevent issues, we mark this memory as PRAM and this
prevents it from being used by u-boot at all.

Signed-off-by: Daniel Allred <d-allred@ti.com>
2016-10-02 08:09:57 -04:00
Daniel Allred
501f0ef304 ARM: DRA7: Add secure emif setup calls
After EMIF DRAM is configured, but before it is used,
calls are made on secure devices to reserve any configured
memory region needed by the secure world and then to lock the
EMIF firewall configuration. If any other firewall
configuration needs to be applied, it must happen before the
lock call.

Signed-off-by: Daniel Allred <d-allred@ti.com>
2016-10-02 08:09:56 -04:00
Daniel Allred
6d132b2b09 arm: omap5: secure API for EMIF memory reservations
Create a few public APIs which rely on secure world ROM/HAL
APIs for their implementation. These are intended to be used
to reserve a portion of the EMIF memory and configure hardware
firewalls around that region to prevent public code from
manipulating or interfering with that memory.

Signed-off-by: Daniel Allred <d-allred@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2016-10-02 08:09:55 -04:00
Daniel Allred
4c854b6199 ti: omap5: Add Kconfig options for secure EMIF reservations
Adds start address and size config options for setting aside
a portion of the EMIF memory space for usage by security software
(like a secure OS/TEE). There are two sizes, a total size and a
protected size. The region is divided into protected (secure) and
unprotected (public) regions, that are contiguous and start at the
start address given. If the start address is zero, the intention
is that the region will be automatically placed at the end of the
available external DRAM space.

Signed-off-by: Daniel Allred <d-allred@ti.com>
2016-10-02 08:09:51 -04:00
Jacob Chen
67171e13a3 rockchip: add boot-mode support for rk3288, rk3036
rockchip platform have a protocol to pass the the kernel reboot mode to bootloader
by some special registers when system reboot. In bootloader we should read it and take action.

We can only setup boot_mode in board_late_init becasue "setenv" need env setuped.
So add CONFIG_BOARD_LATE_INIT to common header and use a entry "rk_board_late_init"
to replace "board_late_init" in board file.

Signed-off-by: Jacob Chen <jacob2.chen@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
2016-10-01 18:36:55 -06:00
Jacob Chen
f48f2b729b rockchip: move common function from board-file to rk3036-board.c
To keep it same with 3288

Signed-off-by: Jacob Chen <jacob2.chen@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
2016-10-01 18:36:55 -06:00
Jacob Chen
cd77fd1b43 rockchip: rename board.c to rk3288-board.c
Signed-off-by: Jacob Chen <jacob2.chen@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
2016-10-01 18:36:55 -06:00
Jacob Chen
73a8598971 rockchip: move partitons define from 3036-kylin to 3036-common
To keep it same with 3288.

Signed-off-by: Jacob Chen <jacob2.chen@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
2016-10-01 18:36:55 -06:00
Xu Ziyuan
c12777a625 rockchip: miniarm: remove eMMC support
The latest rk3288-miniarm board doesn't have eMMC device, so remove it.

Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
2016-10-01 18:35:01 -06:00
Kever Yang
f2358ece1d config: evb-rk3399: enable pwm regulator
Enable the pwm regulator for evb-rk3399.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
2016-10-01 18:35:01 -06:00
Kever Yang
c553de90bd dts: evb-rk3399: add init voltage node for vdd-center
Add a regulator-init-microvolt for vdd_center regulator
so that we can get a init value for driver probe.
Not like pmic regulator, the PWM regulator do not have a
known default output value, so we would like to init the
regulator when driver probe.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
2016-10-01 18:35:01 -06:00
Kever Yang
8d29e3a4c4 Kconfig: rockchip: enable DM_PWM and DM_REGULATOR
Enable DM_PWM and DM_REGULATOR on rockchip SoCs.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
2016-10-01 18:35:01 -06:00
Kever Yang
be3fcd0fe8 rockchip: evb_rk3399: init vdd_center regulator
Add vdd_center pwm regulator get_device to
enable this regulator.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
2016-10-01 18:35:01 -06:00
Kever Yang
1a01695615 power: regulator: add pwm regulator
add driver support for pwm regulator.

Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
2016-10-01 18:35:01 -06:00
Kever Yang
d840daf4c2 rockchip: rkpwm: fix the register sequence
Reference to kernel source code, rockchip pwm has three
type, we are using v2 for rk3288 and rk3399, so let's
update the register to sync with pwm_data_v2 in kernel.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
2016-10-01 18:35:01 -06:00
Kever Yang
8389dcbf98 rockchip: rk3399: update PPLL and pmu_pclk frequency
Update PPLL to 676MHz and PMU_PCLK to 48MHz, because:
1. 48MHz can make sure the pwm can get exact 50% duty ratio, but 99MHz
can not,
2. We think 48MHz is fast enough for pmu pclk and it is lower power cost
than 99MHz,
3. PPLL 676 MHz and PMU_PCLK 48MHz are the clock rate we are using
internally for kernel,it suppose not to change the bus clock like pmu_pclk
in kernel, so we want to change it in uboot.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
2016-10-01 18:35:01 -06:00
jacob2.chen
e73e5fcd84 rockchip: add usb mass storage feature support for rk3036
Enable ums feature for rk3036 boards, so that we can mount the mmc
device to PC.

Signed-off-by: jacob2.chen <jacob2.chen@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
2016-10-01 18:35:01 -06:00
Sandy Patterson
70616df2bf Enable ROCKCHIP_SPL_BACK_TO_BROM for rock2 board
Rock2 has been tested with back to brom feature. The tricky part is that
with this feature the default environment is inside u-boot, and it's
defined for every rk3288 board independetly. So I just changed it for
rock2 here if ROCKCHIP_SPL_BACK_TO_BROM.

Solve by moving environment after u-boot before 1M boundary

Signed-off-by: Sandy Patterson <apatterson@sightlogix.com>
Acked-by: Simon Glass <sjg@chromium.org>
2016-10-01 18:35:01 -06:00
Sandy Patterson
230e0e09da Disable SPL_MMC_SUPPORT if ROCKCHIP_SPL_BACK_TO_BROM is enabled.
Default SPL_MMC_SUPPORT to false when ROCKCHIP_SPL_BACK_TO_BROM is enabled.

Acked-by: Ziyuan Xu <xzy.xu@rock-chips.com>
Signed-off-by: Sandy Patterson <apatterson@sightlogix.com>
Acked-by: Simon Glass <sjg@chromium.org>
2016-10-01 18:35:01 -06:00
Sandy Patterson
427351dc1d rockchip: Fix SPL console output when ROCKCHIP_SPL_BACK_TO_BROM is enabled
Move back_to_bootrom() call later in SPL init so that the console is
initialized and printouts happen.

Currently when ROCKCHIP_SPL_BACK_TO_BROM is enabled there is no console
output from the SPL init stages.

I wasn't sure exactly where this should happen, so if we are set to do
run spl_board_init, then go back to bootrom there after
preloader_console_init(). Otherwise fall back to old behavior of doing
it in board_init_f.

Signed-off-by: Sandy Patterson <apatterson@sightlogix.com>
Acked-by: Ziyuan Xu <xzy.xu@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
2016-10-01 18:35:01 -06:00
Xu Ziyuan
2179a07c0c rockchip: rk3288: sdram: fix DDR address range
The all current Rockchip SoCs supporting 4GB of ram have problems
accessing the memory region 0xfe000000~0xff000000. Actually, some IP
controller can't address to, so let's limit the available range.

This patch fixes a bug which found in miniarm-rk3288-4GB board. The
U-Boot was relocated to 0xfef72000, and .bss variants was also
relocated, such as do_fat_read_at_block. Once eMMC controller transfer
data to do_fat_read_at_block via DMA, DMAC can't access more than
0xfe000000. So that DMAC didn't work sane.

Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
2016-10-01 18:35:01 -06:00
Heiko Schocher
592a749527 net, macb: fix misaligned cache operation warning
when using tftp on the smartweb board, it prints a lot of

CACHE: Misaligned operation at range [23b2e000, 23b2e100]

warnings ... fixed them.

Signed-off-by: Heiko Schocher <hs@denx.de>
2016-10-01 20:05:14 -04:00
Lokesh Vutla
ceee15ce5d ti_armv7_keystone2: Update addr_mon variable
As boot monitor contains a mkimage header, it can be loaded at any location.
So, have a common addr_mon address across all keystone2 SoCs. And also
making sure that boot monitor is installed early during default boot to
avoid any overlapping with other images.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2016-10-01 20:05:12 -04:00
Lokesh Vutla
5d21406516 ARM: keystone2: Add support for parsing monitor header
Given that boot monitor image is being generated to a specific target location
depending on the SoC and U-boot relies on addr_mon env variable to be aligned
with boot monitor target location. When ever the target address gets updated in
boot monitor, it is difficult to sync between u-boot and boot monitor and also
there is no way to update user that boot monitor image is updated.

To avoid this problem, boot monitor image is being generated with mkimage
header. Adding support in mon_install command for parsing this header.

Signed-off-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2016-10-01 20:05:10 -04:00
Murali Karicheri
86e3ca1178 keystone2: k2g: add env script to load firmware initramfs as part of boot flow
On K2G, the PCIe SerDes h/w is a re-use from other K2 devices and SerDes
driver requires a firmware image to initialize the SerDes h/w device.
This is firmware is part of the initramfs file that is loaded to memory
in u-boot and passed to kernel as in other K2 platforms. This patch
customize the u-boot env to have this done automatically when the K2G EVM
boots up. With this, a user may be able to boot the EVM with a standard
PCIe card at the x1 PCIe slot and release image and test PCIe devices
such as NIC, SATA etc.

Signed-off-by: Murali Karicheri <m-karicheri2@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2016-10-01 20:05:08 -04:00
Lokesh Vutla
e1ae357d4b board: k2g: Enable ECC byte lane
Enable ECC byte lane for k2g-evm

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2016-10-01 20:05:07 -04:00
Lokesh Vutla
e92a6b2ee3 board: ks2: Enable ECC using detected DDR size
EEC is being enabled based on the ddr size populated by SPD data.
But not all keystone platforms have SPD data to detect ddr3 size.
So, enable ECC using the detected DDR size.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2016-10-01 20:05:05 -04:00
Petr Kulhavy
6f6c863094 fastboot: move FASTBOOT_FLASH options into Kconfig
Move FASTBOOT_MBR_NAME and FASTBOOT_GPT_NAME into Kconfig.
Add dependency on the FASTBOOT_FLASH setting (also for FASTBOOT_MBR_NAME).
Remove the now redundant GPT_ENTRY_NAME.

Signed-off-by: Petr Kulhavy <brain@jikos.cz>
Reviewed-by: Tom Rini <trini@konsulko.com>
Acked-by: Steve Rae <steve.rae@raedomain.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
[trini: Add FIXME about xxx_PARTITION needing to be in Kconfig]
Signed-off-by: Tom Rini <trini@konsulko.com>
2016-10-01 20:04:59 -04:00
Petr Kulhavy
da2ee24d91 disk: part: refactor generic name creation for DOS and ISO
In both DOS and ISO partition tables the same code to create partition name
like "hda1" was repeated.

Code moved to into a new function part_set_generic_name() in part.c and optimized.
Added recognition of MMC and SD types, name is like "mmcsda1".

Signed-off-by: Petr Kulhavy <brain@jikos.cz>
Reviewed-by: Tom Rini <trini@konsulko.com>
Acked-by: Steve Rae <steve.rae@raedomain.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2016-10-01 20:04:56 -04:00
Petr Kulhavy
b6dd69a4d6 fastboot: add support for writing MBR
Add special target "mbr" (otherwise configurable via CONFIG_FASTBOOT_MBR_NAME)
to write MBR partition table.
Partitions are now searched using the generic function which finds any
partiiton by name. For MBR the partition names hda1, sda1, etc. are used.

Signed-off-by: Petr Kulhavy <brain@jikos.cz>
Reviewed-by: Tom Rini <trini@konsulko.com>
Acked-by: Steve Rae <steve.rae@raedomain.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2016-10-01 20:04:51 -04:00
Petr Kulhavy
87b8530fe2 disk: part: implement generic function part_get_info_by_name()
So far partition search by name has been supported only on the EFI partition
table. This patch extends the search to all partition tables.

Rename part_get_info_efi_by_name() to part_get_info_by_name(), move it from
part_efi.c into part.c and make it a generic function which traverses all part
drivers and searches all partitions (in the order given by the linked list).

For this a new variable struct part_driver.max_entries is added, which limits
the number of partitions searched. For EFI this was GPT_ENTRY_NUMBERS.
Similarly the limit is defined for DOS, ISO, MAC and AMIGA partition tables.

Signed-off-by: Petr Kulhavy <brain@jikos.cz>
Reviewed-by: Tom Rini <trini@konsulko.com>
Acked-by: Steve Rae <steve.rae@raedomain.com>
2016-10-01 20:04:45 -04:00
Zubair Lutfullah Kakakhel
ba07984068 bootm: fix passing argc to standalone apps
This bug appears in b6396403 which makes u-boot unable to pass
arguments via bootm to a standalone application without this patch.

Steps to reproduce.

Compile a u-boot. Use mkimage to package the standalone hello_world.bin
file.

e.g. For the MIPS Boston platform

mkimage -n "hello" -A mips -O u-boot -C none -T standalone \
     -a 0xffffffff80200000 -d hello_world.bin \
     -ep 0xffffffff80200000 hello_out

Then tftp hello_out and run it using

boston # dhcp 192.168.154.45:hello_out
...
boston # bootm $loadaddr 123 321

Without the patch the following output is observed.

boston # bootm $loadaddr 123 321
   Image Name:   hello
   Image Type:   MIPS U-Boot Standalone Program (uncompressed)
   Data Size:    1240 Bytes = 1.2 KiB
   Load Address: 80200000
   Entry Point:  80200000
   Verifying Checksum ... OK
   Loading Standalone Program ... OK
Example expects ABI version 8
Actual U-Boot ABI version 8
Hello World
argc = 0
argv[0] = "0xffffffff88000000"

With the patch, you see the following.

boston # bootm $loadaddr 123 321
   Image Name:   hello
   Image Type:   MIPS U-Boot Standalone Program (uncompressed)
   Data Size:    1240 Bytes = 1.2 KiB
   Load Address: 80200000
   Entry Point:  80200000
   Verifying Checksum ... OK
   Loading Standalone Program ... OK
Example expects ABI version 8
Actual U-Boot ABI version 8
Hello World
argc = 3
argv[0] = "0xffffffff88000000"
argv[1] = "123"
argv[2] = "321"
argv[3] = "<NULL>"

Without the patch, the go command at the entry point seems to work.

boston # go 0xffffffff80200000 123 321
Example expects ABI version 8
Actual U-Boot ABI version 8
Hello World
argc = 3
argv[0] = "0xffffffff80200000"
argv[1] = "123"
argv[2] = "321"
argv[3] = "<NULL>"
Hit any key to exit ...

Signed-off-by: Zubair Lutfullah Kakakhel <Zubair.Kakakhel@imgtec.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2016-10-01 20:04:37 -04:00
Masahiro Yamada
b98278be7b input: specify the default of I8042_KEYB in more correct manner
Creating multiple entries of "config FOO" often gives us bad
experiences.  In this case, we should specify "default X86"
as platforms that want this keyboard by default.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Acked-by: Marek Vasut <marex@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
2016-10-01 20:04:35 -04:00
Masahiro Yamada
558e12571e sandbox, x86: select DM_KEYBOARD instead of default y entry
Once we migrate to DM-based drivers, we cannot go back to legacy
ones, i.e. config options like DM_* are not user-configurable.

Make SANDBOX and X86 select DM_KEYBOARD like other platforms do.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2016-10-01 20:04:33 -04:00
Tom Rini
45b047e557 Merge branch 'master' of git://git.denx.de/u-boot-nds32 2016-09-30 21:59:11 -04:00
Tom Rini
fe4ba689a0 Merge branch 'master' of git://git.denx.de/u-boot-usb
Signed-off-by: Tom Rini <trini@konsulko.com>

Conflicts:
	include/configs/dra7xx_evm.h
2016-09-30 21:58:44 -04:00
rick
d607f6fa99 nds32: Support relocation.
Enable pie option for relocation.

Signed-off-by: rick <rick@andestech.com>
Cc: Andes <uboot@andestech.com>
2016-09-29 15:38:10 +08:00
Sriram Dash
f413d1cae8 mpc85xx: powerpc: usb: Update the list of Socs afftected by erratum A006261
Apply the erratum A006261 for the following Socs:
P2041 rev 2.0, P2040 rev 2.0, P5040 rev 2.0, 2.1

Do not apply erratum A006261 for the following Socs:
T4160, T4080, T1040, T1042, T1020, T1022, T2080, T2081

Erratum A006261 is applicable for the following Socs:
P1010(1.0, 2.0), P2041(1.0, 1.1, 2.0, 2.1), P2040(1.0, 1.1, 2.0, 2.1),
P3041(1.0, 1.1, 2.0, 2.1), P5010(1.0, 2.0), P5020(1.0, 2.0),
P5021(1.0, 2.0), T4240(1.0, 2.0), P5040(1.0,2.0,2.1).

Signed-off-by: Sriram Dash <sriram.dash@nxp.com>
Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2016-09-28 09:08:16 -07:00