Commit graph

86661 commits

Author SHA1 Message Date
Jonas Karlman
68000f750a rockchip: rk3568-rock-3a: Update defconfig
Update defconfig for rk3568-rock-3a with new defaults.

Remove the SPL_ROCKCHIP_BACK_TO_BROM=y option, SPL is expected to load
next stage from a FIT image and then jump to next stage not back to
BootRom.

Add CONFIG_SPL_FIT_SIGNATURE=y to let SPL verify an auto generated hash
of FIT images. This help indicate if there is an issue loading any of
the images to DRAM or SRAM.

Extend SPL_MAX_SIZE to 0x40000, SPL is loaded to 0x0 and TF-A is loaded
to 0x40000, use the space in between as SPL_MAX_SIZE.

Add config option to include useful gpio cmd.

Remove the CONFIG_NET_RANDOM_ETHADDR=y option, ethaddr and eth1addr is
set based on cpuid read from OTP.

Filter out assigned-clock props with CONFIG_OF_SPL_REMOVE_PROPS,
U-Boot proper will read and configure assigned-clock props.

Remove the CONFIG_SPL_PMIC_RK8XX=y option, the pmic is not used in SPL.

Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-05-18 08:44:04 +08:00
Jonas Karlman
703c170b40 rockchip: rk3568-evb: Update defconfig
Update defconfig for rk3568-evb with new defaults.

Remove the SPL_ROCKCHIP_BACK_TO_BROM=y option, SPL is expected to load
next stage from a FIT image and then jump to next stage not back to
BootRom.

Add CONFIG_SPL_FIT_SIGNATURE=y to let SPL verify an auto generated hash
of FIT images. This help indicate if there is an issue loading any of
the images to DRAM or SRAM.

Extend SPL_MAX_SIZE to 0x40000, SPL is loaded to 0x0 and TF-A is loaded
to 0x40000, use the space in between as SPL_MAX_SIZE.

Add config options to include useful gpio, i2c, pmic and regulator cmd.

Remove the CONFIG_NET_RANDOM_ETHADDR=y option, ethaddr and eth1addr is
set based on cpuid read from OTP.

Filter out assigned-clock props with CONFIG_OF_SPL_REMOVE_PROPS,
U-Boot proper will read and configure assigned-clock props.

Add config options to enable support for the RK809 PMIC.

Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-05-18 08:44:04 +08:00
Jonas Karlman
41cb87be06 rockchip: rk3566-radxa-cm3-io: Use pinctrl for sdmmc and sdhci in SPL
Enable pinctrl for sdmmc and sdhci in SPL to support loading of FIT
image from SD and eMMC storage when booting from SPI NOR flash.

Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-05-18 08:44:04 +08:00
Jonas Karlman
1bf49d5a4a rockchip: rk3566-radxa-cm3-io: Update defconfig
Update defconfig for rk3566-radxa-cm3-io with new defaults. Also add
missing supported mmc modes to sdhci node.

Remove the SPL_ROCKCHIP_BACK_TO_BROM=y option, SPL is expected to load
next stage from a FIT image and then jump to next stage not back to
BootRom.

Add CONFIG_SPL_FIT_SIGNATURE=y to let SPL verify an auto generated hash
of FIT images. This help indicate if there is an issue loading any of
the images to DRAM or SRAM.

Extend SPL_MAX_SIZE to 0x40000, SPL is loaded to 0x0 and TF-A is loaded
to 0x40000, use the space in between as SPL_MAX_SIZE.

Add config option to include useful gpio cmd.

Remove the CONFIG_NET_RANDOM_ETHADDR=y option, ethaddr and eth1addr is
set based on cpuid read from OTP.

Filter out assigned-clock props with CONFIG_OF_SPL_REMOVE_PROPS,
U-Boot proper will read and configure assigned-clock props.

Add CONFIG_SYS_NS16550_MEM32=y to use 32bit access of serial register.

Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-05-18 08:44:04 +08:00
Jonas Karlman
dc27b4a1af rockchip: rk356x-u-boot: Add xin24m clock node to SPL
Add bootph-all prop to xin24m clock node, it is referenced by cru node.

Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-05-18 08:44:04 +08:00
Jonas Karlman
f02cbff67d spi: rockchip_sfc: Use linux rockchip,sfc-no-dma prop
Use the same prop as linux to control the use of fifo or dma mode. Also
add a u-boot,spl-sfc-no-dma prop to control the same in SPL.

Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-05-18 08:44:04 +08:00
Eugen Hristev
6832810814 configs: rock5b-rk3588: add PCI drivers and command
Add drivers for PCIe , phy, and command.

Signed-off-by: Eugen Hristev <eugen.hristev@collabora.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-05-18 08:44:04 +08:00
Christopher Obbard
bfbef68ae1 ARM: dts: rockchip: rock5b: enable pcie2x1l2 and associated combphy
Enable the PCIe 2x1l 2 device and associated combphy.
On this bus, the Rock5B has an Ethernet transceiver connected.

Signed-off-by: Christopher Obbard <chris.obbard@collabora.com>
[eugen.hristev@collabora.com: minor tweaks]
Signed-off-by: Eugen Hristev <eugen.hristev@collabora.com>
[jonas@kwiboo.se: add PCIe pins]
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-05-18 08:44:04 +08:00
Joseph Chen
ec8242cceb ARM: dts: rockchip: rk3588s-u-boot: add pcie2x1l2 with PHY
Add the node for PCIe 2x1l 2 device together with the corresponding
combphy.

Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
[eugen.hristev@collabora.com: moved to -u-boot.dtsi, minor
adaptations]
Signed-off-by: Eugen Hristev <eugen.hristev@collabora.com>
[jonas@kwiboo.se: adapt to kernel node]
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-05-18 08:44:04 +08:00
Jonas Karlman
5713135ecc rockchip: rockpro64: Build u-boot-rockchip-spi.bin
Enable CONFIG_ROCKCHIP_SPI_IMAGE to build u-boot-rockchip-spi.bin.
Define CONFIG_SYS_SPI_U_BOOT_OFFS to write u-boot.itb at the expected
offset. Enable CONFIG_LTO to reduce size of SPL so that the mkimage
output fit before the 0x60000 offset in u-boot-rockchip-spi.bin.

  => sf probe
  SF: Detected gd25q128 with page size 256 Bytes, erase size 4 KiB, total 16 MiB
  => load mmc 1:1 10000000 u-boot-rockchip-spi.bin
  1442304 bytes read in 27 ms (50.9 MiB/s)
  => sf update $fileaddr 0 $filesize
  device 0 offset 0x0, size 0x160200
  1421824 bytes written, 20480 bytes skipped in 9.501s, speed 155432 B/s

Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-05-18 08:44:04 +08:00
Jonas Karlman
6e2b8344d6 rockchip: rock-pi-4: Use SDMA to boost eMMC performance
Enable the use of SDMA mode to boost eMMC performance on ROCK Pi 4.
Also add missing flags to indicate the supported MMC modes.

Using mmc read command to read 32 MiB data shows following improvement:

  => time mmc read 10000000 2000 10000

Before: time: 3.178 seconds
After: time: 0.402 seconds

This also enables CONFIG_SPL_FIT_SIGNATURE option to help discover
any possible future issue with loading TF-A into DRAM/SRAM.

Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-05-18 08:44:04 +08:00
Jonas Karlman
cf777572ca rockchip: rockpro64: Use SDMA to boost eMMC performance
Enable the use of SDMA mode to boost eMMC performance on RockPro64.
Also add missing flags to indicate the supported MMC modes.

Using mmc read command to read 32 MiB data shows following improvement:

  => time mmc read 10000000 2000 10000

Before: time: 3.178 seconds
After: time: 0.402 seconds

This also enables CONFIG_SPL_FIT_SIGNATURE option to help discover
any possible future issue with loading TF-A into DRAM/SRAM.

Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-05-18 08:34:45 +08:00
Jonas Karlman
3b804b370d mmc: rockchip_sdhci: Disable DMA mode using a device tree property
Loading part of TF-A into SRAM from eMMC using DMA fails on RK3399
similar to other Rockchip SoCs. Checksum validation fails with:

  ## Checking hash(es) for Image atf-2 ... sha256 error!
  Bad hash value for 'hash' hash node in 'atf-2' image node
  spl_load_simple_fit: can't load image loadables index 1 (ret = -1)
  mmc_load_image_raw_sector: mmc block read error
  SPL: failed to boot from all boot devices
  ### ERROR ### Please RESET the board ###

Add a device tree property, u-boot,spl-fifo-mode, to control when the
rockchip_sdhci driver should disable the use of DMA and fallback on PIO
mode. Same device tree property is used by the rockchip_dw_mmc driver.

In commit 2cc6cde647 ("mmc: rockchip_sdhci: Limit number of blocks
read in a single command") the DMA mode was disabled using a CONFIG
option on RK3588. Revert that and instead disable DMA using the device
tree property for all RK3588 boards, also apply similar workaround for
all RK3399 boards.

Fixes: 2cc6cde647 ("mmc: rockchip_sdhci: Limit number of blocks read in a single command")
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Tested-by: Quentin Schulz <foss+uboot@0leil.net> # RK3399 Puma, RK3588 Tiger
2023-05-18 08:34:45 +08:00
Jonas Karlman
41fc80b8da mmc: rockchip_sdhci: Skip blocks read workaround on RK3399
The workaround to limit number of blocks to read in a single command
should only be applied to RK3568 and RK3588. Change to be more strict
when to apply the workaround.

Fixes: 2cc6cde647 ("mmc: rockchip_sdhci: Limit number of blocks read in a single command")
Suggested-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Tested-by: Quentin Schulz <foss+uboot@0leil.net> # RK3399 Puma, RK3588 Tiger
2023-05-18 08:34:45 +08:00
Jon Lin
c5b4a012bc phy: rockchip: naneng-combphy: Support rk3588
Add support for rk3588 phy variant.
The PHY clock is fixed at 100MHz.

Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
[kever.yang@rock-chips.com: update pcie pll parameters]
Co-developed-by: Kever Yang <kever.yang@rock-chips.com>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
[eugen.hristev@collabora.com: squashed, tidy up]
Signed-off-by: Eugen Hristev <eugen.hristev@collabora.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-05-17 17:36:18 +08:00
Eugen Hristev
d49dc884cb phy: rockchip: naneng-combphy: Add support for multiple resets
Some variants of the PHY have more than just one reset.
To cover all cases, request the rests in bulk rather than just
the reset at index 0.

Co-developed-by: Ren Jianing <jianing.ren@rock-chips.com>
Signed-off-by: Ren Jianing <jianing.ren@rock-chips.com>
Signed-off-by: Eugen Hristev <eugen.hristev@collabora.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-05-17 17:36:18 +08:00
Jon Lin
014a31907a pci: pcie_dw_rockchip: Support max_link_speed dts property
Add support for max_link_speed specified in the PCI DT binding.

Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
[eugen.hristev@collabora.com: port to latest API, set default correctly,
align to 80 chars]
Signed-off-by: Eugen Hristev <eugen.hristev@collabora.com>
[jonas@kwiboo.se: switch to dev_read_u32_default]
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-05-17 17:36:18 +08:00
Jon Lin
5374480395 pci: pcie_dw_rockchip: Add rk3588 compatible
Add compatible for RK3588 SoC.

Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-05-17 17:36:18 +08:00
Eugen Hristev
bb52f1c604 reset: rockchip: implement rk3588 lookup table
The current DT bindings for the rk3588 clock use a different ID than the
one that is supposed to be written to the hardware registers.
Thus, we cannot use directly the id provided in the phandle, but rather
use a lookup table to correctly setup the hardware.

This approach has been implemented already in Linux, by commit :
f1c506d152ff ("clk: rockchip: add clock controller for the RK3588")

Hence, implement a similar approach using the lookup table, and adapt
the existing reset driver to work with SoCs using lookup table.
The file rst-rk3588.c has been copied as much as possible from Linux.

Adapt the clk rk3588 driver as well to bind the reset driver with the
lookup table.

Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Signed-off-by: Eugen Hristev <eugen.hristev@collabora.com>
2023-05-17 17:36:18 +08:00
Eugen Hristev
6891bdf711 configs: rockchip: rock5b-rk3588: add pinctrl to SPL
Add pinctrl driver in SPL. Do not remove pinctrl properties for SPL dtb.

Signed-off-by: Eugen Hristev <eugen.hristev@collabora.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-05-17 17:36:18 +08:00
Eugen Hristev
cec4f82f11 ARM: dts: rk3588-rock-5b-u-boot: add bootph-all to pinctrl for sdmmc
To be able to initialize the pinctrl correctly at SPL level and read
u-boot proper from SD-Card, the pinctrl must be initialized.

Signed-off-by: Eugen Hristev <eugen.hristev@collabora.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-05-17 17:36:18 +08:00
Jonas Karlman
e74ac44f79 phy: Keep balance of counts when ops is missing
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Fixes: 226fce6108 ("phy: Track power-on and init counts in uclass")
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
2023-05-17 17:36:18 +08:00
Eugen Hristev
cdf9010f6e phy: rockchip-inno-usb2: add initial support for rk3588 PHY
Add initial support for the rk3588 PHY variant.
The lookup for the host-port reg inside the struct now does a do {} while()
instead of a while() {} in order to allow a first check for reg == 0.

Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Co-developed-by: Frank Wang <frank.wang@rock-chips.com>
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
Signed-off-by: Eugen Hristev <eugen.hristev@collabora.com>
2023-05-17 17:36:18 +08:00
Eugen Hristev
b59e031a7d phy: remove phy-supply related code
phy-supply is now handled at uclass level. Remove it from the drivers that
implement it at the driver level.

Acked-by: Neil Armstrong <neil.armstrong@linaro.org>
Suggested-by: Jonas Karlman <jonas@kwiboo.se>
Signed-off-by: Eugen Hristev <eugen.hristev@collabora.com>
2023-05-17 17:36:18 +08:00
Eugen Hristev
c57e0dcd93 phy: add support for phy-supply
Some phys require a phy-supply property that is a phandle to a regulator
that needs to be enabled for phy operations.
Implement basic supply lookup, enable and disabling, if DM_REGULATOR is
available.

Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
[jonas@kwiboo.se:
use regulator_set_enable_if_allowed and disable if power_on ops fails]
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Signed-off-by: Eugen Hristev <eugen.hristev@collabora.com>
2023-05-17 17:36:18 +08:00
Eugen Hristev
adef6ebc06 configs: rockchip: rock5b-rk3588: enable USB and regulators
Enable USB command, USB drivers, PHY and regulators, for USB host
operations.

Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Signed-off-by: Eugen Hristev <eugen.hristev@collabora.com>
2023-05-17 17:36:14 +08:00
Eugen Hristev
9ceef3d9a7 ARM: dts: rockchip: rk3588-rock-5b-u-boot: add USB 2.0 host
Add USB 2.0 host nodes and PHYs.

Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Co-developed-by: William Wu <william.wu@rock-chips.com>
Signed-off-by: William Wu <william.wu@rock-chips.com>
Signed-off-by: Eugen Hristev <eugen.hristev@collabora.com>
2023-05-17 09:53:32 +08:00
Tom Rini
6e1852ca2c Pull request efi-2023-07-rc3
Documentation:
 
 * update the description of signature algorithms
 
 UEFI:
 
 * fix unaligned access to GUID in HII database protocol
 * fix launching EFI binaries loaded via semihosting
 * fix filling of file path in loaded image protocol for non-block devices
 -----BEGIN PGP SIGNATURE-----
 
 iQIzBAABCAAdFiEEbcT5xx8ppvoGt20zxIHbvCwFGsQFAmRjIuIACgkQxIHbvCwF
 GsQsZQ/9HijBls1e0WV58F01w3ky0NQoJRVi0ujMEzQuPBkJX1i718f1O+QxJF43
 dpHNiPkXvC9PHDHxBevyC0x0ptsqeNB5Tg5gpl3/M1Ko+23nP4ozhJ6TrtngJ50h
 P9aadOhVAUPH1c4/tIqVFNBI8DrRl8waQ9F8hnycJQ8kw76ye5YBYWwcHKVBwoyc
 1ZIt60M3pBsopQJEVbaoUOc223yYnaV2mLweihndUsRjAI8xO8FNBcyTnDtwazLj
 5F99AnZ1JWH5fYVI+M8ssfMS14SkmdGXH3drbcsQtiUs3k1pFHihBfQdYalfgB/9
 QYsPc7A84Nua+5SajNd6aSFuZCmCXU/4yaAWKIaoKVfGVgsGrRxbqvDuKz3ax4Gb
 jLHWt+mLnk8IrLYNG91QrlA7vUxEcurSUnvq3j69MRUSJWUlDj+bkyGBzWcsdB2K
 niliWo53CFCqRmVL9wf8kLEdaOMV8KJ1V7dxZvbbUa48HccfBXzxbSYnNm1//RYL
 M3jOmBYr0p//I6vLk2P8NWpPqyJUPgrcCHF7RGS8axfa24HMhj2ECJMiXlO8beUx
 CeVov+8GhuRKAcUyf6NaUcbQhyHCk5szEbBKqlH4rwLyuuumOdyB+4SP/WDs7n+x
 +JEqK4m6yfzlkJM9UBHM/yG88DwDhEszk8u22x5/oU9SbYsvTx8=
 =gJu0
 -----END PGP SIGNATURE-----

Merge tag 'efi-2023-07-rc3' of https://source.denx.de/u-boot/custodians/u-boot-efi

Pull request efi-2023-07-rc3

Documentation:

* update the description of signature algorithms

UEFI:

* fix unaligned access to GUID in HII database protocol
* fix launching EFI binaries loaded via semihosting
* fix filling of file path in loaded image protocol for non-block devices
2023-05-16 11:23:30 -04:00
Tom Rini
5645a50a86 Merge branch '2023-05-15-assorted-bugfixes'
- Merge in a long-standing fix for some exynos platforms, correct a
  Kconfig description, fix some env issues, fix an issue in
  devfdt_get_addr_size_index_ptr and look for "panel-timings" not
  "panel-timing" per upstream binding.
2023-05-16 11:16:42 -04:00
Tom Rini
c21fc9e152 Xilinx changes for v2023.07-rc3
.mailmap
 - Fix Xilinx IDs
 
 ZynqMP:
 - Fix R5 split boot mode
 - DT fixes - sync with Linux
 
 Xilinx:
 - Enable virtio and RNG support
 - Enable ADI ethernet phy
 
 SPI/Zynq:
 - Fix dummy byte calculation
 -----BEGIN PGP SIGNATURE-----
 
 iF0EABECAB0WIQQbPNTMvXmYlBPRwx7KSWXLKUoMIQUCZGM+/gAKCRDKSWXLKUoM
 Id6XAKCEfBfLOxuya8r8jdh8N5QCjTj0FACfXAZQYVX67bUr00PHRlHmSppV65Q=
 =Thv+
 -----END PGP SIGNATURE-----

Merge tag 'xilinx-for-v2023.07-rc3' of https://source.denx.de/u-boot/custodians/u-boot-microblaze

Xilinx changes for v2023.07-rc3

.mailmap
- Fix Xilinx IDs

ZynqMP:
- Fix R5 split boot mode
- DT fixes - sync with Linux

Xilinx:
- Enable virtio and RNG support
- Enable ADI ethernet phy

SPI/Zynq:
- Fix dummy byte calculation
2023-05-16 09:10:57 -04:00
Manorit Chawdhry
6d677ea8ec environment: ti: rproc: fix remoteproc environment variables
During refactor this seemed to have been missed.

Fixes: 65dbb128fb ("include: environment: ti: Use .env for environment variables")

Signed-off-by: Manorit Chawdhry <m-chawdhry@ti.com>
2023-05-15 17:14:46 -04:00
Johan Jonker
58f4bb833b core: fdtaddr: use map_sysmem() as cast for the return (part 2)
For the devfdt_get_addr_size_index_ptr() function use
map_sysmem() function as cast for the return for use in
sandbox.

Signed-off-by: Johan Jonker <jbx6244@gmail.com>
2023-05-15 17:14:46 -04:00
Raphael Gallais-Pou
cd88058da3 drivers: core: ofnode: fix typo in panel timing decode
In case where a single timing resolution is implemented in the
device-tree, the property is named "panel-timing", as specify
in Linux kernel binding file:

Documentation/devicetree/bindings/display/panel/panel-common.yaml

  # Display Timings
  panel-timing:
    description:
      Most display panels are restricted to a single resolution and
      require specific display timings. The panel-timing subnode expresses those
      timings.
    $ref: panel-timing.yaml#

  display-timings:
    description:
      Some display panels support several resolutions with different timings.
      The display-timings bindings supports specifying several timings and
      optionally specifying which is the native mode.
    $ref: display-timings.yaml#

Fixes: 0347cc7732 ("drivers: core: ofnode: Add panel timing decode.")
Signed-off-by: Raphael Gallais-Pou <raphael.gallais-pou@foss.st.com>
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2023-05-15 17:14:46 -04:00
Christophe Leroy
40b77f2a3a envtools lack extra settings since commit 86b9c3e4e4 ("env: Allow U-Boot scripts to be placed in
After converting my targets from CFG_EXTRA_ENV_SETTINGS to
CONFIG_EXTRA_ENV_TEXT as suggested by Tom, I discovered that
fw_setenv doesn't set the entire defaut environment anymore.

I tried to fix it with the below patch, but it fails qemu-x86 CI test,
see https://source.denx.de/u-boot/custodians/u-boot-mpc8xx/-/pipelines/16326
That's the only CI test that fails AFAICS.

Could you help with a solution ? This needs to be fixed.

Thanks
Christophe

---- >8 ----
From: Christophe Leroy <christophe.leroy@csgroup.eu>
Subject: [RFC PATCH] envtools: Fix default environment

After converting some targets from CFG_EXTRA_ENV_SETTINGS to
CONFIG_EXTRA_ENV_TEXT, default environment embedded in
fw_env tool missed all extra settings.

Commit 86b9c3e4e4 ("env: Allow U-Boot scripts to be placed in
a .env file") restricted the inclusion of the content of that
file to builds without USE_HOSTCC.

But as mentionned in commit 79fc0c5f49 ("tools/env: cross-compile
fw_printenv without setting HOSTCC"), HOSTCC and USE_HOSTCC are
kept for code re-use.

Remove the restricting so that settings included in a .env
file are also added to fw_env tool.

Fixes: 86b9c3e4e4 ("env: Allow U-Boot scripts to be placed in a .env file")
Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu>
2023-05-15 17:14:46 -04:00
Henrik Grimler
c9901bd2ad samsung: common: do not reset if cros-ec uclass is missing
Otherwise non-ChromeOS samsung devices, like the odroid boards, are
stuck in a bootloop if CONFIG_CROS_EC is not enabled:

    <...>
    MMC: SAMSUNG SDHCI: 2, EXYNOS DWMMC: 0
    Loading Environment from MMC... *** Warning - bad CRC, using default environment

    cros-ec communications failure -96

    Please reset with Power+Refresh

    Cannot init cros-ec device
    resetting ...

Issue started after commit e44d7e73fe ("dm: core: Switch
uclass_*_device_err to use uclass_*_device_check").

Signed-off-by: Henrik Grimler <henrik@grimler.se>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Minkyu Kang <mk7.kang@samsung.com>
2023-05-15 17:14:46 -04:00
Henrik Grimler
7d01ee9d19 Revert "mmc: s5p_sdhci: unset the SDHCI_QUIRK_BROKEN_R1B"
This reverts commit a034ec06ff.

Commit 4a3ea75de4 ("Revert "mmc: sdhci: set to INT_DATA_END when
there are data"") reverted the alternative fix that was added for
Exynos 4 devices, causing an error when trying to boot from an sdcard:

    <...>
    Loading Environment from MMC... sdhci_send_command: Timeout for status update!
    mmc fail to send stop cmd
    <...>

Re-add the quirk to allow booting from sdcards again.

Signed-off-by: Henrik Grimler <henrik@grimler.se>
2023-05-15 17:14:46 -04:00
John Keeping
03972ff671 video: tweak CONFIG_SPL_VIDEO description
Make it clear that this is the SPL option to avoid potential confusion
when the description for CONFIG_SPL_VIDEO is the same as that for
CONFIG_VIDEO.

Signed-off-by: John Keeping <john@metanate.com>
2023-05-15 17:14:46 -04:00
Tom Rini
c9b2a78928 Merge https://source.denx.de/u-boot/custodians/u-boot-cfi-flash
- cfi: respect reg address length (Nuno)
2023-05-15 08:33:16 -04:00
Nuno Sá
43bacbe6ab mtd: cfi: respect reg address length
flash_get_size() will get the flash size from the device itself and go
through all erase regions to read protection status. However, the device
mappable region (eg: devicetree reg property) might be lower than the
device full size which means that the above cycle will result in a data
bus exception. This change fixes it by reading the 'addr_size' during
probe() and also use that as one possible upper limit.

Signed-off-by: Nuno Sá <nuno.sa@analog.com>
2023-05-15 10:00:30 +02:00
Algapally Santosh Sagar
3f71daa16b .mailmap: Map all Xilinx users mail ids to AMD
The mail ids of all the current Xilinx users are to be mapped to AMD
following the merger with AMD. The mailmap file is updated accordingly.

The ids of Marek Behún and Michal Simek are taken as reference.

Signed-off-by: Algapally Santosh Sagar <santoshsagar.algapally@amd.com>
Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@amd.com>
Link: https://lore.kernel.org/r/20230426060104.10412-3-ashok.reddy.soma@amd.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
2023-05-15 09:33:57 +02:00
Algapally Santosh Sagar
0407903e8c .mailmap: Sort the mailmap ids in dictionary order
The mailmap ids are not arranged in the dictionary order. So, sort the
mailmap ids in the dictionary order.

Signed-off-by: Algapally Santosh Sagar <santoshsagar.algapally@amd.com>
Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@amd.com>
Link: https://lore.kernel.org/r/20230426060104.10412-2-ashok.reddy.soma@amd.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
2023-05-15 09:33:57 +02:00
Stefan Herbrechtsmeier
99c1abae41 Revert "spi: zynq_qspi: Use dummy buswidth in dummy byte calculation"
This reverts commit e097847286. The
commit wrongly divides the dummy bytes by dummy bus width to calculate
the dummy bytes. The framework already converts the dummy cycles to the
number of bytes and the controller use the SPI flash command to
determine the dummy cycles via the address width.

Signed-off-by: Stefan Herbrechtsmeier <stefan.herbrechtsmeier@weidmueller.com>
Acked-by: Ashok Reddy Soma <ashok.reddy.soma@amd.com>
Link: https://lore.kernel.org/r/20230427065355.7413-1-stefan.herbrechtsmeier-oss@weidmueller.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
2023-05-15 09:33:57 +02:00
Ashok Reddy Soma
04d66e76d1 arm64: versal: Enable ADIN ethernet phy
Versal VEK280 board has Analog Devices ethernet phy. So, enable
CONFIG_PHY_ADIN config in Versal defconfig.

Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@amd.com>
Link: https://lore.kernel.org/r/20230420085645.21260-3-ashok.reddy.soma@amd.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
2023-05-15 09:33:57 +02:00
Ashok Reddy Soma
e0406f35e1 arm64: zynqmp: Enable ADIN ethernet phy
Some of the Kria SOM and ZynqMP boards are using Analog Devices ethernet
phy. So, enable CONFIG_PHY_ADIN for all ZynqMP platforms.

Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@amd.com>
Link: https://lore.kernel.org/r/20230420085645.21260-2-ashok.reddy.soma@amd.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
2023-05-15 09:33:57 +02:00
Michal Simek
b250bd6139 arm64: zynqmp: Fix User MTD partition size
The commit c8630167e0 ("arm64: zynqmp: Add mtd partition for secure OS
storage area") didn't update User partition size that's why size was beyond
actual device size.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/0a56405553b87a75e066cd71697cafe7c1c97eef.1681309812.git.michal.simek@amd.com
2023-05-15 09:33:57 +02:00
Ashok Reddy Soma
66e8b8128b arm64: zynqmp: Fix issue of apps executing from R5 core 1
In current implementation, applications can execute only on R5 core 0.
The boot address for R5 core 1 is not supplied. Pass TCM address for
R5 core 1 based on the argument to fix the issue.

Remove incomplete comment.

Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@amd.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/da865717d26648ab7a84345ca8749712efdddee5.1680699999.git.michal.simek@amd.com
2023-05-15 09:33:57 +02:00
Michal Simek
9b4d52b2e1 ARM: zynq: Sync Microzed board with Linux kernel
Fix model name, node locations and also add pinctrl description for usb.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/3295fde73db13a712b65f4967eb5f39ced895ad4.1679988091.git.michal.simek@amd.com
2023-05-15 09:33:57 +02:00
Michal Simek
0da6d5a9e2 ARM: zynq: Switch from earlyprintk to earlycon
Switch to earlycon which is preffered over earlyprintk.
It is also sync with Linux kernel (zynq-microzed).

Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/d280fa18068f80412cf12c235c5245651e7062e2.1679987839.git.michal.simek@amd.com
2023-05-15 09:33:57 +02:00
Michal Simek
9c10a69e10 xilinx: Enable virtio mmio transport and devices
Qemu can create virtio mmio transports and passing devices through it
that's why enable virtio by default on all arm64 based SoCs.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/a2ee18e7e8c1881ce72c5cd13127794a02410696.1679583129.git.michal.simek@amd.com
2023-05-15 09:33:55 +02:00
Neal Frager
d58acf644f arch: arm: zynqmp: mp.c: tcminit halt both cores in split mode
The "zynqmp tcminit split" command should halt both cores and not just RPU1
when configuring the TCM memory for split mode.

Signed-off-by: Neal Frager <neal.frager@amd.com>
Link: https://lore.kernel.org/r/20230323082506.31576-1-neal.frager@amd.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
2023-05-15 09:32:49 +02:00