Except ICH7 SPI, all SPI flashes connected to ICH9 / Fast SPI should
have "m25p,fast-read" property present in their DT nodes.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
At present if we see 'ranges' property (with no value) we assume it is a
boolean, as per the devicetree spec.
But another node may define 'ranges' with a value, forcing us to widen it
to an int array. At present this is not supported and causes an error.
Fix this and add some test cases.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reported-by: Tom Rini <trini@konsulko.com>
The autoboot tests are a recent addition to U-Boot, providing much-needed
coverage in this area.
A side effect of the keyed autoboot test is that this feature is enabled
in sandbox always. This changes the autoboot prompt and confuses the
pytests. Some tests become slower, for example the vboot tests take about
27s now instead of 3s.
We don't actually need this feature enabled to be able to run the tests.
Add a switch to allow sandbox to turn it on and off as needed. Use this
in the one test that needs it.
Add a command-line flag in case this is desired in normal use.
Signed-off-by: Simon Glass <sjg@chromium.org>
Fixes: 25c8b9f298 ("test: add first autoboot unit tests")
Reviewed-by: Steffen Jaeckel <jaeckel-floss@eyet-services.de>
- Move the PSCI runtime code for H3/A23/A33 into SRAM
- Pick the environment from the actual MMC boot device (SD card vs.
eMMC)
- Plus a small improvement from Icenowy, just for good measure.
There are more Allwinner SoCs that do not have a SCP now.
When there's no SCP_ADDR macro defined, we can assume there's no SCP
available.
Drop the scp part of FIT description when SCP_ADDR does not exist.
Signed-off-by: Icenowy Zheng <icenowy@sipeed.com>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
So far for the H3, A23, and A33 SoCs, we use DRAM to hold the secure
monitor code (providing PSCI runtime services). And while those SoCs do
not have the secure SRAM B like older SoCs, there is enough (secure)
SRAM A2 to put the monitor code and data in there instead.
Follow the design of 64-bit SoCs and use the first part for the monitor,
and the last 16 KiB for the SCP firmware. With this change, the monitor
no longer needs to reserve a region in DRAM.
Signed-off-by: Samuel Holland <samuel@sholland.org>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
[Andre: amend commit message, fix R40 and V3s build]
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Now that proper load and execution addresses are set in v1 kwbimage we
can use it for loading and booting U-Boot proper.
Use the new spl_parse_board_header() function to implement parsing the
kwbimage v1 header. Use information from this header to locate offset and
size of the U-Boot proper binary, instead of using the legacy U-Boot
header which is prepended to the U-Boot proper binary stored at fixed
offset. This has the advantage that we do not need to relay on legacy
U-Boot header anymore and therefore U-Boot proper binary can be stored at
any offset, as is the case when loading & booting U-Boot proper by
BootROM. The CONFIG_SYS_U_BOOT_OFFS option is therefore not used by SPL
code anymore.
Also allow to compile U-Boot SPL without CONFIG_SPL_SPI_FLASH_SUPPORT,
CONFIG_SPL_MMC_SUPPORT or CONFIG_SPL_SATA_SUPPORT set. In this case
BootROM is used for loading and executing U-Boot proper. This reduces the
size of U-Boot's SPL image. By default these config options are enabled
and so BootROM loading is not used. In some cases BootROM reads from SPI
NOR at lower speed than U-Boot SPL. So people can decide whether they
want to have smaller SPL binary at the cost of slower boot.
Therefore dependency on CONFIG_SPL_DM_SPI, CONFIG_SPL_SPI_FLASH_SUPPORT,
CONFIG_SPL_SPI_LOAD, CONFIG_SPL_SPI_SUPPORT, CONFIG_SPL_DM_GPIO,
CONFIG_SPL_DM_MMC, CONFIG_SPL_GPIO_SUPPORT, CONFIG_SPL_LIBDISK_SUPPORT,
CONFIG_SPL_MMC_SUPPORT, CONFIG_SPL_SATA_SUPPORT and
CONFIG_SPL_LIBDISK_SUPPORT is changed from strict to related "imply"
(which can be selectivelly turned off and causes booting via BootROM).
Options CONFIG_SYS_SPI_U_BOOT_OFFS,
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR and
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_DATA_PART_OFFSET have to to be set to
zero as they define the location where kwbimage header starts. It is the
location where BootROM expects start of the kwbimage from which it reads,
parses and executes SPL part. The same applies to option
CONFIG_SPL_SATA_RAW_U_BOOT_SECTOR, which has to be set to one.
Update all config files to set correct values of these options and set
CONFIG_SYS_U_BOOT_OFFS to the correct value - the offset where U-Boot
proper starts.
Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Marek Behún <marek.behun@nic.cz>
Reviewed-by: Stefan Roese <sr@denx.de>
Current code uses hack in board_init_f() which calls return_to_bootrom()
to skip U-Boot SPL code and return back to BootROM to load U-Boot via
UART or from NAND.
This change migrates that hack from the board_init_f() function and
changes it to return BOOT_DEVICE_BOOTROM instead of returning to BootROM
directly, so that U-Boot's SPL framework is used for returning to
BootROM.
Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Marek Behún <marek.behun@nic.cz>
Reviewed-by: Stefan Roese <sr@denx.de>
Reviewed-by: Chris Packham <judge.packham@gmail.com>
Tested-by: Chris Packham <judge.packham@gmail.com>
U-Boot's SPL framework already has an API for loading U-Boot via
BootROM.
Implement the function board_return_to_bootrom() for mvebu SPL code.
Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Marek Behún <marek.behun@nic.cz>
Reviewed-by: Stefan Roese <sr@denx.de>
Reviewed-by: Chris Packham <judge.packham@gmail.com>
Tested-by: Chris Packham <judge.packham@gmail.com>
This function does not return, so add the appropriate compiler flag.
Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Marek Behún <marek.behun@nic.cz>
Reviewed-by: Stefan Roese <sr@denx.de>
Reviewed-by: Chris Packham <judge.packham@gmail.com>
Tested-by: Chris Packham <judge.packham@gmail.com>
Register r0 should be set to return value 0x0 - NO_ERR.
Set r0 with return value after all registers are restored from the
stack, so that the return value is always correct.
Signed-off-by: Pali Rohár <pali@kernel.org>
Fixes: 944c7a3176 ("arm: mvebu: Add option to use UART xmodem protocol via kwboot")
Reviewed-by: Marek Behún <marek.behun@nic.cz>
Reviewed-by: Stefan Roese <sr@denx.de>
Reviewed-by: Chris Packham <judge.packham@gmail.com>
Tested-by: Chris Packham <judge.packham@gmail.com>
With the introduction of a generic reboot flag implemented in commit
a362ce214f ("fastboot: Implement generic fastboot_set_reboot_flag"), we
no longer need the custom PSCI implementation to handle the reboot reason.
This reverts commit 9a34dedfae.
Signed-off-by: Mattijs Korpershoek <mkorpershoek@baylibre.com>
Acked-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
At early U-Boot stage, before relocation, MMU is not yet configured
and disabled. DDR may not be configured with the correct memory
attributes (can be configured in MT_DEVICE instead of MT_MEMORY).
In this case, usage of memcpy_{from, to}io() may leads to synchronous
abort in AARCH64 in case the normal memory address is not 64Bits aligned.
To avoid such situation, forbid usage of normal memory cast to (u64 *) in
case MMU is not enabled.
Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Cc: mark.kettenis@xs4all.nl
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Align reset_cpu function with the next prototypes in
sysreset.h or in cpu_func.h to solve compilation issue:
void reset_cpu(void);
This patch solves the prototype conflict when cpu_func.h is
included.
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Rename these options so that CONFIG_IS_ENABLED can be used with them.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Heiko Schocher <hs@denx.de>
It is quite confusing that CONFIG_SYS_I2C selects the legacy I2C and
CONFIG_DM_I2C selects the current I2C. The deadline to migrate I2C is less
than a year away.
Also we want to have a CONFIG_I2C for U-Boot proper just like we have
CONFIG_SPL_I2C for SPL, so we can simplify the Makefile rules.
Rename this symbol so it is clear it is going away.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Heiko Schocher <hs@denx.de>
Rename this option so that CONFIG_IS_ENABLED can be used with it.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
Khadas vim series: Use devicetree for SMBIOS settings
Add settings and enable the default sysinfo driver so that these can come
from the device tree.
Reviewed-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Artem Lapkin <art@khadas.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Add the "/reserved-memory/optee" node to the SPL devicetree. The
purpose is to allow configuring TZC regions when booting OP-TEE.
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
OP-TEE is very particular about how the TZC should be configured.
When booting an OP-TEE payload, an incorrect TZC configuration will
result in a panic.
Most information can be derived from the SPL devicetree. The only
information we don't have is the split between TZDRAM and shared
memory. This has to be hardcoded. The rest of the configuration is
fairly easy, and only requires 3 TZC regions. Configure them.
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
The purpose of this change is to allow configuring TrustZone (TZC)
memory permissions. For example, OP-TEE expects TZC regions to be
configured in a very particular way. The API presented here is
intended to allow exactly that.
UCLASS support is not implemented, because it would not be too useful.
Changing TZC permissions needs to be done with care, so as not to cut
off access to memory we are currently using. One place where we can
use this is at the end of SPL, right before jumping to OP-TEE.
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Commit 500327e2ea ("ARM: dts: stm32mp1: DT alignment with Linux kernel v5.8-rc1")
renamed sdmmc2_d47_pins_b phandle to sdmmc2_d47_pins_c, but without updating
the AV96 DT which uses that phandle. Linux missed similar update as well and
it was only added in commit 1ad6e36ec266 ("ARM: dts: stm32: Fix sdmmc2 pins
on AV96") .
Update the AV96 DT pinmux phandle, otherwise eMMC 8bit mode does not work
and access to eMMC takes a very long time to fall back to 4bit mode.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Patrick Delaunay <patrick.delaunay@foss.st.com>
Cc: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
When a push-button is released and PA13/PA14 are defined as input (high-Z)
the LED should not be active as the circuit is open but a small current
leak through PCB or push-button close the circuit and allows a small LED
bias giving erroneous level voltage.
So it is recommended to activate an internal pull-up in order to clearly
fix the voltage at PA13/PA14 when button is released and to wait
a short delay before to read the GPIO value only when the pull-up is
correctly configured.
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
When the TAMP register 20 have an invalid value (0x0 for example after
TAMPER error) the "boot_device" U-Boot env variable have no value and
no error is displayed in U-Boot log.
The STM32MP boot command bootcmd_stm32mp failed with strange trace:
"Boot over !"
and the next command in bootcmd_stm32mp failed with few indication:
if test ${boot_device} = serial || test ${boot_device} = usb;
then stm32prog ${boot_device} ${boot_instance};
As it is difficult to investigate, the current patch avoids this issue:
- change the debug message to error: "unexpected boot mode" is displayed
- display trace "Boot over invalid!" in bootcmd_stm32mp
- execute "run distro_bootcmd" to try all the possible target
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
The MAIN R5FSS0 cluster and corresponding nodes are no longer required
to be enabled in R5 SPL after removing the support for booting any core
from this cluster on R5 SPL. So, remove these from the relevant dts
files.
This is essentially a revert of the additions done in commit 2984b82b3b
("arm: dts: k3-j721e-r5: Enable r5fss0 cluster in SPL").
Signed-off-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Link: https://lore.kernel.org/r/20210726211311.5977-5-s-anna@ti.com
The mach-k3 common code defined a weak start_non_linux_remote_cores()
function so that the proper implementation can be plugged in the
SoC-specific source files. This won't be needed anymore, so remove the
the common code.
Signed-off-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Link: https://lore.kernel.org/r/20210726211311.5977-4-s-anna@ti.com
The common J7 specific start_non_linux_remote_cores() override function
implements the logic to load and boot the Main R5FSS Core0 from R5 SPL.
This won't be supported any more for either J721E or J7200 after the R5
SPL rearchitecture for the System Firmware split into TI Foundation
Security (TIFS) and Device Management (DM) firmwares. So, cleanup the
corresponding code and the related SPL env variables.
Signed-off-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Link: https://lore.kernel.org/r/20210726211311.5977-3-s-anna@ti.com
The Main R5FSS Core0 on J721E SoCs is originally booted from R5 SPL
itself to achieve certain product-level early-boot metrics. This is
no longer supported after the R5 SPL re-architecture (support merged
for v2021.10-rc1). Move the booting of this core altogether from R5
SPL to A72 U-Boot.
The env variables are left as is for now, and will be cleaned up
in a subsequent patch.
Signed-off-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Link: https://lore.kernel.org/r/20210726211311.5977-2-s-anna@ti.com
The default U-Boot environment variables and design are all set up to
have the MCU R5FSS cluster to be in Split-mode. This is the setting
in v2021.01 U-Boot and the dt nodes are synched with the kernel binding
property names in commit 468ec2f3ef ("remoteproc: k3_r5: Sync to
upstreamed kernel DT property names") merged in v2021.04-rc2.
The mode for the cluster got switched back to LockStep mode by mistake
in commit e497876343 ("arm: dts: k3-am65: Sync Linux v5.11-rc6 dts
into U-Boot") also in v2021.04-rc2. This throws the following warning
messages when early-booting the cores using default env variables,
k3_r5f_rproc r5f@41400000: Invalid op: Trying to start secondary core 2 in lockstep mode
Load Remote Processor 1 with data@addr=0x82000000 65268 bytes: Failed!
Fix this by switching back the cluster to the expected Split-mode.
Make this mode change in the u-boot specific dtsi file to avoid such
sync overrides in the future until the kernel dts is also switched to
Split-mode by default.
Fixes: e497876343 ("arm: dts: k3-am65: Sync Linux v5.11-rc6 dts into U-Boot")
Signed-off-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Link: https://lore.kernel.org/r/20210726162213.28719-1-s-anna@ti.com
A Wilink wireless device is connected to MMCSD0 subsystem and is not
supported in U-Boot. Therefore, disable main_sdhci0 device tree node in
U-Boot.
If main_sdhci0 device tree node is disabled then the the index of
main_sdhci1 node becomes 0 which leads to break in boot flow. Therefore,
add an alias to fix the index to 1.
Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Link: https://lore.kernel.org/r/20210726152807.22991-3-a-govindraju@ti.com
Function spl_boot_mode() is called in common/spl/spl_mmc.c, to find the
boot mode for a given boot device. This function was renamed to
spl_mmc_boot_mode() by commit e97590654a.
Therefore, rename spl_boot_mode to spl_mmc_boot_mode.
Fixes: 57dba04afb ("arm: mach-k3: am642: Add support for boot device detection")
Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Link: https://lore.kernel.org/r/20210726152807.22991-2-a-govindraju@ti.com
Add u-boot tags for torrent serdes. This has properties specific to
u-boot on top of DT in v5.13 Linux Kernel.
Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Link: https://lore.kernel.org/r/20210721155849.20994-15-kishon@ti.com
Add default lane function for torrent serdes. This is in sync
with v5.13 Linux Kernel.
Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Link: https://lore.kernel.org/r/20210721155849.20994-14-kishon@ti.com
Add DT node for torrent serdes. This is in sync with v5.13 Linux Kernel.
Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Link: https://lore.kernel.org/r/20210721155849.20994-13-kishon@ti.com
Configure the parent clock of wiz3_pll0_refclk to the internal clock
required for USB3 to be functional and also remove "ti,usb2-only"
property as it now supports USB3 mode. This has properties specific to
u-boot on top of DT present in v5.13 of Linux Kernel.
Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Link: https://lore.kernel.org/r/20210721155849.20994-12-kishon@ti.com
This device tree is imported from Linux 5.13.1 and enabled via the
am335x board file and the am335x evm defconfig.
Signed-off-by: Paul Barker <paul.barker@sancloud.com>
These device trees are updated to match the versions in Linux 5.13.1.
The tick-timer entry in am335x-bone-common.dtsi is preserved.
Signed-off-by: Paul Barker <paul.barker@sancloud.com>
HS400 speed mode is now supported in J7200 SoC[1]. Therefore add
mmc-hs400-1_8v tag in sdhci0 device tree node.
Also update the delay values for various speed modes supported, based on
the revised january 2021 J7200 datasheet[2].
[1] - section 12.3.6.1.1 MMCSD Features, in
https://www.ti.com/lit/ug/spruiu1a/spruiu1a.pdf,
(SPRUIU1A – JULY 2020 – REVISED JANUARY 2021)
[2] - https://www.ti.com/lit/ds/symlink/dra821u.pdf,
(SPRSP57B – APRIL 2020 – REVISED JANUARY 2021)
Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Link: https://lore.kernel.org/r/20210525093826.10390-3-a-govindraju@ti.com
Add a bus driver for this and use it to configure the bus parameters for
the Ethernet interface. Drop the old pre-driver-model code.
Switch over to use driver model for Ethernet.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Move the PHY properties from DWC3 node to USB node in ZynqMP DTs as here
the USB3 PHY used is PSGTR, which is connected to Xilinx USB core. This
PHY initialization should be handled from Xilinx USB core as the
prerequisite register configurations are done here only.
Signed-off-by: Manish Narani <manish.narani@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
The board zynqmp-zc1751-xm016-dc2 support only USB2.0.
This patch removes USB3.0 DT configuration for DC2 board.
Signed-off-by: Piyush Mehta <piyush.mehta@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Documentation:
provide Makefile documentation
SMBIOS:
generate BIOS release date based on UEFI version
improve error handling in SMBIOS table generation
UEFI:
correct handling of signed capsule if authentication if off
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Merge tag 'efi-2021-10-rc1-3' of https://source.denx.de/u-boot/custodians/u-boot-efi
Pull request for efi-2021-10-rc1-3
Documentation:
provide Makefile documentation
SMBIOS:
generate BIOS release date based on UEFI version
improve error handling in SMBIOS table generation
UEFI:
correct handling of signed capsule if authentication if off
SMBIOS tables only support 32bit addresses. If we don't have memory here
handle the error gracefully:
* on x86_64 fail to start U-Boot
* during UEFI booting ignore the missing table
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
CNTFRQ_EL0 is only writable from the highest supported exception
level on the platform. For Armv8-A, this is typically EL3, but
technically EL2 and EL3 are optional so it may need to be
initialized at EL2 or EL1. For Armv8-R, the highest exception
level is always EL2.
This patch moves the initialization outside of the switch_el
block and uses a new macro branch_if_not_highest_el which
dynamically detects whether it is at the highest supported
exception level.
Linux's docs state that CNTFRQ_EL0 should be initialized by the
bootloader. If not set, the the U-Boot prompt countdown hangs.
Signed-off-by: Peter Hoyes <Peter.Hoyes@arm.com>
At the moment the U-Boot port for the DragonBoard 410c is designed
to be loaded as an Android boot image after Qualcomm's Little Kernel (LK)
bootloader. This is simple to set up but LK is redundant in this case,
since everything done by LK can be also done directly by U-Boot.
Dropping LK entirely has at least the following advantages:
- Easier installation/board code (no need for Android boot images)
- (Slightly) faster boot
- Boot directly in 64-bit without a round trip to 32-bit for LK
So far this was not possible yet because of unsolved problems:
1. Signing tool: The firmware expects a "signed" ELF image with extra
(Qualcomm-specific) ELF headers, usually used for secure boot.
The DragonBoard 410c does not have secure boot by default but the
extra ELF headers are still required.
2. PSCI bug: There seems to be a bug in the PSCI implementation
(part of the TrustZone/tz firmware) that causes all other CPU cores
to be started in 32-bit mode if LK is missing in the boot chain.
This causes Linux to hang early during boot.
There is a solution for both problems now:
1. qtestsign (https://github.com/msm8916-mainline/qtestsign)
can be used as a "signing" tool for U-Boot and other firmware.
2. A workaround for the "PSCI bug" is to execute the TZ syscall when
entering U-Boot. That way PSCI is made aware of the 64-bit switch
and starts all other CPU cores in 64-bit mode as well.
Simplify the dragonboard410c board by removing all the extra code that
is only used to build an Android boot image that can be loaded by LK.
This allows dropping the custom linker script, special image magic,
as well as most of the special build/installation instructions.
CONFIG_REMAKE_ELF is used to build a new ELF image that has both U-Boot
and the appended DTB combined. The resulting u-boot.elf can then be
passed to the "signing" tool (e.g. qtestsign).
The PSCI workaround is placed in the "boot0" hook that is enabled
with CONFIG_ENABLE_ARM_SOC_BOOT0_HOOK. The extra check for EL1 allows
compatibility with custom firmware that enters U-Boot in EL2 or EL3,
e.g. qhypstub (https://github.com/msm8916-mainline/qhypstub).
As a first step these changes apply only to DragonBoard410c.
Similar changes could likely also work for the DragonBoard 820c.
Note that removing LK wouldn't be possible that easily without a lot of
work already done three years ago by Ramon Fried. A lot of missing
initialization, pinctrl etc was already added back then even though
it was not strictly needed yet.
Cc: Ramon Fried <rfried.dev@gmail.com>
Signed-off-by: Stephan Gerhold <stephan@gerhold.net>
Add partition information to the spi-nor flash.
This is required for accessing NOR flash via mtdparts.
Signed-off-by: Masami Hiramatsu <masami.hiramatsu@linaro.org>
Reviewed-by: Marek Behún <marek.behun@nic.cz>
RTC devices could provide battery-backed memory that can be used for
storing the reboot mode magic value.
Add a new reboot-mode back-end that uses RTC to store the reboot-mode
magic value. The driver also supports both endianness modes.
Signed-off-by: Nandor Han <nandor.han@vaisala.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
A use case for controlling the boot mode is when the user wants
to control the device boot by pushing a button without needing to
go in user-space.
Add a new backed for reboot mode where GPIOs are used to control the
reboot-mode. The driver is able to scan a predefined list of GPIOs
and return the magic value. Having the modes associated with
the magic value generated based on the GPIO values, allows the
reboot mode uclass to select the proper mode.
Signed-off-by: Nandor Han <nandor.han@vaisala.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
minor test build fixes
sandbox fixes for SDL2 and running TPL
bloblist resize feature
binman multithreading
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Merge tag 'dm-pull-21jul21' of https://gitlab.denx.de/u-boot/custodians/u-boot-dm
dtoc improvements to show better warnings
minor test build fixes
sandbox fixes for SDL2 and running TPL
bloblist resize feature
binman multithreading
The sandbox can handle signals. Due to a damaged global data pointer
additional exceptions in the signal handler may occur leading to an endless
loop. In this case leave the handling of the secondary exception to the
operating system.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Add support for reading devicetree flags for MMC devices. With this we
can distinguish between fixed and removable drives. Note that this
information is only available when the device is probed, not when it is
bound, since it is read in the of_to_plat() method. This could be changed
if needed later.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
SDL provides a hinting feature which provides a higher-quality image
with the double-display option (-K). Enable it.
Signed-off-by: Simon Glass <sjg@chromium.org>
At present the display does not show on some machines, e.g. Ubunutu
20.04 but the reason is unknown. Add a work-around until this can be
determined.
Also include more error checking just in case.
Signed-off-by: Simon Glass <sjg@chromium.org>
The SPL header has a function for obtaining the phase in capital letters,
e.g. 'SPL'. Add one for lower-case also, as used by sandbox.
Use this to generalise the sandbox logic for determining the filename of
the next sandbox executable. This can provide support for VPL.
Signed-off-by: Simon Glass <sjg@chromium.org>
This patch reverts the following commits:
- 4b4159d0f3 ("riscv: dts: add dts for unmatched rev1")
- ffe9a394df ("board: sifive: support spl multi-dtb on unmatched board")
We won't plan to support unmatched that the revision below 3 in u-boot,
so they can be dropped because they might be useless.
Changed in v2:
- rebase codebase to the latest master branch
Signed-off-by: Zong Li <zong.li@sifive.com>
Suggested-by: David Abdurachmanov <david.abdurachmanov@sifive.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
If force_reloc flag is not set and booti is called for an address
ouside RAM (i. e. QSPI NOR flash), we should honor that and not try
to force relocation in a bogus fashion.
Signed-off-by: Vitaly Wool <vitaly.wool@konsulko.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
The RPC HF might be locked by ATF, and any access to its register
space would result in complete hang. Disable the RPC HF by default.
The ATF should be patched to set RPC node status = "okay" in the DT
fragment it passes to U-Boot in case the RPC HF access is unlocked,
and that way U-Boot could access the RPC HF safely.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
The CPU: print only has one space after it, while the other prints
from U-Boot align the value to offset 7. Align the CPU: print too.
No functional change.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Add sysinfo node and phandle to the board ID EEPROM on all boards
where this functionality is described in DT, which is Salvator-X(S),
ULCB and Ebisu. The u-boot,dm-pre-reloc is necessary here, since the
sysinfo must be available early during boot. The V3M and V3H boards
currently do not describe this board ID EEPROM in upstream DT, but
that could be easily added later, once the DTs contain the necessary
nodes.
ULCB and Ebisu needs the full EEPROM node in the u-boot extras DT,
since the EEPROM node is still missing in the upstream DTs. Ebisu
also needs extra compatible string override for the i2c_dvfs.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
The RGMII ports on LS1043ARDB platforms require both RX and TX internal
delays to be enabled. The device tree reports only the TX ID because the
RX ID used to be enabled by default.
With the addition of RX ID support for the Realtek 8211F PHY driver in
commit e32e4d0f58 ("net: phy: realtek: add rx delay support for
RTL8211F"), the RX ID is disabled by the driver if not reported explicitly.
This causes the RX to no longer work.
Change the phy-connection-type for the RGMII ports to "rgmii-id" in order
to enable both RX and TX internal delays.
Fixes: be1d758969 ("ARM: dts: add QorIQ DPAA 1 FMan v3 to LS1043ARDB")
Signed-off-by: Camelia Groza <camelia.groza@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
- Marvell SheevaPlug: Convert Ethernet and SATA to Driver Model (Tony)
- Zyxel NSA310S NAS: Convert to Driver Model (Tony)
- Turris_omnia: Add `u-boot-env` NOR partition (Marek)
- Turris_omnia: Fixup MTD partitions in Linux' DTB (Marek)
- Espressobin: Enable 'mtd' command and define SPI NOR partitions (Pali)
- Enabled distro boot for all TI platforms.
- Cleanup for AM335x Guardian Board
- PRUSS rproc on AM65 platform.
- Add PMIC support for J7200
- Misc fixes for Nokia RX-51
# Conflicts:
# arch/arm/mach-omap2/am33xx/Kconfig
U-Boot now supports parsing SPI NOR partitions from Device Tree. So enable
'mtd' command support for Espressobin board and define partition layout in
U-Boot Espressobin DTS file. Access to SPI NOR via 'sf' command is old
method and 'mtd' command is now preferred variant.
From include file remove '#define CONFIG_MTD_PARTITIONS' as this option is
now defined and enabled in defconfig file. This change is required to fix
compile error:
CC arch/arm/lib/asm-offsets.s
In file included from include/config.h:4,
from include/common.h:16,
from lib/asm-offsets.c:14:
include/configs/mvebu_armada-37xx.h:63: warning: "CONFIG_MTD_PARTITIONS" redefined
#define CONFIG_MTD_PARTITIONS /* required for UBI partition support */
In file included from ././include/linux/kconfig.h:4,
from <command-line>:
include/generated/autoconf.h:44: note: this is the location of the previous definition
#define CONFIG_MTD_PARTITIONS 1
After enabling support for mtd command, output from 'mtd list' on
Espressobin board is:
=> mtd list
List of MTD devices:
* w25q32dw
- device: spi-flash@0
- parent: spi@10600
- driver: jedec_spi_nor
- path: /soc/internal-regs/spi@10600/spi-flash@0
- type: NOR flash
- block size: 0x1000 bytes
- min I/O: 0x1 bytes
- 0x000000000000-0x000000400000 : "w25q32dw"
- 0x000000000000-0x0000003f0000 : "firmware"
- 0x0000003f0000-0x000000400000 : "u-boot-env"
=>
Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Konstantin Porotchkin <kostap@marvell.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Specify a separate partition `u-boot-env` for U-Boot's env settings for
the Turris Omnia board.
Do this only in U-Boot's specific DTS. We do not want to do this in
Linux' official DTS, because Omnia's stock U-Boot stores env at a
different address, and there are still boards with stock U-Boot.
In a subsequent patch will add board code that fixes Linux's DTB before
booting Linux.
Signed-off-by: Marek Behún <marek.behun@nic.cz>
Reviewed-by: Stefan Roese <sr@denx.de>
Add device tree kirkwood-nsa310s.dts for Zyxel NSA310S board to
convert to Driver Model.
Signed-off-by: Tony Dinh <mibodhi@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
As the deadline for migration to DM_USB, when using a USB host
controller has now gone two years past the deadline, enforce migration.
This is done by:
- Ensuring that all host controller options (other than the very legacy
old MUSB ones) now select USB_HOST. USB_HOST now enforces DM_USB and
OF_CONTROL.
- Remove other parts of Kconfig logic that had platforms pick DM_USB.
- To keep Kconfig happy, have some select statements test for USB_HOST
as well.
- Re-order some Kconfig entries and menus so that we can cleanly pick
host or gadget roles. For the various HCD options that have platform
glue options, group them together and update dependencies in some
cases.
- As SPL_DM_USB is not required, on platforms that had not yet enabled
it, disable it.
Cc: Marek Vasut <marex@denx.de>
Cc: Icenowy Zheng <icenowy@aosc.io>
Cc: Samuel Holland <samuel@sholland.org>
Cc: FUKAUMI Naoki <naobsd@gmail.com>
Cc: Andre Przywara <andre.przywara@arm.com>
Cc: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
This board has not been converted to CONFIG_DM_MMC by the deadline.
Remove it. As this is also the last in family remove the related
support as well.
Cc: Angelo Durgehello <angelo.dureghello@timesys.com>
Cc: TsiChung Liew <Tsi-Chung.Liew@nxp.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
This board has not been converted to CONFIG_DM_MMC by the deadline.
Remove it. As this is also the last in family remove the related
support as well.
Cc: Angelo Durgehello <angelo.dureghello@timesys.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
This board has not been converted to CONFIG_DM_MMC by the deadline.
Remove it.
Cc: Angelo Durgehello <angelo.dureghello@timesys.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
This board has not been converted to CONFIG_DM_MMC by the deadline.
Remove it.
Cc: Angelo Durgehello <angelo.dureghello@timesys.com>
Cc: TsiChung Liew <Tsi-Chung.Liew@nxp.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
Add DT binding for GT64120 and MSC01 PCI controllers. Only
GT64120 is enabled by default to support Qemu. The MSC01 node
will be dynamically enabled by Malta board code dependent
on the plugged core card.
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Add clock function to setup relevant clocks for USB3.0 controllers and
PHYs on i.MX8MQ
Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Patrick Wildt <patrick@blueri.se>
Tested-by: Patrick Wildt <patrick@blueri.se>
Remove the mmc alias no more required as the sequence number
of mmc device is used for boot_instance.
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Use the device sequence number in boot_instance variable
and no more the SDMMC instance provided by ROM code/TF-A.
After this patch we don't need to define the mmc alias in
device tree, for example:
mmc0 = &sdmmc1;
mmc1 = &sdmmc2;
mmc2 = &sdmmc3;
to have a correct mapping between the ROM code boot device =
"${boot_device}${boot_instance}" and the MMC device in U-Boot.
With this patch the 'mmc0' device (used in mmc commands) is
always used when only one instance sdmmc is activated in device
tree, even if it is only the sdmmc2 or sdmmc3.
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Use the existing defines PMIC_SIZE and OTP_SIZE and a new define
CMD_SIZE for virtual partition size.
This patch corrects the size for OTP partition in alternate name
(1024 instead of 512) and avoids other alignment issues.
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Enable the clocks during syscon probe when they are present in device tree.
This patch avoids a freeze when the SYSCFG clock is not enabled by
TF-A / OP-TEE.
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
The expected sequence to close the device
1/ Load key in DDR with any supported load command
2/ Update OTP with key: STM32MP> stm32key read <addr>
At this point the device is able to perform image authentication but
non-authenticated images can still be used and executed.
So it is the last moment to test boot with signed binary and
check that the ROM code accepts them.
3/ Close the device: only signed binary will be accepted !!
STM32MP> stm32key close
Warning: Programming these OTP is an irreversible operation!
This may brick your system if the HASH of key is invalid
This command should be deactivated by default in real product.
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Allow to read the OTP value and lock status with the command
$> stm32key read.
This patch also protects the stm32key fuse command.
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Add a helper function to access to BSEC misc driver.
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Lock the OTP value of key's hash after the command
$> stm32key fuse <address>
This operation forbids a second update of these OTP as they are
ECC protected in BSEC: any update of these OTP with a different value
causes a BSEC disturb error and the closed chip will be bricked.
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Simplify parsing the command argument by using
the macro U_BOOT_CMD_WITH_SUBCMDS.
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
This command is used to evaluate the secure boot on stm32mp SOC,
it is deactivated by default in real products.
We activate this command only in STMicroelectronics defconfig
used with the evaluation boards.
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reduce the content of short help message for stm32prog command and
removed the carriage return to fix the display of 'help' command when
this command is activated.
Fixes: 954bd1a923 ("stm32mp: add the command stm32prog")
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
In this case the value seems save to pass to os_free(). Add a comment.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reported-by: Coverity (CID: 165109)
Add voltage and thermal management (VTM) node. The efuse values for the
OPPs are stored under the VTM, and is needed for AVS class 0 support.
Signed-off-by: Gowtham Tammana <g-tammana@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Link: https://lore.kernel.org/r/20210714205300.17424-4-g-tammana@ti.com
secureworld_exit() is only used in one file, so make it static
to that file and remove it from sys_proto.h. This
may help with some further optimization in the future.
Signed-off-by: Adam Ford <aford173@gmail.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Link: https://lore.kernel.org/r/20210625192308.277136-3-aford173@gmail.com
try_unlock_memory() is only used in one file, so make it static
in that file,remove it from the sys_proto header file, and relocate
it into the #ifdef section that call it. This will make it only built
under the conditions when it is called, and it may help with some
further optimization in the future.
Signed-off-by: Adam Ford <aford173@gmail.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Link: https://lore.kernel.org/r/20210625192308.277136-2-aford173@gmail.com
The `struct udevice *` reference is needed for either of the
K3_LOAD_SYSFW, K3_AM64_DDRSS config guards. Adding the missing
K3_AM64_DDRSS guard.
Signed-off-by: Gowtham Tammana <g-tammana@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Link: https://lore.kernel.org/r/20210624171614.14244-1-g-tammana@ti.com
Add the DT nodes for the ICSSG0, ICSSG1 and ICSSG2 processor subsystems
that are present on the K3 AM65x SoCs. The three ICSSGs are identical
to each other for the most part, with the ICSSG2 supporting slightly
enhanced features for supporting SGMII PRU Ethernet. Each ICSSG instance
is represented by a PRUSS subsystem node. These nodes are enabled by
default.
DT nodes are fetch from Linux 5.13 Kernel.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Link: https://lore.kernel.org/r/20210622063431.3151-5-lokeshvutla@ti.com
So far all the u-boot specific properties for both r5 and a53 are
placed in k3-am654-base-board-u-boot.dtsi. But there are few a53
nodes that should be updated but doesn't belong to r5. So create a
separate r5 specific u-boot dtsi.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Link: https://lore.kernel.org/r/20210622063431.3151-4-lokeshvutla@ti.com
The final 128KB in SRAM is reserved by default for DMSC-lite code and
secure proxy communication buffer. The memory region used for DMSC-lite
code can be optionally freed up by secure firmware API[1]. However, the
buffer for secure proxy communication is not configurable. This default
hardware configuration is unique for AM64.
Therefore, indicate the area reserved for DMSC-lite code and secure proxy
communication buffer in the oc_sram device tree node.
[1] - http://downloads.ti.com/tisci/esd/latest/6_topic_user_guides/security_handover.html#triggering-security-handover
Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Acked-by: Suman Anna <s-anna@ti.com>
Link: https://lore.kernel.org/r/20210616163821.20457-3-a-govindraju@ti.com
Earlier, the region 0x701c0000 to 0x701dffff was firewalled off because of
a bug in SYSFW. In the v2021.05 release of SYSFW this bug has been fixed
and this region can now be used for other allocations.
Therefore, move TF-A's load address to 0x701c0000 and update its location
in the device tree node. Also, increase the size allocated for TF-A to
account for future expansions.
Fixes: defd62ca13 ("arm: dts: k3-am64-main: Update the location of ATF in SRAM and increase its max size")
Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Suman Anna <s-anna@ti.com>
Link: https://lore.kernel.org/r/20210616163821.20457-2-a-govindraju@ti.com
pinmux update for guardian board
- control ASP Board Power: GPIO, on/off ASP Board Power
- control Coincell Voltage Measurement: GPIO, enable/disable
ADC measurements
- powerOff Device GPIO-PowerOff, cut the PMIC supply
Signed-off-by: Moses Christopher <BollavarapuMoses.Christopher@in.bosch.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Link: https://lore.kernel.org/r/20210611161350.2141-7-Gireesh.Hiremath@in.bosch.com
This is a revert of a recent logic change in setup_zimage(). We do
actually need to install this information always. Change it to install
from the Coreboot tables if available, else the normal source.
Fixes: e7bae8283f ("x86: Allow installing an e820 when booting from coreboot")
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
All the x86 devicetree files are built at once, whichever board is
actually being built. If coreboot is the target build, CONFIG_ROM_SIZE
is not defined and samus cannot build Chromium OS verified boot. Add
this condition to avoid errors about CONFIG_ROM_SIZE being missing.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
Use VENDOR_COREBOOT instead of TARGET_COREBOOT so we can have multiple
coreboot boards, sharing options. Only SYS_CONFIG_NAME needs to be
defined TARGET_COREBOOT.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Add a function comment for get_coreboot_info() and a declaration for
cb_get_sysinfo(), since this may be called from elsewhere.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
A recent change to disable cache setup when booting from coreboot
assumed that this has been done by SPL. The result is that for the
coreboot board, the cache is disabled (in start.S) and never
re-enabled.
If the cache was turned off, as it is on boards without SPL, we should
turn it back on. Add this new condition.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
These constants conflict with error codes returned by the MP
implementation when something is wrong. In particular, mp_first_cpu()
returns MP_SELECT_BSP when running without multiprocessing enabled.
Since this is -2, it is interpreted as an error by callers, which
expect a positive CPU number for the first CPU.
Correct this by using a different range for the pre-defined CPU
numbers, above zero and out of the range of possible CPU values. For
now it is safe to assume there are no more than 64K CPUs.
This fixes the 'mtrr' command when CONFIG_SMP is not enabled.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
When starting U-Boot from a previous-stage bootloader we presumably don't
need to set up the variable MTRRs. In fact this could be harmful if the
existing settings are not what U-Boot uses.
Skip that step in this case.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
If fixup offset is zero then there is nothing to fix. All calculation in
this case just increase addresses by value zero which results in identity.
So in this case skip whole fixup re-calculation as it is not needed.
This is just an optimization for special case when fix_offset is zero which
skips code path which does only identity operations (meaning nothing). No
functional changes.
Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Konstantin Porotchkin <kostap@marvell.com>
Reviewed-by: Stefan Roese <sr@denx.de>
The U-Boot "stemmy" board is mainly intended to simplify booting
mainline Linux on various smartphones from Samsung based on ST-Ericsson
Ux500. While the mainline kernel is working great, there are still some
features missing there. In particular, it is currently not possible to
charge the battery when using the mainline kernel.
This means that it is still necessary to boot the downstream/vendor
kernel from Samsung sometimes to charge the device. That kernel is
ancient, still uses board files + ATAGS instead of device trees and
relies on a strange very long kernel command line hardcoded in the
Samsung bootloader.
Actually, since mainline is booted with device trees there is a very
simple way to make the old downstream kernel work as well: We can
simply take most of the ATAGS passed to U-Boot from the Samsung
bootloader and copy them as-is when booting a kernel without device
tree. That way the long command line and other needed ATAGS are copied
as-is without having to bother with them.
The only exception is the ATAG_INITRD - since the initrd is loaded
by U-Boot, the atag for that should be generated in U-Boot so it points
to the correct address. All other ATAGS are copied as-is and not
generated in U-Boot.
Also use the chance and provide a serial# for U-Boot by parsing the
ATAG_SERIAL that is also passed by the Samsung bootloader.
Signed-off-by: Stephan Gerhold <stephan@gerhold.net>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
At the moment the "stemmy" board attempts to detect the RAM size with
a simple memory test (get_ram_size()). Unfortunately, this does not work
correctly for devices with 768 MiB RAM (e.g. Samsung Galaxy Ace 2
(GT-I8160), "codina"). Reading/writing memory after the 768 MiB RAM
succeeds but actually overwrites some earlier parts of the memory.
For U-Boot this does not result in any major problems, but on Linux
this will eventually lead to strange crashes because of the memory
corruption.
Since the "stemmy" U-Boot port is designed to be chainloaded from
the original Samsung bootloader, the most reliable way to get the
available amount of RAM is to look at the ATAGS passed by the Samsung
bootloader. Fortunately, the header used to generate ATAGS in U-Boot
(asm/setup.h) can also be easily used to parse them.
Also clarify and simplify stemmy.h a bit to make it more clear where
some of the magic values in there are actually coming from.
Signed-off-by: Stephan Gerhold <stephan@gerhold.net>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Add the device tree for Akebi96. Akebi96 is a 96boards certified
development board based on UniPhier LD20.
( https://www.96boards.org/product/akebi96/ )
Signed-off-by: Masami Hiramatsu <masami.hiramatsu@linaro.org>
Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
According to arch/arm/lib/crt0_64.S, the BSS section is "UNAVAILABLE"
and uninitialized before relocation. Also, it overlaps with the
appended DTB before relocation, so writing data into a variable
in the BSS section might corrupt the appended DTB.
Unfortunately, pinctrl-apq8016.c and pinctrl-apq8096.c do place the
"pin_name" variable in the BSS section (since it's uninitialized).
It's also used before relocation, when setting up the pinctrl for
the serial driver.
On DB410c this causes "GPIO_5" to be written into some part of an
appended DTB, e.g.:
80111820: edfe0dd0 9f100000 38000000 c00e0000 ...........8....
80111830: 28000000 11000000 10000000 00000000 ...(............
80111840: 4f495047 8800355f 00000000 00000000 GPIO_5..........
80111850: 00000000 00000000 01000000 00000000 ................
80111860: 03000000 04000000 00000000 02000000 ................
80111870: 03000000 04000000 0f000000 02000000 ................
80111880: 03000000 2d000000 1b000000 6c617551 .......-....Qual
80111890: 6d6d6f63 63655420 6c6f6e68 6569676f comm Technologie
Depending on the part of the DTB that is corrupted this might not
cause any problems, but it can also result in strange reboots
without any serial output.
Fortunately, in practice this does not cause issues on DB410c yet
because board_fdt_blob_setup() in dragonboard410c.c currently
overrides the appended DTB with the one passed by the previous
bootloader (LK) (which does not get corrupted).
DB820c does not have board_fdt_blob_setup() so I would expect it to
be affected by this problem. Perhaps everyone was just fortunate to
not compile an U-Boot configuration where the pin_name corrupts an
important part of the DTB.
Make sure "pin_name" is explicitly placed in the .data section
instead of .bss to fix this.
Cc: Ramon Fried <rfried.dev@gmail.com>
Signed-off-by: Stephan Gerhold <stephan@gerhold.net>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
In case the iMX8M boot from eMMC boot partition and the primary image
is corrupted, the BootROM is capable of starting a secondary image in
the other eMMC boot partition as a fallback.
However, the BootROM leaves the eMMC BOOT_PARTITION_ENABLE setting as
it was, i.e. pointing to the boot partition containing the corrupted
image, and the BootROM does not provide any indication that this sort
of fallback occured.
According to AN12853 i.MX ROMs Log Events, Rev. 0, May 2020, it is
possible to determine whether fallback event occurred by parsing the
ROM event log. In case ROM event ID 0x51 is present, fallback event
did occur.
This patch implements ROM event log parsing and search for event ID
0x51 for all iMX8M SoCs, and based on that corrects the eMMC boot
partition selection. This way, the SPL loads the remaining boot
components from the same eMMC boot partition from which it was
started, even in case of the fallback.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Faiz Abbas <faiz_abbas@ti.com>
Cc: Harald Seiler <hws@denx.de>
Cc: Lokesh Vutla <lokeshvutla@ti.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Ye Li <ye.li@nxp.com>
Fix the dsa switch config:
- remove the unnecessary phy-mode from the switch itself
- added the necessary fixed-link node to the non-cpu ports required
for U-Boot DSA
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
The Gateworks GW7901 is an ARM based single board computer (SBC)
featuring:
- i.MX8M Mini SoC
- LPDDR4 DRAM
- eMMC FLASH
- SPI FRAM
- Gateworks System Controller (GSC)
- Atmel ATECC Crypto Authentication
- USB 2.0
- Microchip GbE Switch
- Multiple multi-protocol RS232/RS485/RS422 Serial ports
- onboard 802.11ac WiFi / BT
- microSD socket
- miniPCIe socket with PCIe, USB 2.0 and dual SIM sockets
- Wide range DC power input
- 802.3at PoE
To add support for this board:
- add dts from Linux (accepted for v5.14)
- add SPL PMIC config
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Make macros actually use passed parameter instead of local variables
that happen
to be named the same as symbols in macro expansion.
Signed-off-by: Kacper Kubkowski <kkubkowski@fluence.pl>
With the first redesign the debug UART had changed from
UART2 to UART1.
As the first hardware revision is considered as alpha and
will not be supported in future. The old setup will not
be preserved.
Signed-off-by: Teresa Remmet <t.remmet@phytec.de>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
This update includes eqos support and some minor changes.
Synced with kernel commit
412627f6ffe3 ("arm64: dts: imx8mp-phyboard-pollux-rdk: Add missing pinctrl entry")
Signed-off-by: Teresa Remmet <t.remmet@phytec.de>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
Factor out the common node settings for dm-spl and dm-pre-reloc
and move them to imx8mp-u-boot.dtsi
Signed-off-by: Teresa Remmet <t.remmet@phytec.de>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
If reset-gpio is defined by device-tree use that if
CONFIG_PCIE_IMX_PERST_GPIO is not defined.
Note that after this the following boards which define
CONFIG_PCIE_IMX_PERST_GPIO in their board header file as well as their
device-tree should be able to remove CONFIG_PCIE_IMX_PERST_GPIO without
consequence:
- mx6sabresd
- mx6sxsabresd
- novena
- tbs2910
- vining_2000
Note that the ge_bx50v3 board uses CONFIG_PCIE_IMX_PERST_GPIO and does
not have reset-gpios defined it it's pcie node in the dt thus removing
CONFIG_PCIE_IMX_PERST_GPIO globally can't be done until that board adds
reset-gpios.
Cc: Ian Ray <ian.ray@ge.com> (maintainer:GE BX50V3 BOARD)
Cc: Sebastian Reichel <sebastian.reichel@collabora.com> (maintainer:GE BX50V3 BOARD)
Cc: Fabio Estevam <festevam@gmail.com> (maintainer:MX6SABRESD BOARD)
Cc: Marek Vasut <marex@denx.de> (maintainer:NOVENA BOARD)
Cc: Soeren Moch <smoch@web.de> (maintainer:TBS2910 BOARD)
Cc: Silvio Fricke <open-source@softing.de> (maintainer:VINING_2000 BOARD)
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Some IPs have their accessible address space restricted by the
interconnect. Let's make sure U-Boot only ever uses the space below
the 4G address boundary (which is 3GiB big), even when the effective
available memory is bigger.
We implement board_get_usable_ram_top() for all i.MX8M SoCs, as the
whole family is affected by this.
Signed-off-by: Frieder Schrempf <frieder.schrempf@kontron.de>
Aside from the usual fixes and updates one visible change is the
MMC update, which fixes some lingering bugs and gives a decent speed
increase on some boards (9->19 MB/s on H6, 21->43 MB/s on A64 eMMC).
I am keeping an watchful eye on bug reports here, to spot any correctness
regressions.
Another change is finally the enablement of the first USB host port on
many boards without micro-USB (data) sockets, like the Pine64 family.
That doubles the number of usable USB ports from 1 to 2 on those boards.
Some smaller fixes, 4GB DRAM support (on the H616) and a new board (ZeroPi)
conclude this first round of changes.
Compile-tested for all 157 sunxi boards, boot-tested on Pine H64,
Pine64-LTS, OrangePi Zero 2 and BananaPi M2 Berry.
Summary:
- DT update for H3/H5/H6
- Enable first USB port on boards without micro-USB
- ZeroPi board support
- 4GB DRAM support for H616 boards
- MMC fixes and speed improvement
- some fixes
To avoid the complexity of DMA operations (with chained descriptors), we
use repeated MMIO reads and writes to the SD_FIFO_REG, which allows us
to drain or fill the MMC data buffer FIFO very easily.
However those MMIO accesses are somewhat costly, so this limits our MMC
performance, to between 17 and 22 MB/s, but down to 9.5 MB/s on the H6
(partly due to the lower AHB1 frequency).
As it turns out we read the FIFO status register after *every* word we
read or write, which effectively doubles the number of MMIO accesses,
thus effectively more than halving our performance.
To avoid this overhead, we can make use of the FIFO level bits, which are
in the very same FIFO status registers.
So for a read request, we now can collect as many words as the FIFO
level originally indicated, and only then need to update the status
register.
We don't know for sure the size of the FIFO (and it seems to differ
across SoCs anyway), so writing is more fragile, which is why we still
use the old method for that. If we find a minimum FIFO size available on
all SoCs, we could use that, in a later optimisation.
This patch increases the eMMC read speed on a Pine64-LTS from about
22MB/s to 44 MB/s. SD card reads don't gain that much, but with 23 MB/s
we now reach the practical limit for 3.3V SD cards.
On the H6 we double our transfer speed, from 9.5 MB/s to 19.7 MB/s.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
All SoCs since the Allwinner A64 (H5, H6, R40, H616) feature the so
called "new timing mode", so enable this in Kconfig for those SoCs.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Most Allwinner SoCs which use the so called "new timing mode" in their
MMC controllers actually use the double-rate PLL6/PERIPH0 clock as their
parent input clock. This is interestingly enough compensated by a hidden
"by 2" post-divider in the mod clock, so the divider and actual output
rate stay the same.
Even though for the H6 and H616 (but only for them!) we use the doubled
input clock for the divider computation, we never accounted for the
implicit post-divider, so the clock was only half the speed on those SoCs.
This didn't really matter so far, as our slow MMIO routine limits the
transfer speed anyway, but we will fix this soon.
Clean up the code around that selection, to always use the normal PLL6
(PERIPH0(1x)) clock as an input. As the rate and divider are the same,
that makes no difference.
Explain the hardware differences in a comment.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
The H616 is our first supported Allwinner SoC which goes beyond the 4GB
address space "barrier", by having more than 32 address bits.
Lift the preliminary 3GB DRAM limit for the H616, and update the page
table setup on the way, to actually map that last GB as well.
As not all devices are actually capable of dealing with more than 32
bits (the DMA in the EMAC for instance), we also limit U-Boot's own
DRAM usage to 4GB on the way.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
ZeroPi is a new board of high performance with low cost
designed by FriendlyElec., using the Allwinner H3 SOC.
ZeroPi features
- Allwinner H3, Quad-core Cortex-A7@1.2GHz
- 256MB/512MB DDR3 RAM
- microsd slot
- 10/100/1000Mbps Ethernet
- Debug Serial Port
- DC 5V/2A power-supply
Signed-off-by: Yu-Tung Chang <mtwget@gmail.com>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Most clock factors and dividers in the H6 PLLs use a "+1 encoding",
which we were missing on two occasions.
This fixes the MMC clock setup on the H6, which could be slightly off due
to the wrong parent frequency:
mmc 2 set mod-clk req 52000000 parent 1176000000 n 2 m 12 rate 49000000
Also the CPU frequency (PLL1) was a tad too high before.
For PLL5 (DRAM) we already accounted for this +1, but in the DRAM code
itself, not in the bit field macro. Move this there to be aligned with
what the other SoCs and other PLLs do.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Update the H3 DT files from the Linux 5.12 release.
The changes update some boards, and don't affect U-Boot, but fix Gigabit
Ethernet when this DT is passed on to the Linux kernel.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Update the H5 DT files from the Linux 5.12 release.
The changes don't affect U-Boot at all, but fix Gigabit Ethernet when
this DT is passed on to the Linux kernel. It also introduces DVFS.
This also updates the shared sunxi-h3-h5.dtsi, but that only adds nodes
that are of no concern to U-Boot.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Update the H6 DT files from the Linux 5.12 release.
The changes are minimal (many LED node renames), but also help to enable
USB port 0 in U-Boot (later), enable the RSB device (not yet used in
U-Boot), and also introduce an MMC frequency limit.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
As seen with clang-12:
warning: __asm_invalidate_l3_dcache changed binding to STB_WEAK
As we indeed use ENTRY and then declare the function weak manually. Use
the WEAK declarative from <linux/linkage.h> instead.
Signed-off-by: Tom Rini <trini@konsulko.com>
