Commit graph

89966 commits

Author SHA1 Message Date
AKASHI Takahiro
c1d2ed0c63 power: domain: add SCMI driver
Add power domain driver based on SCMI power domain management protocol.

Signed-off-by: AKASHI Takahiro <takahiro.akashi@linaro.org>
2023-10-24 17:05:24 -04:00
AKASHI Takahiro
fc358b1a76 firmware: scmi: add power domain protocol support
In this patch, added are helper functions to directly manipulate
SCMI power domain management protocol. DM compliant power domain
driver will be implemented on top of those interfaces in a succeeding
patch.

Signed-off-by: AKASHI Takahiro <takahiro.akashi@linaro.org>
2023-10-24 17:05:24 -04:00
Alexander Gendin
04291ee0ab cmd: mbr: Allow 4 MBR partitions without need for extended
Current code allows up to 3 MBR partitions without extended one.
If more than 3 partitions are required, then extended partition(s)
must be used.
This commit allows up to 4 primary MBR partitions without the
need for extended partition.

Add mbr test unit. In order to run the test manually, mmc6.img file
of size 12 MiB or greater is required in the same directory as u-boot.
Test also runs automatically via ./test/py/test.py tool.
Running mbr test is only supported in sandbox mode.

Signed-off-by: Alex Gendin <agendin@matrox.com>
[ And due to some further changes for testing ]
Signed-off-by: Simon Glass <sjg@chromium.org>
2023-10-24 17:05:24 -04:00
Andrey Skvortsov
9859edd3fc pstore: Use root address-cells/size-cells as defaults for reserved-memory
u-boot adds reserve-memory node, if it's missing, with following
properties:

```
    reserved-memory {
         #address-cells = <2>;
         #size-cells = <2>;
         ranges;
    }
```

But with these default address-cells and size-cells values, pstore
isn't working on A64. Root node for A64 defines 'address-cells' and
'size-cells' as 1.

dtc complains if reserved-memory has different address-cells and
size-cells.

```
     Warning (ranges_format): /reserved-memory:ranges: empty "ranges"
     property but its #address-cells (2) differs from / (1)
```

This patch takes into account address-cells and size-cells of the root
node and uses them as values for new reserved-memory node.

Signed-off-by: Andrey Skvortsov <andrej.skvortzov@gmail.com>
2023-10-24 16:34:45 -04:00
John Clark
801c482207 .gitignore: ignore misc include, simple-bin, and tools/generated build artifacts
make rock5b-rk3588_defconfig
make
git status

before
~~~~~~~
On branch master
Your branch is ahead of 'origin/master' by 1 commit.
  (use "git push" to publish your local commits)

Untracked files:
  (use "git add <file>..." to include in what will be committed)
	include/autoconf.mk
	include/autoconf.mk.dep
	include/config.h
	mkimage-in-simple-bin-spi.mkimage-rockchip-tpl
	mkimage-in-simple-bin-spi.mkimage-u-boot-spl
	mkimage-in-simple-bin.mkimage-rockchip-tpl
	mkimage-in-simple-bin.mkimage-u-boot-spl
	simple-bin-spi.map
	simple-bin.fit.fit
	simple-bin.fit.itb
	simple-bin.map
	tools/generated/

after
~~~~~~~
On branch master
Your branch is ahead of 'origin/master' by 1 commit.
  (use "git push" to publish your local commits)

nothing to commit, working tree clean

Signed-off-by: John Clark <inindev@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2023-10-24 16:34:45 -04:00
John Clark
27537d4673 Makefile: remove misc include and simple-bin build artifacts on clean
make rock5b-rk3588_defconfig
make
make clean
git status

before
~~~~~~~
On branch master
Your branch is up to date with 'origin/master'.

Untracked files:
  (use "git add <file>..." to include in what will be committed)
	include/autoconf.mk
	include/autoconf.mk.dep
	include/config.h
	mkimage-in-simple-bin-spi.mkimage-rockchip-tpl
	mkimage-in-simple-bin-spi.mkimage-u-boot-spl
	mkimage-in-simple-bin.mkimage-rockchip-tpl
	mkimage-in-simple-bin.mkimage-u-boot-spl
	simple-bin.fit.fit
	simple-bin.fit.itb

after
~~~~~~~
On branch master
Your branch is ahead of 'origin/master' by 1 commit.
  (use "git push" to publish your local commits)

nothing to commit, working tree clean

Signed-off-by: John Clark <inindev@gmail.com>
2023-10-24 16:34:45 -04:00
Tom Rini
0b9441ae76 riscv: Remove common.h usage
We can remove common.h from most cases of the code here, and only a few
places need an additional header instead.

Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Rick Chen <rick@andestech.com>
2023-10-24 16:34:45 -04:00
Tom Rini
8991fed97d mips: Remove common.h usage
We can remove common.h from most cases of the code here, and only a few
places need an additional header instead.

Signed-off-by: Tom Rini <trini@konsulko.com>
2023-10-24 16:34:45 -04:00
Tom Rini
577dddb5b7 microblaze: Remove common.h usage
We can remove common.h from most cases of the code here, and only a few
places need an additional header instead.

Signed-off-by: Tom Rini <trini@konsulko.com>
Acked-by: Michal Simek <michal.simek@amd.com>
2023-10-24 16:34:45 -04:00
Tom Rini
07011890a6 m68k: Remove common.h usage
We can remove common.h from most cases of the code here, and only a few
places need an additional header instead.

Signed-off-by: Tom Rini <trini@konsulko.com>
Acked-by: Angelo Dureghello <angelo@kernel-space.org>
2023-10-24 16:34:45 -04:00
Tom Rini
60c08dd771 arc: Remove common.h usage
We can remove common.h from most cases of the code here, and only a few
places need an additional header instead.

Signed-off-by: Tom Rini <trini@konsulko.com>
Acked-by: Alexey Brodkin <abrodkin@synopsys.com>
2023-10-24 16:34:45 -04:00
Tom Rini
12c00f9e8b include: Add <linux/types.h> in a few places
These files references a number of types that are defined in
<linux/types.h> (and so forth), so include it here rather than rely on
indirect inclusion.

Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2023-10-24 16:34:45 -04:00
Simon Glass
2f34b0331a patman: Add a little documentation on the checkpatch tests
These texts lack comments. Add some so that it is clearer what is going
on.

Signed-off-by: Simon Glass <sjg@chromium.org>
2023-10-24 16:34:45 -04:00
Tom Rini
a8384f8da1 checkpatch.pl: Make common.h check boarder
At this point in time we should not add common.h to any new files, so
make checkpatch.pl complain.

Signed-off-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
2023-10-24 16:34:45 -04:00
Yurii Monakov
2dd86b9075 cli: Consume invalid escape sequences early
Unexpected 'Esc' key presses are accumulated internally, even if it is
already clear that the current escape sequence is invalid. This results
in weird behaviour. For example, the next character after 'Esc' key
simply disappears from input and 'Unknown command' is printed
after 'Enter'.

This commit fixes some issues with extra 'Esc' keys entered by user:

1. Sequence <Esc><Esc><Enter> right after autoboot stop gives:
=>
nknown command 'ry 'help'
=>
2. Sequence <Esc><p><r><i><Enter> gives:
=> ri
Unknown command 'ri' - try 'help'
=>
3. Extra 'Esc' key presses break backspace functionality.

Signed-off-by: Yurii Monakov <monakov.y@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2023-10-24 16:34:45 -04:00
Tom Rini
5cab3515f8 Merge tag 'u-boot-rockchip-20231024' of https://source.denx.de/u-boot/custodians/u-boot-rockchip
- Add Board: rk3588 NanoPC-T6, Orange Pi 5, Orange Pi 5 Plus;
- clk driver fix for rk3568 and rk3588;
- rkmtd cmd support for rockchip nand device;
- dts update and sync from linux;
2023-10-24 09:39:52 -04:00
Tom Rini
1b2a3d08c0 u-boot-imx-20231024
-------------------
 
 CI: https://source.denx.de/u-boot/custodians/u-boot-imx/-/pipelines/18211
 
 - Fixes for MC2432 Eeprom
 - i.MX93 ADC
 - Secondary boot mode on i.MX8M
 -----BEGIN PGP SIGNATURE-----
 
 iG0EABECAC0WIQS2TmnA27QKhpKSZe309WXkmmjvpgUCZTd93A8cc2JhYmljQGRl
 bnguZGUACgkQ9PVl5Jpo76bb9gCdEQkNaVg/xSF2FXyFmwSxMDfasfsAmgKWOgPJ
 fcLnp+4ZLv6rBw9mzvCK
 =t171
 -----END PGP SIGNATURE-----

Merge tag 'u-boot-imx-20231024' of https://gitlab.denx.de/u-boot/custodians/u-boot-imx

u-boot-imx-20231024
-------------------

CI: https://source.denx.de/u-boot/custodians/u-boot-imx/-/pipelines/18211

- Fixes for MC2432 Eeprom
- i.MX93 ADC
- Secondary boot mode on i.MX8M
2023-10-24 09:39:02 -04:00
Johan Jonker
d039b1b551 rockchip: configs: sandbox: enable rkmtd command
Enable rkmtd command for testing with sandbox_defconfig
and sandbox64_defconfig.

Signed-off-by: Johan Jonker <jbx6244@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2023-10-24 15:55:17 +08:00
Johan Jonker
73e1f877ce rockchip: doc: add rkmtd.rst
Add documention for Rockchip rkmtd virtual block device.

Signed-off-by: Johan Jonker <jbx6244@gmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2023-10-24 15:55:17 +08:00
Johan Jonker
500439eb34 rockchip: test: dm: add rkmtd test
Add Rockchip rkmtd test:
Create/attach/detach RKMTD device.
Send/read data with Rockchip boot block header.
Test that reusing the same label should work.
Basic test of 'rkmtd' commands.

Signed-off-by: Johan Jonker <jbx6244@gmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2023-10-24 15:55:17 +08:00
Johan Jonker
aacf214d0c rockchip: cmd: add rkmtd command
The command rkmtd creates a virtual block device to transfer
Rockchip boot block data to and from NAND with block orientated
tools like "ums" and "rockusb".

It uses the Rockchip MTD driver to scan for boot blocks and copies
data from the first block in a GPT formated virtual disk.
Data must be written in U-boot "idbloader.img" format and start at
partition "loader1" offset 64. The data header is parsed
for length and offset. When the last sector is received
it erases up to 5 erase blocks on NAND and writes bootblocks
in a pattern depending on the NAND ID. Data is then verified.
When a block turns out bad the block header is discarded.

Signed-off-by: Johan Jonker <jbx6244@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2023-10-24 15:55:17 +08:00
Johan Jonker
81bd22e935 rockchip: block: blk-uclass: add bounce buffer flag to blk_desc
Currently bounce buffer support is enabled for all block devices
when available. Add a flag to blk_desc to enable only on demand.

Signed-off-by: Johan Jonker <jbx6244@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-10-24 15:55:17 +08:00
Johan Jonker
80201eccaa rockchip: block: add rkmtd class and drivers
Add rkmtd class and drivers to create a virtual block device
to transfer Rockchip boot block data to and from NAND with
block orientated tools like "ums" and "rockusb".

Signed-off-by: Johan Jonker <jbx6244@gmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-10-24 15:55:17 +08:00
Johan Jonker
900c303a02 rockchip: dm: prepare rkmtd UCLASS
Prepare a rkmtd UCLASS in use for writing Rockchip boot blocks
in combination with existing userspace tools and rockusb command.

Signed-off-by: Johan Jonker <jbx6244@gmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2023-10-24 15:55:16 +08:00
Johan Jonker
d27f227271 mtd: nand: raw: rockchip_nfc: add NAND_SKIP_BBTSCAN option
On Rockchip SoCs the first boot stages are written on NAND
with help of manufacturer software that uses a different format
then the MTD framework. Skip the automatic BBT scan with the
NAND_SKIP_BBTSCAN option to be able to pass the driver probe
function and to let the original data unchanged.

Signed-off-by: Johan Jonker <jbx6244@gmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-10-24 15:55:16 +08:00
Jonas Karlman
b51cf8bb09 board: rockchip: Add Xunlong Orange Pi 5 Plus
Xunlong Orange Pi 5 Plus is a single-board computer based on the
Rockchip RK3588 SoC. The board provides abundant interfaces, including
two HDMI output ports, one HDMI input port, two 2.5G Ethernet ports,
M.2 M-Key slot, M.2 E-Key slot, two USB 3.0, two USB 2.0, and two Type-C.

Features tested on a Orange Pi 5 Plus 4GB v1.2:
- SD-card boot
- eMMC boot
- SPI Flash boot
- PCIe/NVMe
- USB 2.0 host
- Ethernet

Device tree is imported from linux v6.7-rockchip-dts64-1 tag.

Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-10-24 15:55:16 +08:00
Jonas Karlman
28c5f941ed board: rockchip: Add Xunlong Orange Pi 5
Xunlong Orange Pi 5 is a single-board computer based on the Rockchip
RK3588S SoC. The board provides abundant interfaces, HDMI output, GPIO
interface, M.2 PCIe2.0, Type-C, Gigabit LAN port, 2*USB2.0, 1*USB3.0,
etc.

Features tested on a Orange Pi 5 4GB v1.2:
- SD-card boot
- SPI Flash boot
- PCIe/NVMe
- USB 2.0 host
- Ethernet

Device tree is imported from linux v6.7-rockchip-dts64-1 tag.

Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-10-24 15:55:16 +08:00
Ricardo Pardini
7b4544f122 mtd: spi-nor: Add support for XMC XM25QU128C
Add support for XMC XM25QU128C (128M-bit) Serial Flash memory. Used on
the Xunlong Orange Pi 3B, 5 and 5 Plus boards.

Datasheet:
https://www.xmcwh.com/uploads/806/XM25QU128C_Ver2.0.pdf

Signed-off-by: Ricardo Pardini <ricardo@pardini.net>
[jonas@kwiboo.se: update commit message]
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-10-24 15:55:16 +08:00
Jonas Karlman
c1710bfc4f rockchip: rk3588-rock-5b: Sync USB3 nodes from mainline linux patches
The device tree for rk3588 and rock-5b contain usb3 nodes that have
deviated too much from current state of submitted mainline linux usb3
patches, see [1].

Sync usb3 related nodes from latest patches and collaboras rk3588 tree
so that dwc3-generic driver can be updated to include support for the
rockchip,rk3588-dwc3 compatible in the future, use rockchip,rk3568-dwc3
compatible until final node is merged in linux maintainer tree.

[1] https://lore.kernel.org/lkml/20231009172129.43568-1-sebastian.reichel@collabora.com/

Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-10-24 15:55:16 +08:00
Jonas Karlman
191ece249a rockchip: rk3588-rock-5b: Enable support for PCIe SATA cards
Enable support for PCIe SATA cards and the on-board SATA controller.

This also revert use of CONFIG_PCI_INIT_R in order to speed up boot from
eMMC or SD-cards. Standard boot will initialize pci after faster boot
media have been enumerated.

Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Christopher Obbard <chris.obbard@collabora.com>
Tested-by: Christopher Obbard <chris.obbard@collabora.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-10-24 15:55:16 +08:00
Jonas Karlman
8c19506bc5 rockchip: rk3588-rock-5a: Enable support for USB 2.0 ports
Enable Kconfig options for the two USB 2.0 ports and bottom USB 3.0 port
on ROCK 5 Model A.

Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-10-24 15:55:16 +08:00
Jonas Karlman
57379c0021 rockchip: rk3588: Sync device tree from v6.7-rockchip-dts64-1 tag
Sync rk3588 device tree from v6.7-rockchip-dts64-1 tag.

Adds PCIe, button and led nodes to rk3588-evb1-v10 and rk3588-rock-5b
boards. Also remove includes from u-boot.dtsi-files that is no longer
needed.

Linux commits:
42145b7a8235 ("arm64: dts: rockchip: add PCIe network controller to rock-5b")
199cbd5f195a ("arm64: dts: rockchip: add PCIe for M.2 M-key to rock-5b")
da447ec38780 ("arm64: dts: rockchip: add PCIe for M.2 E-Key to rock-5b")
86a2024d95e2 ("arm64: dts: rockchip: add PCIe2 network controller to rk3588-evb1")
46bb398ea1d8 ("arm64: dts: rockchip: add PCIe3 bus to rk3588-evb1")
1c9a53ff7ece ("arm64: dts: rockchip: Add sdio node to rock-5b")
3eaf2abd11aa ("arm64: dts: rockchip: Add sfc node to rk3588s")
bf012368bb0a ("arm64: dts: rockchip: Add I2S2 M0 pin definitions to rk3588s")
3d77a3e51b0f ("arm64: dts: rockchip: Add UART9 M0 pin definitions to rk3588s")
0002c377e862 ("arm64: dts: rockchip: Remove duplicate regulator vcc3v3_wf from rock-5b")
a6169ab36923 ("arm64: dts: rockchip: Enable UART6 on rock-5b")
dd6dc0c4c126 ("arm64: dts: rockchip: Add AV1 decoder node to rk3588s")
afa933c208e5 ("arm64: dts: rockchip: add ADC buttons to rk3588-evb1")
7952cbbda301 ("arm64: dts: rockchip: add status LED to rock-5b")

Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Christopher Obbard <chris.obbard@collabora.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-10-24 15:55:16 +08:00
Tom Fitzhenry
6ea2477a96 dt-bindings: leds: import common led bindings from linux v6.5
This brings in more colours, e.g. ORANGE needed for the QuartzPro64 DT.

Linux commits:
472d7b9e8141 ("dt-bindings: leds: Expand LED_COLOR_ID definitions")

Signed-off-by: Tom Fitzhenry <tom@tom-fitzhenry.me.uk>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-10-24 15:55:16 +08:00
Tom Rini
351da15f71 Prepare v2024.01-rc1
Signed-off-by: Tom Rini <trini@konsulko.com>
2023-10-23 16:29:47 -04:00
Tom Rini
4bb6f61220 configs: Resync with savedefconfig
Rsync all defconfig files using moveconfig.py

Signed-off-by: Tom Rini <trini@konsulko.com>
2023-10-23 15:08:23 -04:00
Tom Rini
5ef34c2329 Merge branch '2023-10-23-bootstd-fixes-and-improvements'
- Fix a few bootstd issues that have been reported and ahci support to
  bootstd
2023-10-23 15:01:08 -04:00
Tony Dinh
1052920aa9 bootstd: sata: bootdev scanning for ahci sata with no drive attached
It's normal to have no SATA drive attached to the controller, so return a
successful status when there is no block device found after probing.

Note: this patch depends on the previous patch
https://patchwork.ozlabs.org/project/uboot/patch/20230917230649.30357-1-mibodhi@gmail.com/

Resend the right patch.

Signed-off-by: Tony Dinh <mibodhi@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Stefan Roese <sr@denx.de>
2023-10-23 13:07:23 -04:00
Tony Dinh
a7527fbbf2 bootstd: sata: Add bootstd support for ahci sata
Add ahci sata bootdev and corresponding hunting function.

Signed-off-by: Tony Dinh <mibodhi@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Stefan Roese <sr@denx.de>
2023-10-23 13:07:12 -04:00
Simon Glass
7a790f018a bootstd: Scan all bootdevs in a boot_targets entry (take 2)
When the boot_targets environment variable is used with the distro-boot
scripts, each device is included individually. For example, if there
are three mmc devices, then we will have something like:

   boot_targets="mmc0 mmc1 mmc2"

In contrast, standard boot supports specifying just the uclass, i.e.:

   boot_targets="mmc"

The intention is that this should scan all MMC devices, but in fact it
currently only scans the first.

Update the logic to handle this case, without required BOOTSTD_FULL to
be enabled.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reported-by: Date Huang <tjjh89017@hotmail.com>
Reported-by: Vincent Stehlé <vincent.stehle@arm.com>
Reported-by: Ivan Ivanov <ivan.ivanov@suse.com>
Tested-by: Ivan T.Ivanov <iivanov@suse.de>
2023-10-23 13:05:13 -04:00
Simon Glass
16e19350d9 bootstd: Correct logic for single uclass
The current logic for "bootflow mmc" is flawed since it checks the
uclass of the bootdev instead of its parent, the media device. Correct
this and add a test that covers this scenario.

Signed-off-by: Simon Glass <sjg@chromium.org>
Tested-by: Ivan T.Ivanov <iivanov@suse.de>
2023-10-23 13:05:13 -04:00
Simon Glass
7ae83bfaf4 bootstd: Expand boot-ordering test to include USB
Scan the USB bus as well, so we can check that different uclasses work
correctly in boot_targets

update the function comment with more detail.

Signed-off-by: Simon Glass <sjg@chromium.org>
Tested-by: Ivan T.Ivanov <iivanov@suse.de>
2023-10-23 13:05:13 -04:00
Simon Glass
abd1e94f70 Revert "bootstd: Scan all bootdevs in a boot_targets entry"
This commit was intended to allow all bootdevs in each boot_targets
entry to be scanned. However it causes bad ordering with bootdevs, e.g.
scanning Ethernet bootdevs when it should be keeping to mmc.

Revert it so we can try another approach.

This reverts commit e824d0d0c2.

Signed-off-by: Simon Glass <sjg@chromium.org>
Tested-by: Ivan T.Ivanov <iivanov@suse.de>
2023-10-23 13:05:13 -04:00
Tom Rini
d6b3297dde CI: Re-enable maintainer check
At this point we have all of the defconfigs maintained again, so
re-enable the check to prevent further regressions.

Signed-off-by: Tom Rini <trini@konsulko.com>
2023-10-23 11:41:01 -04:00
Tom Rini
eea6227d1f ae350: Update defconfig list
Update the list of defconfigs, this was missed with the last pull
request of the u-boot-riscv tree.

Signed-off-by: Tom Rini <trini@konsulko.com>
2023-10-23 11:40:44 -04:00
Tom Rini
cedc741231 Second set of u-boot-at91 features for the 2024.01 cycle
-----BEGIN PGP SIGNATURE-----
 
 iQFQBAABCgA6FiEEqxhEmNJ6d7ZdeFLIHrMeAg6sL8gFAmU2fxwcHGV1Z2VuLmhy
 aXN0ZXZAY29sbGFib3JhLmNvbQAKCRAesx4CDqwvyKr+B/42+WkPiAiwt79R6Kh5
 UKo404oN1na28D3V12EvikiCH2QWubi38EV7VfcB3jqEpxj4j+rY0cSLZv+u7d4/
 bfQN3FPrcTwYnXYLbYkUKC+MAVzGLiVzFBBhIt5cPrT4iVXctwYY6LJ58aX8uRo6
 KU6CwXYc3cnmIUqpXE4EYbbQU4TAp55SV2n8QLFFI9DHcy2kELfdrZduFn+Hm9Ij
 9sQHH5JxbrGHv5XpcjJkARW3M4K3K4TPzweFGN61VMJwWqzD3L4YPshwIGDfhRui
 LECKCdr/rWkavumXCfw2pD3RYFTqnqnUzaEN/3ueL9FCJ2uFH1EyaoSuXFEn3+Ul
 m1LE
 =CMMd
 -----END PGP SIGNATURE-----

Merge tag 'u-boot-at91-2024.01-b' of https://source.denx.de/u-boot/custodians/u-boot-at91

Second set of u-boot-at91 features for the 2024.01 cycle

This feature set a new board named Conclusive KSTR sama5d27 with some
small prerequisites patches.
2023-10-23 11:39:38 -04:00
Tom Rini
a8f6dab0d4 Merge branch 'master' of https://source.denx.de/u-boot/custodians/u-boot-sunxi
This is mostly about support for the Allwinner R528/T113s SoC, which is
reportedly the same die as the Allwinner D1, but with the two
Arm Cortex-A7 cores activated instead of the RISC-V one.
Using sunxi code outside of arch/arm proved to be difficult, so apart
from enabling this Arm SoC, the patches also prepare for more refactoring
to get the D1 nicely supported some day:
- We get rid of some Kconfig (hard-)coded GPIO pins, responsible for
  enabling regulators.
- The GPIO code is moved out of arch/arm, into drivers/gpio.
- Some definitions are moved out of header files under asm/arch.
- Some T113s/D1 specific definitions are guarded by a generic Kconfig
  symbol (CONFIG_SUNXI_GEN_NCAT2).
- The DRAM controller initialisation code is located under drivers/ram.
- The base SoC .dtsi files are shared (under arch/riscv, as in Linux).

Of course there are also the usual new SoC specific patches, like clock
and pinmux descriptions, alongside a rework of the pinctrl code, since
Allwinner changed the GPIO register layout, for the first time since
sunxi's inception.
On top of this the PSCI code sees some update, to provide SMP services
for R528/T113s boards. Many thanks to Sam for providing this code and
staying strong through the review cycles.
The final patch enables support for one popular board, I hope to see
more DTs and defconfigs contributed in the future!

Many thanks to all the various contributors, testers and reviewers,
that series was a real team effort!
2023-10-23 11:39:33 -04:00
Artur Rojek
27347893f0 board: Add support for Conclusive KSTR-SAMA5D27
Introduce support for Conclusive KSTR-SAMA5D27 Single Board Computer.

Co-developed-by: Jakub Klama <jakub@conclusive.pl>
Signed-off-by: Jakub Klama <jakub@conclusive.pl>
Co-developed-by: Marcin Jabrzyk <marcin@conclusive.pl>
Signed-off-by: Marcin Jabrzyk <marcin@conclusive.pl>
Signed-off-by: Artur Rojek <artur@conclusive.pl>
2023-10-23 17:07:06 +03:00
Artur Rojek
a6965af7e4 arm: dts: at91: sama5: Add flexcom4 node
Set up flexcom4 for Microchip SAMA5D27 SoC and prepare it for usage in
I2C mode.

Signed-off-by: Artur Rojek <artur@conclusive.pl>
2023-10-23 17:07:06 +03:00
Artur Rojek
6092ce50ef event: add new EVT_SETTINGS_R event
Introduce EVT_SETTINGS_R, triggered post-relocation and before console
init.

This event gives an option to perform any platform-dependent setup,
which needs to take place before show_board_info(). Usage examples
include readout of EEPROM stored settings.

Signed-off-by: Artur Rojek <artur@conclusive.pl>
Reviewed-by: Simon Glass <sjg@chromium.org>
2023-10-23 17:07:06 +03:00
Artur Rojek
cd3dbb5687 common: add prototype & rename populate_serial_number()
Rename populate_serial_number() to a more descriptive
serial_read_from_eeprom() and provide the missing function prototype.

This is useful for boards that wish to read their serial number from
EEPROM at init.

Signed-off-by: Artur Rojek <artur@conclusive.pl>
Reviewed-by: Simon Glass <sjg@chromium.org>
2023-10-23 17:07:06 +03:00