Commit graph

121 commits

Author SHA1 Message Date
Tom Rini
eca99c0256 Merge git://git.denx.de/u-boot-samsung 2015-02-13 13:11:33 -05:00
Akshay Saraswat
2e82e92526 Exynos: Clock: Cleanup soc_get_periph_rate
Since we have src, div and pre-div mask bits defined corresponding
to peripherals, calculation of clock specific to I2C appears
redundant and confusing. Using clk_bit_info struct we can write
calculations generic to all peripherals which makes code easy to
understand and free from peripheral specific exceptions.

Signed-off-by: Akshay Saraswat <akshay.s@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2015-02-13 17:23:06 +09:00
Akshay Saraswat
c5d32170bb Exynos: clock: change mask bits as per peripheral
We have assumed and kept mask bits for divider and pre-divider
as 0xf and 0xff, respectively. But these mask bits change from
one peripheral to another, and hence, need to be specified in
accordance with the peripherals.

Signed-off-by: Akshay Saraswat <akshay.s@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2015-02-13 17:23:06 +09:00
Akshay Saraswat
d95279685b Exynos5: Use clock_get_periph_rate generic API
Replacing SoC and peripheral specific function calls with generic
clock_get_periph_rate calls to get the peripheral clocks.
Also, removing dead code of peripheral and SoC specific function
implementations which was used earlier for fetching peripheral clocks.
This code is not being used anymore because of the introduction
of generic clock_get_periph_rate function.

Signed-off-by: Akshay Saraswat <akshay.s@samsung.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2015-02-13 17:23:06 +09:00
Akshay Saraswat
9deff10746 Exynos5: Fix exynos5_get_periph_rate calculations
exynos5_get_periph_rate function reads incorrect div for
SDMMC2 & 3. It also reads prediv and does division only for
SDMMC0 & 2 when actually various other peripherals need that.
Adding changes to fix these mistakes in periph rate calculation.

Signed-off-by: Akshay Saraswat <akshay.s@samsung.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2015-02-13 17:23:06 +09:00
Akshay Saraswat
ecdfb4e9d2 Exynos542x: Add and enable get_periph_rate support
We planned to fetch peripheral rate through one generic API per
peripheral. These generic peripheral functions are in turn
expected to fetch apt values from a function refactored as
per SoC versions. This patch adds support for fetching peripheral
rates for Exynos5420 and Exynos5800.

Signed-off-by: Akshay Saraswat <akshay.s@samsung.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2015-02-13 17:23:06 +09:00
Akshay Saraswat
325eb18c77 Exynos542x: Move exynos5420_get_pll_clk up and rename
Moving exynos5420_get_pll_clk function definition up in the
code to keep it together with rest of SoC_get_pll_clk functions.
This makes code more legible and also removes the need of
declaration when called before the position of definition in
code. Also, renaming exynos5420_get_pll_clk to
exynos542x_get_pll_clk because it is being used for both Exynos
5420 and 5800.

Signed-off-by: Akshay Saraswat <akshay.s@samsung.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2015-02-13 17:23:06 +09:00
Akshay Saraswat
d606ded1db Exynos5: Fix compiler warnings due to clock_get_periph_rate
Apparently, members of clk_bit_info array do not map correctly
to the members of enum periph_id. This mapping got broken after
we changed periph_id(s) to reflect interrupt number instead of
their position in a sequence. This patch intends to fix above
mentioned issue.

Signed-off-by: Akshay Saraswat <akshay.s@samsung.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2015-02-13 17:23:06 +09:00
Joonyoung Shim
483e49bfd7 EXYNOS5: Add function to enable exynos5420 usbdev phy ctrl
Exynos5420 has different registers with other exynos5 SoCs to control
usb device phy, so need separated function to enable exynos5420 usb
device phy.

Signed-off-by: Joonyoung Shim <jy0922.shim@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2015-02-13 17:19:55 +09:00
Jaehoon Chung
a276172cf3 arm: exynos: fix the div value for set_mmc_clk
The most exynos used the  "Ratio + 1" as div value.
And value at register is "Ratio".
So if want to set exact value, it needs to subtract one.

Value at register ("Ratio") = div - 1

Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2015-02-13 17:15:14 +09:00
Simon Glass
b724bd7d63 dm: Kconfig: Move CONFIG_SYS_MALLOC_F_LEN to Kconfig
Move this option to Kconfig and update all boards.
Signed-off-by: Simon Glass <sjg@chromium.org>
2015-02-12 15:17:28 -07:00
Simon Glass
aab7e80d5f dm: exynos: Move driver model CONFIGs to Kconfig
Remove driver model CONFIGs from the board config headers and use Kconfig
instead.

Signed-off-by: Simon Glass <sjg@chromium.org>
2015-02-12 10:35:34 -07:00
Przemyslaw Marczak
fda0e27bfd exynos5: pinmux: check flag for i2c config
Some versions of Exynos5 supports High-Speed I2C,
on few interfaces, this change allows support this.
The new flag is: PINMUX_FLAG_HS_MODE

Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Akshay Saraswat <akshay.s@samsung.com>
Cc: Minkyu Kang <mk7.kang@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-01-29 17:10:00 -07:00
Joonyoung Shim
fb56435f50 arm: exynos: clock: support SPLL as mmc source clock for exynos5420
MMC of exynos5420 can select SPLL as source clock, so add to support
SPLL in exynos5420_get_mmc_clk(). It was tested on Odroid-XU3 board.

Signed-off-by: Joonyoung Shim <jy0922.shim@samsung.com>
Acked-by: Jaehoon Chung <jh80.chung@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2014-12-24 10:56:24 +09:00
Hyungwon Hwang
6207604f9c Odroid-XU3: Add support for Odroid-XU3
This patch adds support for Odroid-XU3.

Signed-off-by: Hyungwon Hwang <human.hwang@samsung.com>
Reviewed-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk>
Tested-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Kevin Hilman <khilman@linaro.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2014-12-22 20:37:10 +09:00
Tom Rini
878cd63e02 Merge branch 'master' of http://git.denx.de/u-boot-samsung 2014-11-26 11:21:16 -05:00
Tom Rini
fce0a90a68 Merge branch 'master' of git://git.denx.de/u-boot-arm 2014-11-24 17:05:11 -05:00
Hans de Goede
ea624e1951 ARM: Add arch/arm/cpu/armv7/Kconfig with non-secure and virt options
Add arch/arm/cpu/armv7/Kconfig with non-secure and virt options, this is a
preparation patch for adding an env variable to choose between secure /
non-secure boot on non-secure boot capable systems, specifically this
prepares for adding CONFIG_ARMV7_BOOT_SEC_DEFAULT as a proper Kconfig option.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
2014-11-24 09:09:49 +01:00
Masahiro Yamada
b41411954d linux/kernel.h: sync min, max, min3, max3 macros with Linux
U-Boot has never cared about the type when we get max/min of two
values, but Linux Kernel does.  This commit gets min, max, min3, max3
macros synced with the kernel introducing type checks.

Many of references of those macros must be fixed to suppress warnings.
We have two options:
 - Use min, max, min3, max3 only when the arguments have the same type
   (or add casts to the arguments)
 - Use min_t/max_t instead with the appropriate type for the first
   argument

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Acked-by: Pavel Machek <pavel@denx.de>
Acked-by: Lukasz Majewski <l.majewski@samsung.com>
Tested-by: Lukasz Majewski <l.majewski@samsung.com>
[trini: Fixup arch/blackfin/lib/string.c]
Signed-off-by: Tom Rini <trini@ti.com>
2014-11-23 06:48:30 -05:00
Suriyan Ramasami
bdba132828 arm: odroid: enable/disable usb host phy for exynos4412
Enable/disable the usb host phy on the odroid U/X2 boards which are based
on the Exynos4412 SOC.

Signed-off-by: Suriyan Ramasami <suriyan.r@gmail.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2014-11-17 19:33:21 +09:00
Vadim Bendebury
4f29862487 Peach-Pi: Use the enhanced usb_copy() prototype
Exynos5800 IROM has a different, from 5250 and 5420, prototype of the
usb_copy() function. Luckily the earlier version did not expect any
arguments, which means the same code could be used with old and new
SoCs, the old ones just ignoring the arguments.

Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Signed-off-by: Akshay Saraswat <akshay.s@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2014-11-17 19:03:38 +09:00
Akshay Saraswat
0e03e82465 Exynos5: ddr3: Choose between single or double channel config
Add a 4G configuration and choose it based on the number of banks
declared in config file. A board with 4 SDRAM banks declared (as
per CONFIG_NR_DRAM_BANKS) will end up with the 2G confiuration.

Signed-off-by: Doug Anderson <dianders@chromium.org>
Signed-off-by: Akshay Saraswat <akshay.s@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2014-11-17 19:03:38 +09:00
Alim Akhtar
061091098a DMC: Exynos5: Enable update mode for DREX controller
As per Exynos5800 UM ver 0.00 section 17.13.2.1
CONCONTROL register bit 3 [update_mode], Exynos5800 does not
support the PHY initiated update. And it is recommanded to
set this field to 1'b1 during initialization. This patch sets this bit.
Applying MC-initiated mode makes DDL tracking ON, that helps in
compensate MIF voltage variation.

Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com>
Signed-off-by: Doug Anderson <dianders@chromium.org>
Signed-off-by: Akshay Saraswat <akshay.s@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2014-11-17 19:03:38 +09:00
Akshay Saraswat
79043d84da Config: Exynos5800: Enable build for Peach-Pi
This adds following things :
- New config and defconfig for Peach-Pi board.
- Alterations in Kconfig and MAINTAINERS.
- Addition of CONFIG_EXYNOS5800.
- ADdition of exynos5800-peach-pi in dts list.

Signed-off-by: Akshay Saraswat <akshay.s@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2014-11-17 19:03:38 +09:00
Akshay Saraswat
aa14b42d53 Exynos5800: Introduce new proid for Exynos5800
This patch intends to add a new proid for Exynos5800 which is a
variant of Exynos5420. Product id for Exynos5800 is 0x5422.
Both Exynos5420 and Exynos5800 are pin to pin compitable. This
gives us an advantage of reusing Exynos5420 clock, pinmux, memory
and other settings.

Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com>
Signed-off-by: Akshay Saraswat <akshay.s@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2014-11-17 19:03:38 +09:00
Georges Savoundararadj
2e07c249a6 kconfig: arm: introduce symbol for ARM CPUs
This commit introduces a Kconfig symbol for each ARM CPU:
CPU_ARM720T, CPU_ARM920T, CPU_ARM926EJS, CPU_ARM946ES, CPU_ARM1136,
CPU_ARM1176, CPU_V7, CPU_PXA, CPU_SA1100.
Also, it adds the CPU feature Kconfig symbol HAS_VBAR which is selected
for CPU_ARM1176 and CPU_V7.

For each target, the corresponding CPU is selected and the definition of
SYS_CPU in the corresponding Kconfig file is removed.

Also, it removes redundant "string" type in some Kconfig files.

Signed-off-by: Georges Savoundararadj <savoundg@gmail.com>
Acked-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
Cc: Masahiro Yamada <yamada.m@jp.panasonic.com>
2014-10-29 09:02:09 -04:00
Masahiro Yamada
02627356b6 kconfig: add CONFIG_SUPPORT_SPL
CONFIG_SPL should not be enabled for boards that do not have SPL.
CONFIG_SUPPORT_SPL introduced by this commit should be "select"ed
by boards with SPL support and CONFIG_SPL should depend on it.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Acked-by: Simon Glass <sjg@chromium.org>
2014-10-27 17:54:10 -04:00
Simon Glass
7f1961018c dm: exynos: Make sure that GPIOs are requested
With driver model GPIOs must be requested before use. Make sure this is
done correctly.

(Note that the soft SPI part of universal is omitted, since this driver
is about to be replaced with a driver-model-aware version)

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-10-22 10:36:33 -06:00
Simon Glass
903fd79564 dm: exynos: Tidy up GPIO headers
The wrong header is being included, thus requiring the code to re-declare
the generic GPIO interface in each GPIO header.

Fix this.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-10-22 10:36:18 -06:00
Simon Glass
1d55110003 config: Move smdkv310 to use common exynos4 file
Most of the smdkv310 features are common with other exynos4 boards. To
permit easier addition of driver model support, use the common file and
add a device tree file.

Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2014-10-08 17:25:47 +09:00
Masahiro Yamada
783e6a72b8 kconfig: move CONFIG_OF_* to Kconfig
This commit moves:
  CONFIG_OF_CONTROL
  CONFIG_OF_SEPARATE
  CONFIG_OF_EMBED
  CONFIG_OF_HOSTFILE

Because these options are currently not supported for SPL,
the "Device Tree Control" menu does not appear in the SPL
configuration.

Note:
zynq-common.h should be adjusted so as not to change the
default value of CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Acked-by: Simon Glass <sjg@chromium.org>
Cc: Stephen Warren <swarren@nvidia.com>
Cc: Minkyu Kang <mk7.kang@samsung.com>
Acked-by: Michal Simek <michal.simek@xilinx.com>
2014-09-25 09:27:50 -04:00
Masahiro Yamada
461be2f96e kconfig: remove redundant "string" type in arch and board Kconfigs
Now the types of CONFIG_SYS_{ARCH, CPU, SOC, VENDOR, BOARD, CONFIG_NAME}
are specified in arch/Kconfig.

We can delete the ones in arch and board Kconfig files.

This commit can be easily reproduced by the following command:

find . -name Kconfig -a ! -path ./arch/Kconfig | xargs sed -i -e '
/config[[:space:]]SYS_\(ARCH\|CPU\|SOC\|\VENDOR\|BOARD\|CONFIG_NAME\)/ {
    N
    s/\n[[:space:]]*string//
}
'

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2014-09-13 16:43:55 -04:00
Ajay Kumar
496f0e47e1 arm: exynos: Add get_lcd_clk and set_lcd_clk callbacks for Exynos5420
Add get_lcd_clk and set_lcd_clk callbacks for Exynos5420 needed by
exynos video driver.
Also, configure ACLK_400_DISP1 as the parent for MUX_ACLK_400_DISP1_SUB_SEL.

Signed-off-by: Ajay Kumar <ajaykumar.rs@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2014-09-05 20:37:07 +09:00
Ajay Kumar
e6756f6a2e arm: exynos: Add RPLL for Exynos5420
RPLL is needed to drive the LCD panel on Exynos5420 based boards.

Signed-off-by: Ajay Kumar <ajaykumar.rs@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2014-09-05 20:37:07 +09:00
Przemyslaw Marczak
73eca21128 odroid: kconfig: add odroid_defconfig
This config is valid for two devices:
- Odroid X2,
- Odroid U3.

Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com>
Cc: Minkyu Kang <mk7.kang@samsung.com>
Cc: Tom Rini <trini@ti.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2014-09-05 13:58:50 +09:00
Przemyslaw Marczak
4fb4d55a35 arch:exynos: boot mode: add get_boot_mode(), code cleanup
This patch introduces code clean-up for exynos boot mode check.
It includes:
- removal of typedef: boot_mode
- move the boot mode enum to arch-exynos/power.h
- add bootmode for sequence: eMMC 4.4 ch4 / SD ch2
- add new function: get_boot_mode() for OM[5:1] pin check
- update spl boot code

Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com>

Changes v5:
- exynos: boot mode: add missing bootmode (1st:EMMC 4.4 / 2nd:SD ch2)

Changes v6:
- none

changes v7:
- change boot mode name: BOOT_MODE_MMC to BOOT_MODE_SD
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2014-09-05 13:58:49 +09:00
Przemyslaw Marczak
19f1b629bf exynos: pinmux: fix the gpio names for exynos4x12 mmc
This change fixes the bad gpio configuration for the exynos dwmmc.

Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com>
Cc: Beomho Seo <beomho.seo@samsung.com>
Cc: Minkyu Kang <mk7.kang@samsung.com>
Cc: Jaehoon Chung <jh80.chung@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2014-09-05 13:58:49 +09:00
Masahiro Yamada
72df68cc6b exynos: kconfig: move board select menu and common settings
Becuase the board select menu in arch/arm/Kconfig is too big,
move the Exynos board select menu to exynos/Kconfig.

Consolidate also common settings (CONFIG_SYS_CPU="armv7" and
CONFIG_SYS_SOC="exynos").

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Acked-by: Minkyu Kang <mk7.kang@samsung.com>
2014-08-30 21:21:59 -04:00
Albert ARIBAUD
304f936aea Merge remote-tracking branch 'u-boot-samsung/master'
Conflicts:
	boards.cfg

Conflict was trivial between goni maintainer change and
lager_nor removal.
2014-07-01 20:52:51 +02:00
Akshay Saraswat
eacf46d340 Exynos5420: Let macros be used for exynos5420
Macros defined in exynos5_setup.h specific to SMDK5420
are required for Peach-Pit too. Hence, replacing
CONFIG_SMDK5420 with CONFIG_EXYNOS5420 to enable these
macros for all the boards based on Exynos5420.

Signed-off-by: Akshay Saraswat <akshay.s@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2014-06-23 08:45:44 +09:00
Akshay Saraswat
ed32522fe0 Exynos5420: DMC: Add software read leveling
Sometimes Read DQ and DQS are not in phase. Since, this
phase shift differs from board to board, we need to
calibrate it at DRAM init phase, that's read DQ calibration.
This patch adds SW Read DQ calibration routine to compensate
this skew.

Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com>
Signed-off-by: Akshay Saraswat <akshay.s@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2014-06-13 17:05:14 +09:00
Doug Anderson
c9334fcda9 DMC: exynos5420: Gate CLKM to when reading PHY_CON13
when CLKM is running.  If we stop CLKM when sampling it the glitches
all go away, so we'll do that as per Samsung suggestion.

We also check the "is it locked" bits of PHY_CON13 and loop until they
show the the value sampled actually represents a locked value.  It
doesn't appear that the glitching and "is it locked" are related, but
it seems wise to wait until the PHY tells us the value is good before
we use it.  In practice we will not loop more than a couple times (and
usually won't loop at all).

Signed-off-by: Doug Anderson <dianders@chromium.org>
Signed-off-by: Akshay Saraswat <akshay.s@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2014-06-13 17:05:13 +09:00
Akshay Saraswat
aacdd79095 Exynos5420: Remove code for enabling read leveling
This patch intends to remove all code which enables hardware read
leveling. All characterization environments may not cope up with
h/w read leveling enabled, so we must disable this.
Also, disabling h/w read leveling improves the MIF LVcc value
(LVcc value is the value at which DDR will fail to work properly).
Improving LVcc means we have enough voltage margin for MIF.
When h/w leveling is enabled, we have almost zero volatge margin.

Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com>
Signed-off-by: Akshay Saraswat <akshay.s@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2014-06-13 17:05:13 +09:00
Akshay Saraswat
cfde7588d8 Exynos5: DMC: Modify the definition of ddr3_mem_ctrl_init
Passing fewer arguments is better and mem_iv_size is never
used. Let's keep only one argument and make it cleaner.

Signed-off-by: Hatim Ali <hatim.rv@samsung.com>
Signed-off-by: Akshay Saraswat <akshay.s@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2014-06-13 17:05:13 +09:00
Minkyu Kang
7922a2d479 Revert "exynos: Enable PSHOLD in SPL"
This reverts commit eb0dd9986c.
2014-06-13 17:00:56 +09:00
Vasili Galka
4b9ca09399 cosmetic: Whitespace fix
Signed-off-by: Vasili Galka <vvv444@gmail.com>
2014-06-11 16:27:05 -04:00
Doug Anderson
567802bbd6 Exynos: Make sure ps_hold gets set in the SPL
Setting ps_hold ought to be one of the first things we do when we
first boot up. If we wait until the main u-boot runs we won't set it
in time and the PMIC may power us back off.

Signed-off-by: Doug Anderson <dianders@chromium.org>
Signed-off-by: Akshay Saraswat <akshay.s@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2014-05-31 14:22:20 +09:00
Simon Glass
eb0dd9986c exynos: Enable PSHOLD in SPL
There is quite a tight deadline in enabling PSHOLD, less than a second.
In some cases (e.g. with USB download), U-Boot takes longer than that
to load, so the board powers off before U-Boot starts.

Add a call in SPL to enable PSHOLD.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Lukasz Majewski <l.majewski@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2014-05-28 10:58:19 +09:00
Jaehoon Chung
39c4975622 ARM: exynos: clock: modify the set_mmc_clk for exynos4
Modified the mmc_set_clock for eynos4.
The goal of this patch is that fsys-div register should be reset.
And retore the div-value, not using the value of lowlevel_init.
(For using SDMMC4, this patch is needs)

Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
Tested-by: Lukasz Majewski <l.majewski@samsung.com>
Acked-by: Lukasz Majewski <l.majewski@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2014-05-16 14:54:26 +09:00
Beomho Seo
00ee81300f arm: exynos: clock: Remove exynos4x12_set_mmc_clk function
exynos4x12_set_mmc_clk function have been removed.
Because, exynos4x12_clock and exynos4_clock return same div_fsys* value.

Signed-off-by: Beomho Seo <beomho.seo@samsung.com>
Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
Tested-by: Piotr Wilczek <p.wilczek@samsung.com>
Cc: Lukasz Majewski <l.majewski@samsung.com>
Cc: Piotr Wilczek <p.wilczek@samsung.com>
Cc: Minkyu Kang <mk7.kang@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2014-05-16 14:54:26 +09:00