The 'sf' command is not supposed to rely on the MTD stack, but both
'sf' and 'nand' commands use helpers located in mtd_uboot.c. Despite
their location, these functions do not depend at all on the MTD
stack.
This file (drivers/mtd/mtd_uboot.c) is only compiled if CONFIG_MTD is
selected, which is inconsistent with the current situation. Solve this
by moving these three functions (which are only used by the above two
commands) out of mtd_uboot.c and put them in a C file only compiled
with cmd/sf.c and cmd/nand.c.
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
[trini: Don't export get_part function now]
Signed-off-by: Tom Rini <trini@konsulko.com>
Add more clarity by changing the Kconfig entry name.
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
[trini: Re-run migration, update a few more cases]
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Boris Brezillon <boris.brezillon@bootlin.com>
This adds a general board file based on MT8518 SoCs from MediaTek.
Apart from the generic parts (cpu) we add some low level init codes
and initialize the early clocks.
This commit is adding the basic boot support for the MT8518 eMMC board.
Signed-off-by: mingming lee <mingming.lee@mediatek.com>
[trini: Migrate env location to defconfig, set ENV_IS_IN_MMC]
Signeed-off-by: Tom Rini <trini@konsulko.com>
Add support for MediaTek MT8518 SoC. This include the file
that will initialize the SoC after boot and its device tree.
Signed-off-by: mingming lee <mingming.lee@mediatek.com>
We don't have full device-tree support in SPL yet - add an appropriate
U_BOOT_DEVICE() to the board file.
Signed-off-by: Bartosz Golaszewski <bgolaszewski@baylibre.com>
The DM family of DaVinci SoCs is no longer supported. Drop the
irrelevant code from the driver.
Signed-off-by: Bartosz Golaszewski <bgolaszewski@baylibre.com>
This commit:
d409c96216
causes build failure with ICACHE enabled. This is due to missing
invalidate_icache_all() stub. Let's add empty invalidate_icache_all() in
the case where ICACHE is not enabled.
Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
A number of board function belong in init.h with the others. Move them.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
Move this function into init.h which seems to be designed for this sort
of thing. Also update the header to declare struct global_data so that it
can be included without global_data.h being needed.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
Move these functions into the command.h header file which is a better fit.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
Move these two functions into the irq_funcs.h header file. Also move
interrupt_handler_t as this is used by the irq_install_handler() function.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
These functions do not use driver model but are fairly widely used in
U-Boot. But it is not clear that they will use driver model anytime soon,
so we don't want to label them as 'legacy'.
Move them to a new irq_func.h header file. Avoid the name 'irq.h' since it
is widely used in U-Boot already.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
These functions are CPU-related and do not use driver model. Move them to
cpu_func.h
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
These functions belong in cpu_func.h. Another option would be cache.h
but that code uses driver model and we have not moved these cache
functions to use driver model. Since they are CPU-related it seems
reasonable to put them here.
Move them over.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
These functions belong in cpu_func.h since they do not use driver model.
Move them over. Don't bother adding comments since these functions should
be deleted.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
This function belongs in time.h so move it over and add a comment.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
This function has a similar name to the common wait_ticks(). It is only
used in one place and seems small enough to drop.
Inline it.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
These functions belong in time.h so move them over and add comments.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
At present this function sits in its own file but it does not really
justify it. There are similar string functions in vsprintf.h, so move it
there. Also add the missing function comment.
Use the vsprintf.h include file explicitly where needed.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
Drop inclusion of crc.h in common.h and use the correct header directly
instead.
With this we can drop the conflicting definition in fw_env.h and rely on
the crc.h header, which is already included.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
These should be moved to driver model, but in the meantime, move them
out of the common header to help reduce its size.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
Although layerscape platforms reuse mxc_get_clock() of i.MX platforms,
eSDHC clock getting do not have to use it. It uses global data
gd->arch.sdhc_clk directly in fsl_esdhc driver. Even there are more
than one eSDHC controllers on SoC, they use same reference clock.
Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
Update the sdmmc2 node for eMMC support on eval board stm32mp157c-ev1.
- update slew-rate for pin configuration
- update "vqmmc-supply"
- remove "st,sig-dir"
- add mandatory "pinctrl-names"
- add "mmc-ddr-3_3v"
This patch solve the eMMC detection issue for command "mmc dev 1".
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Device tree and binding alignment with kernel v5.4-rc4
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
Device tree and binding alignment with kernel v5.3
and converted to SPDX.
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
- fix boot banner on RPi3/4
- add support for one binary on RPi3/4
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Merge tag 'rpi-next-2020.01' of https://github.com/mbgg/u-boot
- add RPi4 upstream compatible to pinctrl
- fix boot banner on RPi3/4
- add support for one binary on RPi3/4
In case the SPL on Gen5 loads U-Boot from NAND, unreset the NAND IP
explicitly in the platform code as the denali-spl driver is not aware
of DM at all.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Dalon Westergreen <dwesterg@gmail.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>
Cc: Ley Foon Tan <ley.foon.tan@intel.com>
Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Cc: Tien Fong Chee <tien.fong.chee@intel.com>
Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
Add new FPGA ID for ArriaV ST/D3 or SX/B3 .
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Dalon Westergreen <dwesterg@gmail.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>
Cc: Ley Foon Tan <ley.foon.tan@intel.com>
Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Cc: Tien Fong Chee <tien.fong.chee@intel.com>
Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
On Gen5, when the FPGA is loaded and there was some prior interaction
between the HPS and the FPGA via bridges (e.g. Linux was running and
using some of the IPs in the FPGA) followed by warm reset, it has been
observed that there might be outstanding unfinished transactions. This
leads to an obscure misbehavior of the bridge.
When the bridge is enabled again in U-Boot and there are outstanding
transactions, a read from within the bridge address range would return
a result of the previous read instead. Example:
=> bridge enable ; md 0xff200000 1
ff200000: 1234abcd
=> bridge enable ; md 0xff200010 1
ff200010: 5678dcba <------- this is in fact a value which is stored in
a memory at 0xff200000
=> bridge enable ; md 0xff200000 1
ff200000: 90effe09 <------- this is in fact a value which is stored in
a memory at 0xff200010
and so it continues. Issuing a write does lock the system up completely.
This patch opens the FPGA bridges in 'bridge enable' command, the tears
them down again, and then opens them again. This allows these outstanding
transactions to complete and makes this misbehavior go away.
However, it is not entirely clear whether this is the correct solution.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Dalon Westergreen <dwesterg@gmail.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>
Cc: Ley Foon Tan <ley.foon.tan@intel.com>
Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Cc: Tien Fong Chee <tien.fong.chee@intel.com>
Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
On Gen5, the 'bridge disable' command write 0x0 to brgmodrst register,
which releases all bridges from reset, instead of putting all bridges
into reset. Fix this by inverting the mask and actually putting the
bridges into reset.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Dalon Westergreen <dwesterg@gmail.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>
Cc: Ley Foon Tan <ley.foon.tan@intel.com>
Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Cc: Tien Fong Chee <tien.fong.chee@intel.com>
Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Provide a defconfig which allows us to boot Raspberrry Pi 4
and Raspberry Pi 3 Model B/B+
Instead of using the embedded DTB as done in RPi3 we use the
devicetree provided by the firmware.
Signed-off-by: Matthias Brugger <mbrugger@suse.com>
For bcm283x based on arm64 we also have to change the mm_region.
Add assign this in mach_cpu_init() so we can create now one binary
for RPi3 and RPi4.
Signed-off-by: Matthias Brugger <mbrugger@suse.com>
As part of the effort to create one binary for several bcm83x SoCs
we read the IO base address from device-tree.
Signed-off-by: Matthias Brugger <mbrugger@suse.com>
We move the per SOC define BCM283x_BASE to a global variable.
This is a first step to provide a single binary for several bcm283x
SoCs.
Signed-off-by: Matthias Brugger <mbrugger@suse.com>
Rename the file bcm283x-uboot.dtsi so that it get
automatically include through the scripts/Makefile.lib
using $(CONFIG_SYS_SOC))-u-boot.dtsi
Without this uarts and pincontroller miss the property dm-pre-reloc
and the first call to bcm283x_mu_serial_ofdata_to_platdata() fails
as the pins are not set correctly.
As a result the U-Boot banner isn't shown on boot.
Before commmit
143256b353 ("fdt: update bcm283x device tree sources to Linux 5.1-rc6 state")
we included bcm283x-uboot.dtsi directly in the device-tree file.
Which got deleted by the metioned commit.
This is a much robuster solution.
Reported-by: Tom Rini <trini@konsulko.com>
Reported-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Tested-by: Tom Rini <trini@konsulko.com> [RPi 3, 32b and 64b modes]
Signed-off-by: Matthias Brugger <mbrugger@suse.com>
In commmit
143256b353 ("fdt: update bcm283x device tree sources to Linux 5.1-rc6 state")
we deleted the label for the node soc from bcm283x.dtsi
As we don't need to add the property dm-pre-reloc to the soc node,
we can delete it from bcm283x-uboot.dtsi
Tested-by: Tom Rini <trini@konsulko.com> [RPi 3, 32b and 64b modes]
Signed-off-by: Matthias Brugger <mbrugger@suse.com>
- Clean vid/pid in Kconfig and add fastboot for rk3399
- add 'u-boot, spl-fifo-mode' for mmc
- Use FIT generator for rk3229 optee and rk3368 ATF
- fan53555: add support for Silergy SYR82X and SYR83X
In GCC 9 support for the Armv5 and Armv5E architectures (which have no
known implementations) has been removed, cf.
https://gcc.gnu.org/gcc-9/changes.html
ARM11 is an armv6 implementation. So change the architecture flag for the
compiler to armv6 for ARM11.
Suggested-by: Fabio Estevam <festevam@gmail.com>
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
As part of loading trustedfirmware, the SPL is required to place portions
of code into the socs sram but the mmc controllers can only do dma
transfers into the regular memory, not sram.
The results of this are not directly visible in u-boot itself, but
manifest as security-relate cpu aborts during boot of for example Linux.
There were a number of attempts to solve this elegantly but so far
discussion is still ongoing, so to make the board at least boot correctly
put both mmc controllers into fifo-mode, which also circumvents the
issue for now.
Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Setup dwc3_device structure for non-dm gadgets, which is used
in rk3399 platforms.
dwc3_device would have basic regbase, dr_mode, high speed
and 16-bit UTMI+ etc.
Cc: Marek Vasut <marex@denx.de>
Tested-by: Levin Du <djw@t-chip.com.cn>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
(Fix to use CONFIG_USB_DWC3_GADGET instead of CONFIG_USB_DWC3)
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Use generator script so that we can use environment for TEE source.
$TEE for tee.bin, and if file not exist, the script can report a warning,
and meke the build success without a error.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
