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54 commits

Author SHA1 Message Date
Fabio Estevam
7e30a3eb76 imx8: Run SPL with caches enabled 
It is safe to run SPL with caches enabled on i.MX8, so
remove such restriction.

Signed-off-by: Fabio Estevam <festevam@gmail.com>
Acked-by: Peng Fan <peng.fan@nxp.com>
Acked-by: Oliver Graute <oliver.graute@kococonnector.com>
Acked-by: Anatolij Gustschin <agust@denx.de>
Tested-by: Igor Opaniuk <igor.opaniuk@toradex.com>
Acked-by: Igor Opaniuk <igor.opaniuk@toradex.com>
 2020-05-01 13:46:22 +02:00
Tom Rini
556fd590db configs: Resync with savedefconfig 
Rsync all defconfig files using moveconfig.py

Signed-off-by: Tom Rini <trini@konsulko.com>
 2020-04-28 16:15:47 -04:00
Tom Rini
052170c6a0 configs: Resync with savedefconfig 
Rsync all defconfig files using moveconfig.py

Signed-off-by: Tom Rini <trini@konsulko.com>
 2020-01-22 13:38:00 -05:00
Peng Fan
439321b264 imx: add i.MX8MP EVK board 
Add basic i.MX8MP EVK board support

U-Boot SPL 2020.01-rc4-00388-gb1bf40c0ae-dirty (Dec 30 2019 - 17:55:33 +0800)
power_pca9450b_init
DDRINFO: start DRAM init
DDRINFO:ddrphy calibration done
DDRINFO: ddrmix config done
Normal Boot
Failed to find clock node. Check device tree
WDT:   Not found!
Trying to boot from BOOTROM
image offset 0x8000, pagesize 0x200, ivt offset 0x0

U-Boot 2020.01-rc4-00388-gb1bf40c0ae-dirty (Dec 30 2019 - 17:55:33 +0800)

CPU:   Freescale i.MX8MP rev1.0 at 1000 MHz
Reset cause: POR
Model: NXP i.MX8MPlus EVK board
DRAM:  6 GiB
MMC:   FSL_SDHC: 1, FSL_SDHC: 2
Loading Environment from MMC... OK
In:    serial
Out:   serial
Err:   serial
Net:   No ethernet found.
Hit any key to stop autoboot:  0
u-boot=> mmc list
FSL_SDHC: 1 (SD)
FSL_SDHC: 2

Signed-off-by: Peng Fan <peng.fan@nxp.com>
 2020-01-08 13:20:09 +01:00