mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-10 15:14:43 +00:00
imx: add i.MX8MP EVK board
Add basic i.MX8MP EVK board support U-Boot SPL 2020.01-rc4-00388-gb1bf40c0ae-dirty (Dec 30 2019 - 17:55:33 +0800) power_pca9450b_init DDRINFO: start DRAM init DDRINFO:ddrphy calibration done DDRINFO: ddrmix config done Normal Boot Failed to find clock node. Check device tree WDT: Not found! Trying to boot from BOOTROM image offset 0x8000, pagesize 0x200, ivt offset 0x0 U-Boot 2020.01-rc4-00388-gb1bf40c0ae-dirty (Dec 30 2019 - 17:55:33 +0800) CPU: Freescale i.MX8MP rev1.0 at 1000 MHz Reset cause: POR Model: NXP i.MX8MPlus EVK board DRAM: 6 GiB MMC: FSL_SDHC: 1, FSL_SDHC: 2 Loading Environment from MMC... OK In: serial Out: serial Err: serial Net: No ethernet found. Hit any key to stop autoboot: 0 u-boot=> mmc list FSL_SDHC: 1 (SD) FSL_SDHC: 2 Signed-off-by: Peng Fan <peng.fan@nxp.com>
This commit is contained in:
Peng Fan
Stefano Babic
parent
234187e2bc
commit
439321b264
12 changed files with 2741 additions and 1 deletions
|
|
@ -702,7 +702,8 @@ dtb-$(CONFIG_ARCH_IMX8) += \
|
|||
dtb-$(CONFIG_ARCH_IMX8M) += \
|
||||
imx8mm-evk.dtb \
|
||||
imx8mn-ddr4-evk.dtb \
|
||||
imx8mq-evk.dtb
|
||||
imx8mq-evk.dtb \
|
||||
imx8mp-evk.dtb
|
||||
|
||||
dtb-$(CONFIG_RCAR_GEN2) += \
|
||||
r8a7790-lager-u-boot.dtb \
|
||||
|
|
|
|||
121
arch/arm/dts/imx8mp-evk-u-boot.dtsi
Normal file
121
arch/arm/dts/imx8mp-evk-u-boot.dtsi
Normal file
|
|
@ -0,0 +1,121 @@
|
|||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* Copyright 2019 NXP
|
||||
*/
|
||||
|
||||
&{/soc@0} {
|
||||
u-boot,dm-pre-reloc;
|
||||
u-boot,dm-spl;
|
||||
};
|
||||
|
||||
&clk {
|
||||
u-boot,dm-spl;
|
||||
u-boot,dm-pre-reloc;
|
||||
};
|
||||
|
||||
&osc_32k {
|
||||
u-boot,dm-spl;
|
||||
u-boot,dm-pre-reloc;
|
||||
};
|
||||
|
||||
&osc_24m {
|
||||
u-boot,dm-spl;
|
||||
u-boot,dm-pre-reloc;
|
||||
};
|
||||
|
||||
&aips1 {
|
||||
u-boot,dm-spl;
|
||||
u-boot,dm-pre-reloc;
|
||||
};
|
||||
|
||||
&aips2 {
|
||||
u-boot,dm-spl;
|
||||
};
|
||||
|
||||
&aips3 {
|
||||
u-boot,dm-spl;
|
||||
};
|
||||
|
||||
&iomuxc {
|
||||
u-boot,dm-spl;
|
||||
};
|
||||
|
||||
®_usdhc2_vmmc {
|
||||
u-boot,dm-spl;
|
||||
};
|
||||
|
||||
&pinctrl_uart2 {
|
||||
u-boot,dm-spl;
|
||||
};
|
||||
|
||||
&pinctrl_usdhc2_gpio {
|
||||
u-boot,dm-spl;
|
||||
};
|
||||
|
||||
&pinctrl_usdhc2 {
|
||||
u-boot,dm-spl;
|
||||
};
|
||||
|
||||
&pinctrl_usdhc3 {
|
||||
u-boot,dm-spl;
|
||||
};
|
||||
|
||||
&gpio1 {
|
||||
u-boot,dm-spl;
|
||||
};
|
||||
|
||||
&gpio2 {
|
||||
u-boot,dm-spl;
|
||||
};
|
||||
|
||||
&gpio3 {
|
||||
u-boot,dm-spl;
|
||||
};
|
||||
|
||||
&gpio4 {
|
||||
u-boot,dm-spl;
|
||||
};
|
||||
|
||||
&gpio5 {
|
||||
u-boot,dm-spl;
|
||||
};
|
||||
|
||||
&uart2 {
|
||||
u-boot,dm-spl;
|
||||
};
|
||||
|
||||
&i2c1 {
|
||||
u-boot,dm-spl;
|
||||
};
|
||||
|
||||
&i2c2 {
|
||||
u-boot,dm-spl;
|
||||
};
|
||||
|
||||
&i2c3 {
|
||||
u-boot,dm-spl;
|
||||
};
|
||||
|
||||
&i2c4 {
|
||||
u-boot,dm-spl;
|
||||
};
|
||||
|
||||
&i2c5 {
|
||||
u-boot,dm-spl;
|
||||
};
|
||||
|
||||
&i2c6 {
|
||||
u-boot,dm-spl;
|
||||
};
|
||||
|
||||
&usdhc1 {
|
||||
u-boot,dm-spl;
|
||||
};
|
||||
|
||||
&usdhc2 {
|
||||
u-boot,dm-spl;
|
||||
};
|
||||
|
||||
&usdhc3 {
|
||||
u-boot,dm-spl;
|
||||
};
|
||||
231
arch/arm/dts/imx8mp-evk.dts
Normal file
231
arch/arm/dts/imx8mp-evk.dts
Normal file
|
|
@ -0,0 +1,231 @@
|
|||
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
/*
|
||||
* Copyright 2019 NXP
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include "imx8mp.dtsi"
|
||||
|
||||
/ {
|
||||
model = "NXP i.MX8MPlus EVK board";
|
||||
compatible = "fsl,imx8mp-evk", "fsl,imx8mp";
|
||||
|
||||
chosen {
|
||||
stdout-path = &uart2;
|
||||
};
|
||||
|
||||
memory@40000000 {
|
||||
device_type = "memory";
|
||||
reg = <0x0 0x40000000 0 0xc0000000>,
|
||||
<0x1 0x00000000 0 0xc0000000>;
|
||||
};
|
||||
|
||||
reg_usdhc2_vmmc: regulator-usdhc2 {
|
||||
compatible = "regulator-fixed";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
|
||||
regulator-name = "VSD_3V3";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
|
||||
enable-active-high;
|
||||
};
|
||||
};
|
||||
|
||||
&fec {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_fec>;
|
||||
phy-mode = "rgmii-id";
|
||||
phy-handle = <ðphy1>;
|
||||
fsl,magic-packet;
|
||||
status = "okay";
|
||||
|
||||
mdio {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
ethphy1: ethernet-phy@1 {
|
||||
compatible = "ethernet-phy-ieee802.3-c22";
|
||||
reg = <1>;
|
||||
eee-broken-1000t;
|
||||
reset-gpios = <&gpio4 2 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&snvs_pwrkey {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart2 {
|
||||
/* console */
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_uart2>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usdhc2 {
|
||||
assigned-clocks = <&clk IMX8MP_CLK_USDHC2>;
|
||||
assigned-clock-rates = <400000000>;
|
||||
pinctrl-names = "default", "state_100mhz", "state_200mhz";
|
||||
pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
|
||||
pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
|
||||
pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
|
||||
cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
|
||||
vmmc-supply = <®_usdhc2_vmmc>;
|
||||
bus-width = <4>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usdhc3 {
|
||||
assigned-clocks = <&clk IMX8MP_CLK_USDHC3>;
|
||||
assigned-clock-rates = <400000000>;
|
||||
pinctrl-names = "default", "state_100mhz", "state_200mhz";
|
||||
pinctrl-0 = <&pinctrl_usdhc3>;
|
||||
pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
|
||||
pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
|
||||
bus-width = <8>;
|
||||
non-removable;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&wdog1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_wdog>;
|
||||
fsl,ext-reset-output;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&iomuxc {
|
||||
pinctrl-names = "default";
|
||||
|
||||
pinctrl_fec: fecgrp {
|
||||
fsl,pins = <
|
||||
MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC 0x3
|
||||
MX8MP_IOMUXC_SAI1_RXD3__ENET1_MDIO 0x3
|
||||
MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0 0x91
|
||||
MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1 0x91
|
||||
MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2 0x91
|
||||
MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3 0x91
|
||||
MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC 0x91
|
||||
MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL 0x91
|
||||
MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0 0x1f
|
||||
MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1 0x1f
|
||||
MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2 0x1f
|
||||
MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3 0x1f
|
||||
MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL 0x1f
|
||||
MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC 0x1f
|
||||
MX8MP_IOMUXC_SAI1_RXD0__GPIO4_IO02 0x19
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_reg_usdhc2_vmmc: regusdhc2vmmc {
|
||||
fsl,pins = <
|
||||
MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x41
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_uart2: uart2grp {
|
||||
fsl,pins = <
|
||||
MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX 0x49
|
||||
MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX 0x49
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc2: usdhc2grp {
|
||||
fsl,pins = <
|
||||
MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x190
|
||||
MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d0
|
||||
MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d0
|
||||
MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d0
|
||||
MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d0
|
||||
MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d0
|
||||
MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc2_100mhz: usdhc2grp-100mhz {
|
||||
fsl,pins = <
|
||||
MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x194
|
||||
MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d4
|
||||
MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4
|
||||
MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4
|
||||
MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4
|
||||
MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4
|
||||
MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc2_200mhz: usdhc2grp-200mhz {
|
||||
fsl,pins = <
|
||||
MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x196
|
||||
MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d6
|
||||
MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d6
|
||||
MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d6
|
||||
MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d6
|
||||
MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d6
|
||||
MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc2_gpio: usdhc2grp-gpio {
|
||||
fsl,pins = <
|
||||
MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12 0x1c4
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc3: usdhc3grp {
|
||||
fsl,pins = <
|
||||
MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x190
|
||||
MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d0
|
||||
MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d0
|
||||
MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d0
|
||||
MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d0
|
||||
MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d0
|
||||
MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d0
|
||||
MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d0
|
||||
MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d0
|
||||
MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d0
|
||||
MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x190
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc3_100mhz: usdhc3grp-100mhz {
|
||||
fsl,pins = <
|
||||
MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x194
|
||||
MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d4
|
||||
MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d4
|
||||
MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d4
|
||||
MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d4
|
||||
MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d4
|
||||
MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d4
|
||||
MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d4
|
||||
MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d4
|
||||
MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d4
|
||||
MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x194
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc3_200mhz: usdhc3grp-200mhz {
|
||||
fsl,pins = <
|
||||
MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x196
|
||||
MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d6
|
||||
MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d6
|
||||
MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d6
|
||||
MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d6
|
||||
MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d6
|
||||
MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d6
|
||||
MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d6
|
||||
MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d6
|
||||
MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d6
|
||||
MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x196
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_wdog: wdoggrp {
|
||||
fsl,pins = <
|
||||
MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0xc6
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
|
@ -44,10 +44,17 @@ config TARGET_IMX8MN_EVK
|
|||
select SUPPORT_SPL
|
||||
select IMX8M_DDR4
|
||||
|
||||
config TARGET_IMX8MP_EVK
|
||||
bool "imx8mp LPDDR4 EVK board"
|
||||
select IMX8MP
|
||||
select SUPPORT_SPL
|
||||
select IMX8M_LPDDR4
|
||||
|
||||
endchoice
|
||||
|
||||
source "board/freescale/imx8mq_evk/Kconfig"
|
||||
source "board/freescale/imx8mm_evk/Kconfig"
|
||||
source "board/freescale/imx8mn_evk/Kconfig"
|
||||
source "board/freescale/imx8mp_evk/Kconfig"
|
||||
|
||||
endif
|
||||
|
|
|
|||
14
board/freescale/imx8mp_evk/Kconfig
Normal file
14
board/freescale/imx8mp_evk/Kconfig
Normal file
|
|
@ -0,0 +1,14 @@
|
|||
if TARGET_IMX8MP_EVK
|
||||
|
||||
config SYS_BOARD
|
||||
default "imx8mp_evk"
|
||||
|
||||
config SYS_VENDOR
|
||||
default "freescale"
|
||||
|
||||
config SYS_CONFIG_NAME
|
||||
default "imx8mp_evk"
|
||||
|
||||
source "board/freescale/common/Kconfig"
|
||||
|
||||
endif
|
||||
6
board/freescale/imx8mp_evk/MAINTAINERS
Normal file
6
board/freescale/imx8mp_evk/MAINTAINERS
Normal file
|
|
@ -0,0 +1,6 @@
|
|||
i.MX8MP EVK BOARD
|
||||
M: Peng Fan <peng.fan@nxp.com>
|
||||
S: Maintained
|
||||
F: board/freescale/imx8mp_evk/
|
||||
F: include/configs/imx8mp_evk.h
|
||||
F: configs/imx8mp_evk_defconfig
|
||||
12
board/freescale/imx8mp_evk/Makefile
Normal file
12
board/freescale/imx8mp_evk/Makefile
Normal file
|
|
@ -0,0 +1,12 @@
|
|||
#
|
||||
# Copyright 2019 NXP
|
||||
#
|
||||
# SPDX-License-Identifier: GPL-2.0+
|
||||
#
|
||||
|
||||
obj-y += imx8mp_evk.o
|
||||
|
||||
ifdef CONFIG_SPL_BUILD
|
||||
obj-y += spl.o
|
||||
obj-$(CONFIG_IMX8M_LPDDR4) += lpddr4_timing.o
|
||||
endif
|
||||
94
board/freescale/imx8mp_evk/imx8mp_evk.c
Normal file
94
board/freescale/imx8mp_evk/imx8mp_evk.c
Normal file
|
|
@ -0,0 +1,94 @@
|
|||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* Copyright 2019 NXP
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <errno.h>
|
||||
#include <asm/mach-imx/iomux-v3.h>
|
||||
#include <asm-generic/gpio.h>
|
||||
#include <asm/arch/imx8mp_pins.h>
|
||||
#include <asm/arch/sys_proto.h>
|
||||
#include <asm/mach-imx/gpio.h>
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
#define UART_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_FSEL1)
|
||||
#define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE)
|
||||
|
||||
static iomux_v3_cfg_t const uart_pads[] = {
|
||||
MX8MP_PAD_UART2_RXD__UART2_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
|
||||
MX8MP_PAD_UART2_TXD__UART2_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
|
||||
};
|
||||
|
||||
static iomux_v3_cfg_t const wdog_pads[] = {
|
||||
MX8MP_PAD_GPIO1_IO02__WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL),
|
||||
};
|
||||
|
||||
int board_early_init_f(void)
|
||||
{
|
||||
struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;
|
||||
|
||||
imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));
|
||||
|
||||
set_wdog_reset(wdog);
|
||||
|
||||
imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int dram_init(void)
|
||||
{
|
||||
/* rom_pointer[1] contains the size of TEE occupies */
|
||||
if (rom_pointer[1])
|
||||
gd->ram_size = PHYS_SDRAM_SIZE - rom_pointer[1];
|
||||
else
|
||||
gd->ram_size = PHYS_SDRAM_SIZE;
|
||||
|
||||
#if CONFIG_NR_DRAM_BANKS > 1
|
||||
gd->ram_size += PHYS_SDRAM_2_SIZE;
|
||||
#endif
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int dram_init_banksize(void)
|
||||
{
|
||||
gd->bd->bi_dram[0].start = PHYS_SDRAM;
|
||||
if (rom_pointer[1])
|
||||
|
||||
gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE - rom_pointer[1];
|
||||
else
|
||||
gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE;
|
||||
|
||||
#if CONFIG_NR_DRAM_BANKS > 1
|
||||
gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
|
||||
gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
|
||||
#endif
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
phys_size_t get_effective_memsize(void)
|
||||
{
|
||||
if (rom_pointer[1])
|
||||
return (PHYS_SDRAM_SIZE - rom_pointer[1]);
|
||||
else
|
||||
return PHYS_SDRAM_SIZE;
|
||||
}
|
||||
|
||||
int board_init(void)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
int board_late_init(void)
|
||||
{
|
||||
#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
|
||||
env_set("board_name", "EVK");
|
||||
env_set("board_rev", "iMX8MP");
|
||||
#endif
|
||||
|
||||
return 0;
|
||||
}
|
||||
1847
board/freescale/imx8mp_evk/lpddr4_timing.c
Normal file
1847
board/freescale/imx8mp_evk/lpddr4_timing.c
Normal file
File diff suppressed because it is too large
Load diff
158
board/freescale/imx8mp_evk/spl.c
Normal file
158
board/freescale/imx8mp_evk/spl.c
Normal file
|
|
@ -0,0 +1,158 @@
|
|||
/*
|
||||
* Copyright 2018-2019 NXP
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <spl.h>
|
||||
#include <asm/io.h>
|
||||
#include <errno.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/mach-imx/iomux-v3.h>
|
||||
#include <asm/arch/imx8mp_pins.h>
|
||||
#include <asm/arch/sys_proto.h>
|
||||
#include <asm/mach-imx/boot_mode.h>
|
||||
#include <power/pmic.h>
|
||||
|
||||
#include <power/pca9450.h>
|
||||
#include <asm/arch/clock.h>
|
||||
#include <asm/mach-imx/gpio.h>
|
||||
#include <asm/mach-imx/mxc_i2c.h>
|
||||
#include <fsl_esdhc.h>
|
||||
#include <mmc.h>
|
||||
#include <asm/arch/ddr.h>
|
||||
|
||||
#include <dm/uclass.h>
|
||||
#include <dm/device.h>
|
||||
#include <dm/uclass-internal.h>
|
||||
#include <dm/device-internal.h>
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
int spl_board_boot_device(enum boot_device boot_dev_spl)
|
||||
{
|
||||
return BOOT_DEVICE_BOOTROM;
|
||||
}
|
||||
|
||||
void spl_dram_init(void)
|
||||
{
|
||||
ddr_init(&dram_timing);
|
||||
}
|
||||
|
||||
void spl_board_init(void)
|
||||
{
|
||||
struct udevice *dev;
|
||||
int ret;
|
||||
|
||||
puts("Normal Boot\n");
|
||||
|
||||
ret = uclass_get_device_by_name(UCLASS_CLK,
|
||||
"clock-controller@30380000",
|
||||
&dev);
|
||||
if (ret < 0)
|
||||
printf("Failed to find clock node. Check device tree\n");
|
||||
}
|
||||
|
||||
#define I2C_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PE)
|
||||
#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
|
||||
struct i2c_pads_info i2c_pad_info1 = {
|
||||
.scl = {
|
||||
.i2c_mode = MX8MP_PAD_I2C1_SCL__I2C1_SCL | PC,
|
||||
.gpio_mode = MX8MP_PAD_I2C1_SCL__GPIO5_IO14 | PC,
|
||||
.gp = IMX_GPIO_NR(5, 14),
|
||||
},
|
||||
.sda = {
|
||||
.i2c_mode = MX8MP_PAD_I2C1_SDA__I2C1_SDA | PC,
|
||||
.gpio_mode = MX8MP_PAD_I2C1_SDA__GPIO5_IO15 | PC,
|
||||
.gp = IMX_GPIO_NR(5, 15),
|
||||
},
|
||||
};
|
||||
|
||||
#ifdef CONFIG_POWER
|
||||
#define I2C_PMIC 0
|
||||
int power_init_board(void)
|
||||
{
|
||||
struct pmic *p;
|
||||
int ret;
|
||||
|
||||
ret = power_pca9450b_init(I2C_PMIC);
|
||||
if (ret)
|
||||
printf("power init failed");
|
||||
p = pmic_get("PCA9450");
|
||||
pmic_probe(p);
|
||||
|
||||
/* BUCKxOUT_DVS0/1 control BUCK123 output */
|
||||
pmic_reg_write(p, PCA9450_BUCK123_DVS, 0x29);
|
||||
|
||||
/*
|
||||
* increase VDD_SOC to typical value 0.95V before first
|
||||
* DRAM access, set DVS1 to 0.85v for suspend.
|
||||
* Enable DVS control through PMIC_STBY_REQ and
|
||||
* set B1_ENMODE=1 (ON by PMIC_ON_REQ=H)
|
||||
*/
|
||||
pmic_reg_write(p, PCA9450_BUCK1OUT_DVS0, 0x1C);
|
||||
pmic_reg_write(p, PCA9450_BUCK1OUT_DVS1, 0x14);
|
||||
pmic_reg_write(p, PCA9450_BUCK1CTRL, 0x59);
|
||||
|
||||
/* set WDOG_B_CFG to cold reset */
|
||||
pmic_reg_write(p, PCA9450_RESET_CTRL, 0xA1);
|
||||
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_SPL_LOAD_FIT
|
||||
int board_fit_config_name_match(const char *name)
|
||||
{
|
||||
/* Just empty function now - can't decide what to choose */
|
||||
debug("%s: %s\n", __func__, name);
|
||||
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
||||
void board_init_f(ulong dummy)
|
||||
{
|
||||
int ret;
|
||||
|
||||
arch_cpu_init();
|
||||
|
||||
init_uart_clk(1);
|
||||
|
||||
board_early_init_f();
|
||||
|
||||
timer_init();
|
||||
|
||||
preloader_console_init();
|
||||
|
||||
/* Clear the BSS. */
|
||||
memset(__bss_start, 0, __bss_end - __bss_start);
|
||||
|
||||
ret = spl_init();
|
||||
if (ret) {
|
||||
debug("spl_init() failed: %d\n", ret);
|
||||
hang();
|
||||
}
|
||||
|
||||
enable_tzc380();
|
||||
|
||||
/* Adjust pmic voltage to 1.0V for 800M */
|
||||
setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
|
||||
|
||||
power_init_board();
|
||||
|
||||
/* DDR initialization */
|
||||
spl_dram_init();
|
||||
|
||||
board_init_r(NULL, 0);
|
||||
}
|
||||
|
||||
int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
|
||||
{
|
||||
puts("resetting ...\n");
|
||||
|
||||
reset_cpu(WDOG1_BASE_ADDR);
|
||||
|
||||
return 0;
|
||||
}
|
||||
84
configs/imx8mp_evk_defconfig
Normal file
84
configs/imx8mp_evk_defconfig
Normal file
|
|
@ -0,0 +1,84 @@
|
|||
CONFIG_ARM=y
|
||||
CONFIG_SPL_SYS_ICACHE_OFF=y
|
||||
CONFIG_SPL_SYS_DCACHE_OFF=y
|
||||
CONFIG_ARCH_IMX8M=y
|
||||
CONFIG_SYS_TEXT_BASE=0x40200000
|
||||
CONFIG_SPL_GPIO_SUPPORT=y
|
||||
CONFIG_SPL_LIBCOMMON_SUPPORT=y
|
||||
CONFIG_SPL_LIBGENERIC_SUPPORT=y
|
||||
CONFIG_SYS_MALLOC_F_LEN=0x10000
|
||||
CONFIG_DM_GPIO=y
|
||||
CONFIG_TARGET_IMX8MP_EVK=y
|
||||
CONFIG_SPL_MMC_SUPPORT=y
|
||||
CONFIG_SPL_SERIAL_SUPPORT=y
|
||||
CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
|
||||
CONFIG_ENV_SIZE=0x1000
|
||||
CONFIG_ENV_OFFSET=0x400000
|
||||
CONFIG_NR_DRAM_BANKS=2
|
||||
CONFIG_SPL=y
|
||||
CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x48000000
|
||||
CONFIG_SPL_TEXT_BASE=0x920000
|
||||
CONFIG_FIT=y
|
||||
CONFIG_FIT_EXTERNAL_OFFSET=0x3000
|
||||
CONFIG_SPL_LOAD_FIT=y
|
||||
CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-imx/mkimage_fit_atf.sh"
|
||||
CONFIG_OF_SYSTEM_SETUP=y
|
||||
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/imx8m/imximage-8mp-lpddr4.cfg"
|
||||
CONFIG_DEFAULT_FDT_FILE="imx8mp-evk.dtb"
|
||||
CONFIG_BOARD_LATE_INIT=y
|
||||
CONFIG_BOARD_EARLY_INIT_F=y
|
||||
CONFIG_SPL_BOARD_INIT=y
|
||||
CONFIG_SPL_BOOTROM_SUPPORT=y
|
||||
CONFIG_SPL_SEPARATE_BSS=y
|
||||
CONFIG_SPL_I2C_SUPPORT=y
|
||||
CONFIG_SPL_POWER_SUPPORT=y
|
||||
CONFIG_SPL_WATCHDOG_SUPPORT=y
|
||||
CONFIG_HUSH_PARSER=y
|
||||
CONFIG_SYS_PROMPT="u-boot=> "
|
||||
# CONFIG_CMD_EXPORTENV is not set
|
||||
# CONFIG_CMD_IMPORTENV is not set
|
||||
# CONFIG_CMD_CRC32 is not set
|
||||
CONFIG_CMD_CLK=y
|
||||
CONFIG_CMD_FUSE=y
|
||||
CONFIG_CMD_GPIO=y
|
||||
CONFIG_CMD_I2C=y
|
||||
CONFIG_CMD_MMC=y
|
||||
CONFIG_CMD_CACHE=y
|
||||
CONFIG_CMD_REGULATOR=y
|
||||
CONFIG_CMD_EXT2=y
|
||||
CONFIG_CMD_EXT4=y
|
||||
CONFIG_CMD_EXT4_WRITE=y
|
||||
CONFIG_CMD_FAT=y
|
||||
CONFIG_OF_CONTROL=y
|
||||
CONFIG_SPL_OF_CONTROL=y
|
||||
CONFIG_DEFAULT_DEVICE_TREE="imx8mp-evk"
|
||||
CONFIG_ENV_IS_IN_MMC=y
|
||||
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
|
||||
CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
|
||||
CONFIG_SPL_DM=y
|
||||
CONFIG_CLK_COMPOSITE_CCF=y
|
||||
CONFIG_CLK_IMX8MP=y
|
||||
CONFIG_MXC_GPIO=y
|
||||
CONFIG_DM_PCA953X=y
|
||||
CONFIG_DM_I2C=y
|
||||
CONFIG_SYS_I2C_MXC=y
|
||||
CONFIG_SYS_I2C_MXC_I2C1=y
|
||||
CONFIG_SYS_I2C_MXC_I2C2=y
|
||||
CONFIG_SYS_I2C_MXC_I2C3=y
|
||||
CONFIG_LED=y
|
||||
CONFIG_LED_GPIO=y
|
||||
CONFIG_DM_MMC=y
|
||||
CONFIG_SUPPORT_EMMC_BOOT=y
|
||||
CONFIG_MMC_IO_VOLTAGE=y
|
||||
CONFIG_FSL_ESDHC_IMX=y
|
||||
CONFIG_PHYLIB=y
|
||||
CONFIG_DM_ETH=y
|
||||
CONFIG_PINCTRL=y
|
||||
CONFIG_SPL_PINCTRL=y
|
||||
CONFIG_PINCTRL_IMX8M=y
|
||||
CONFIG_DM_REGULATOR=y
|
||||
CONFIG_DM_REGULATOR_FIXED=y
|
||||
CONFIG_DM_REGULATOR_GPIO=y
|
||||
CONFIG_MXC_UART=y
|
||||
CONFIG_SYSRESET=y
|
||||
CONFIG_SYSRESET_PSCI=y
|
||||
165
include/configs/imx8mp_evk.h
Normal file
165
include/configs/imx8mp_evk.h
Normal file
|
|
@ -0,0 +1,165 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* Copyright 2019 NXP
|
||||
*/
|
||||
|
||||
#ifndef __IMX8MP_EVK_H
|
||||
#define __IMX8MP_EVK_H
|
||||
|
||||
#include <linux/sizes.h>
|
||||
#include <asm/arch/imx-regs.h>
|
||||
|
||||
#ifdef CONFIG_SECURE_BOOT
|
||||
#define CONFIG_CSF_SIZE 0x2000 /* 8K region */
|
||||
#endif
|
||||
|
||||
#define CONFIG_SPL_MAX_SIZE (152 * 1024)
|
||||
#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
|
||||
#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR
|
||||
#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300
|
||||
#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
|
||||
#define CONFIG_SYS_UBOOT_BASE (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)
|
||||
|
||||
#ifdef CONFIG_SPL_BUILD
|
||||
/*#define CONFIG_ENABLE_DDR_TRAINING_DEBUG*/
|
||||
#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv8/u-boot-spl.lds"
|
||||
#define CONFIG_SPL_STACK 0x990000
|
||||
#define CONFIG_SPL_BSS_START_ADDR 0x0095e000
|
||||
#define CONFIG_SPL_BSS_MAX_SIZE 0x2000 /* 8 KB */
|
||||
#define CONFIG_SYS_SPL_MALLOC_START 0x42200000
|
||||
#define CONFIG_SYS_SPL_MALLOC_SIZE SZ_512K /* 512 KB */
|
||||
#define CONFIG_SYS_ICACHE_OFF
|
||||
#define CONFIG_SYS_DCACHE_OFF
|
||||
|
||||
#define CONFIG_MALLOC_F_ADDR 0x940000
|
||||
|
||||
#define CONFIG_SPL_ABORT_ON_RAW_IMAGE
|
||||
|
||||
#undef CONFIG_DM_MMC
|
||||
#undef CONFIG_DM_PMIC
|
||||
#undef CONFIG_DM_PMIC_PFUZE100
|
||||
|
||||
#define CONFIG_POWER
|
||||
#define CONFIG_POWER_I2C
|
||||
#define CONFIG_POWER_PCA9450
|
||||
|
||||
#undef CONFIG_DM_I2C
|
||||
#define CONFIG_SYS_I2C
|
||||
|
||||
#endif
|
||||
|
||||
/* Initial environment variables */
|
||||
#define CONFIG_EXTRA_ENV_SETTINGS \
|
||||
"script=boot.scr\0" \
|
||||
"image=Image\0" \
|
||||
"console=ttymxc1,115200 earlycon=ec_imx6q,0x30890000,115200\0" \
|
||||
"fdt_addr=0x43000000\0" \
|
||||
"fdt_high=0xffffffffffffffff\0" \
|
||||
"boot_fdt=try\0" \
|
||||
"fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \
|
||||
"initrd_addr=0x43800000\0" \
|
||||
"initrd_high=0xffffffffffffffff\0" \
|
||||
"mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \
|
||||
"mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \
|
||||
"mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \
|
||||
"mmcautodetect=yes\0" \
|
||||
"mmcargs=setenv bootargs ${jh_clk} console=${console} root=${mmcroot}\0 " \
|
||||
"loadbootscript=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
|
||||
"bootscript=echo Running bootscript from mmc ...; " \
|
||||
"source\0" \
|
||||
"loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
|
||||
"loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
|
||||
"mmcboot=echo Booting from mmc ...; " \
|
||||
"run mmcargs; " \
|
||||
"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
|
||||
"if run loadfdt; then " \
|
||||
"booti ${loadaddr} - ${fdt_addr}; " \
|
||||
"else " \
|
||||
"echo WARN: Cannot load the DT; " \
|
||||
"fi; " \
|
||||
"else " \
|
||||
"echo wait for boot; " \
|
||||
"fi;\0" \
|
||||
"netargs=setenv bootargs ${jh_clk} console=${console} " \
|
||||
"root=/dev/nfs " \
|
||||
"ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
|
||||
"netboot=echo Booting from net ...; " \
|
||||
"run netargs; " \
|
||||
"if test ${ip_dyn} = yes; then " \
|
||||
"setenv get_cmd dhcp; " \
|
||||
"else " \
|
||||
"setenv get_cmd tftp; " \
|
||||
"fi; " \
|
||||
"${get_cmd} ${loadaddr} ${image}; " \
|
||||
"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
|
||||
"if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \
|
||||
"booti ${loadaddr} - ${fdt_addr}; " \
|
||||
"else " \
|
||||
"echo WARN: Cannot load the DT; " \
|
||||
"fi; " \
|
||||
"else " \
|
||||
"booti; " \
|
||||
"fi;\0"
|
||||
|
||||
#define CONFIG_BOOTCOMMAND \
|
||||
"mmc dev ${mmcdev}; if mmc rescan; then " \
|
||||
"if run loadbootscript; then " \
|
||||
"run bootscript; " \
|
||||
"else " \
|
||||
"if run loadimage; then " \
|
||||
"run mmcboot; " \
|
||||
"else run netboot; " \
|
||||
"fi; " \
|
||||
"fi; " \
|
||||
"else booti ${loadaddr} - ${fdt_addr}; fi"
|
||||
|
||||
/* Link Definitions */
|
||||
#define CONFIG_LOADADDR 0x40480000
|
||||
|
||||
#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
|
||||
|
||||
#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000
|
||||
#define CONFIG_SYS_INIT_RAM_SIZE 0x80000
|
||||
#define CONFIG_SYS_INIT_SP_OFFSET \
|
||||
(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
|
||||
#define CONFIG_SYS_INIT_SP_ADDR \
|
||||
(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
|
||||
|
||||
#define CONFIG_ENV_OVERWRITE
|
||||
#define CONFIG_SYS_MMC_ENV_DEV 1 /* USDHC2 */
|
||||
#define CONFIG_MMCROOT "/dev/mmcblk1p2" /* USDHC2 */
|
||||
|
||||
/* Size of malloc() pool */
|
||||
#define CONFIG_SYS_MALLOC_LEN SZ_32M
|
||||
|
||||
/* Totally 6GB DDR */
|
||||
#define CONFIG_SYS_SDRAM_BASE 0x40000000
|
||||
#define PHYS_SDRAM 0x40000000
|
||||
#define PHYS_SDRAM_SIZE 0xC0000000 /* 3 GB */
|
||||
#define PHYS_SDRAM_2 0x100000000
|
||||
#define PHYS_SDRAM_2_SIZE 0xC0000000 /* 3 GB */
|
||||
|
||||
#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM
|
||||
#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + \
|
||||
(PHYS_SDRAM_SIZE >> 1))
|
||||
|
||||
#define CONFIG_MXC_UART_BASE UART2_BASE_ADDR
|
||||
|
||||
/* Monitor Command Prompt */
|
||||
#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
|
||||
#define CONFIG_SYS_CBSIZE 2048
|
||||
#define CONFIG_SYS_MAXARGS 64
|
||||
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
|
||||
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
|
||||
sizeof(CONFIG_SYS_PROMPT) + 16)
|
||||
|
||||
#define CONFIG_FSL_USDHC
|
||||
|
||||
#define CONFIG_SYS_FSL_USDHC_NUM 2
|
||||
#define CONFIG_SYS_FSL_ESDHC_ADDR 0
|
||||
|
||||
#define CONFIG_SYS_MMC_IMG_LOAD_PART 1
|
||||
|
||||
#define CONFIG_SYS_I2C_SPEED 100000
|
||||
|
||||
#endif
|
||||
Loading…
Reference in a new issue