T104xrdb has several sleep management signals that are used for deep
sleep. They are enabled by OS to enter deep sleep and should be
disabled by u-boot when cores wake up.
Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
There should be a break for case PHY_INTERFACE_MODE_SGMII, otherwise it
will fall into case PHY_INTERFACE_MODE_RGMII.
Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Add support of 2 stage NAND, SD, SPI boot loader using SPL framework.
here, PBL initialise the internal SRAM and copy SPL(160KB). This further
initialise DDR using SPD and environment and copy u-boot(768 KB) from NAND to DDR.
Finally SPL transer control to u-boot.
Initialise/create followings required for SPL framework
- Add spl.c which defines board_init_f, board_init_r
- update tlb and ddr accordingly
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
T1040RDB and T1042RDB_PI has CPLD. Here CPLD controls board mux/features.
This support of CPLD includes
- files and register defintion
- Commands to swtich alternate bank and default bank
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Update following DDR related settings for T1040RDB, T1042RDB_PI
-Correct number of chip selects to two as t1040 supports
two Chip selects.
-Update board_specific_parameters udimm structure with settings
derived via calibration.
-Update ddr_raw_timing sructure corresponding to DIMM.
-Set ODT to off. Typically on FSL board, ODT is set to 75 ohm,
but on T104xRDB, on setting this , DDR instability is observed.
Board-level debugging is in progress.
Verified the updated settings to be working fine with dual-ranked
Micron, MT18KSF51272AZ-1G6 DIMM at data rate 1600MT/s.
Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com>
Signed-off-by: York Sun <yorksun@freescale.com>
This covers only non-L2 switch ethernet interfaces i.e.
RGMII and SGMII interface for both T1040RDB and T1042RDB_PI
T1040RDB is configured as serdes protocol 0x66 which can
support following interfaces
2 RGMIIS on DTSEC4, DTSEC5
1 SGMII on DTSEC3
T1042RDB_PI is configured as serdes protocol 0x06 which can
support following interfaces
2 RGMIIS on DTSEC4, DTSEC5
Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com>
[York Sun: Minor change in commit message]
Signed-off-by: York Sun <yorksun@freescale.com>
Due to increased size of u-boot, FMAN ucode start address has been shifted
by 256KB causing a overlap with rootfs start address.
Update rootfs start address to reflect correct memory map.
Also fix minor typo in README
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
u-boot binary size for Freescale mpc85xx platforms is 512KB.
This has been reached to upper limit for some of the platforms causig
linker error.
So, Increase the u-boot binary size to 768KB.
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Freescale DDR driver has been used for mpc83xx, mpc85xx, mpc86xx SoCs.
The similar DDR controllers will be used for ARM-based SoCs.
Signed-off-by: York Sun <yorksun@freescale.com>
T1042RDB_PI is Freescale Reference Design Board supporting the T1042
QorIQ Power Architecture™ processor. T1042 is a reduced personality
of T1040 SoC without Integrated 8-port Gigabit. The board is designed
with low power features targeted for Printing Image Market.
T1042RDB_PI is similar to T1040RDB board with few differences like
it has video interface, supports T1042 personality
T1042RDB_PI board Overview
-----------------------
- Four e5500 cores, each with a private 256 KB L2 cache
- 256 KB shared L3 CoreNet platform cache (CPC)
- Interconnect CoreNet platform
- 32-/64-bit DDR3L/DDR4 SDRAM memory controller with ECC and interleaving
support
- Data Path Acceleration Architecture (DPAA) incorporating acceleration
for the following functions:
- Packet parsing, classification, and distribution
- Queue management for scheduling, packet sequencing, and congestion
management
- Cryptography Acceleration
- RegEx Pattern Matching Acceleration
- IEEE Std 1588 support
- Hardware buffer management for buffer allocation and deallocation
- Ethernet interfaces
- Two on-board RGMII 10/100/1G ethernet ports.
- SERDES Connections, 8 lanes supporting:
— PCI
— SATA 2.0
- DDR Controller 32-/64-bit DDR3L/DDR4 SDRAM memory controller with ECC and
Interleaving
-IFC/Local Bus
- NAND flash: 1GB 8-bit NAND flash
- NOR: 128MB 16-bit NOR Flash
- Ethernet
- Two on-board RGMII 10/100/1G ethernet ports.
- PHY #0 remains powered up during deep-sleep
- CPLD
- Clocks
- System and DDR clock (SYSCLK, “DDRCLK”)
- SERDES clocks
- Video
- DIU supports video at up to 1280x1024x32bpp
- HDMI connector
- Power Supplies
- USB
- Supports two USB 2.0 ports with integrated PHYs
- Two type A ports with 5V@1.5A per port.
- SDHC
- SDHC/SDXC connector
- SPI
- On-board 64MB SPI flash
- I2C
- Device connected: EEPROM, thermal monitor, VID controller, RTC
- Other IO
- Two Serial ports
- ProfiBus port
- Four I2C ports
Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com>
