Commit graph

133 commits

Author SHA1 Message Date
Stefan Roese
29905a451b mmc: sdhci: Use timer based timeout detection in sdhci_send_command()
The loop counter based timeout detection does not work on the Armada
38x based board (DB-88F6820-GP). At least with dcache enabled a
timeout is detected. Without dcache enabled, the timeout does not
occur. Increasing the loop counter solves this issue. But a better
solution is to use a timer based timeout detection instead. This
patch now implements this timer based detection.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Pantelis Antoniou <panto@antoniou-consulting.com>
Cc: Luka Perkov <luka.perkov@sartura.hr>
2015-07-10 14:54:00 +02:00
Kevin Liu
5e1c23cd39 mmc: sdhci: add timeout setting for response busy command
Timeout interrupt also work for response busy command(R1b) like
cmd38/cmd6. So need to set it accordingly. Current code only
set timeout for data command.

Signed-off-by: Kevin Liu <kliu5@marvell.com>
Signed-off-by: Rob Herring <robh@kernel.org>
Cc: Pantelis Antoniou <panto@antoniou-consulting.com>
2015-05-05 12:29:42 +03:00
Rob Herring
3c1fcb770b sdhci: fix warnings on 64-bit builds
Change addresses to unsigned long to be compatible with 64-bit builds.
Regardless of fixing warnings, the device is still only 32-bit capable.

Signed-off-by: Rob Herring <robh@kernel.org>
Cc: Pantelis Antoniou <panto@antoniou-consulting.com>
2015-03-18 09:55:59 +02:00
Matt Reimer
e113fe3c06 mmc: sdhci: don't clobber adjacent registers
SDHCI_HOST_CONTROL is a byte-sized register, so don't write to it
as if it were a long, as that would result in clobbering the three
registers following.

Signed-off-by: Matt Reimer <mreimer@sdgsystems.com>
2015-03-18 09:53:01 +02:00
Matt Reimer
f88a429f11 mmc: sdhci: fix bus width switching on Samsung SoCs
Fix bus width switching from 8-bit mode down to 4-bit or 1-bit modes on
Samsung SoCs using SDHCI_QUIRK_USE_WIDE8.  These SoCs report controller
version 2.0 yet they support 8-bit bus widths.  If 8-bit mode was
previously enabled and then an operation like "mmc dev" caused a switch
back down to 4-bit or 1-bit mode, WIDE8 was left set, causing failures.

This problem was manifested by "mmc dev" timing out.

Signed-off-by: Matt Reimer <mreimer@sdgsystems.com>
2015-02-23 19:52:00 +02:00
Jeroen Hofstee
6588c78bf3 sdhci: make local functions static
Signed-off-by: Jeroen Hofstee <jeroen@myspectrum.nl>
2014-10-25 07:02:02 -04:00
Pantelis Antoniou
93bfd61677 mmc: Split mmc struct, rework mmc initialization (v2)
The way that struct mmc was implemented was a bit of a mess;
configuration and internal state all jumbled up in a single structure.

On top of that the way initialization is done with mmc_register leads
to a lot of duplicated code in drivers.

Typically the initialization got something like this in every driver.

	struct mmc *mmc = malloc(sizeof(struct mmc));
	memset(mmc, 0, sizeof(struct mmc);
	/* fill in fields of mmc struct */
	/* store private data pointer */
	mmc_register(mmc);

By using the new mmc_create call one just passes an mmc config struct
and an optional private data pointer like this:

	struct mmc = mmc_create(&cfg, priv);

All in tree drivers have been updated to the new form, and expect
mmc_register to go away before long.

Changes since v1:

* Use calloc instead of manually calling memset.
* Mark mmc_register as deprecated.

Signed-off-by: Pantelis Antoniou <panto@antoniou-consulting.com>
2014-03-24 12:58:56 +02:00
Pantelis Antoniou
22cb7d334e mmc: Convert mmc struct's name array to a pointer
Using an array is pointless; even more pointless (and scary) is using
sprintf to fill it without a format string.

Signed-off-by: Pantelis Antoniou <panto@antoniou-consulting.com>
2014-03-24 11:32:10 +02:00
Pantelis Antoniou
ab769f227f mmc: Remove ops from struct mmc and put in mmc_ops
Remove the in-structure ops and put them in mmc_ops with
a constant pointer to it.

This makes the mmc structure smaller as well as conserving
code space (in theory).

All in-tree drivers are converted as well; this is done in a
single patch in order to not break git bisect.

Changes since V1:
Fix compilation b0rked issue on omap platforms where OMAP_GPIO was
not set.

Signed-off-by: Pantelis Antoniou <panto@antoniou-consulting.com>
2014-03-24 11:32:10 +02:00
Darwin Rambo
30e6d979fa mmc: Minor cleanup of sdhci.c
Fixup prints to show where the print is done from, and
a few minor formatting/grammar issues.

Signed-off-by: Darwin Rambo <drambo@broadcom.com>
Acked-by: Pantelis Antoniou <panto@antoniou-consulting.com>
2014-01-09 11:36:56 +02:00
Przemyslaw Marczak
56b34bc617 mmc: sdhci: Avoid commands errors by simple timeout adaptation.
Old command timeout value was too small and it caused I/O errors which
led to uncompleted read/write/erase operations and filesystem errors.
Timeout adaptation fixes this issue.

Changes in sdhci_send_command() function:
- change timeout variable to static
- increase default command timeout to 100 ms
- add definition of max command timeout value,
  which can be redefined in each board config file
- wait for card ready state for max defined time
  if it doesn't exceed defined maximum or return COMM_ERR

Once successfully increased timeout value will be used in next function
call. This fix was tested on Goni, Trats, Trats2 boards by testing UMS
on MMC storage.

Changes v2:
- move global variable cmd_timeout into function sdhci_send_command()
- change condition "==" to ">=" when comparing time with timeout
- print information about timeout increasing and card busy timeout

Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com>
Cc: Pantelis Antoniou <panto@antoniou-consulting.com>
2013-10-31 09:55:33 +02:00
Juhyun \(Justin\) Oh
2c011847c1 Fix wrong sdhci host control register read and write
The patch fixes the improper read and write of sdhci
host control register for sdma transfer.

The problem comes when reading and writing 1 byte long
host control register with the sdhci_readl() and
sdhci_writel(). The misuse of these functions overwrite
the value of the next registers which are in 4 bytes boundary.

This patch replaces four byte register read/write functions
with one byte read/write ones. Beside, it eliminates
unnecessary bit operation. i.e. or-ing zero against a variable.

Signed-off-by: Juhyun (Justin) Oh <Juhyun_Oh@sigmadesigns.com>
2013-09-20 19:02:29 +03:00
Jaehoon Chung
113e5dfcd7 mmc: sdhci: use the SDHCI_QUIRK_USE_WIDE8 for samsung SoC
Samsung SoC is supported the WIDE8, even if Controller version is v2.0.
So add the SDHCI_QUIRK_USE_WIDE8 for Samsung-SoC.

Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Pantelis Antoniou <panto@antoniou-consulting.com>
2013-09-17 20:03:43 +03:00
Wolfgang Denk
1a4596601f Add GPL-2.0+ SPDX-License-Identifier to source files
Signed-off-by: Wolfgang Denk <wd@denx.de>
[trini: Fixup common/cmd_io.c]
Signed-off-by: Tom Rini <trini@ti.com>
2013-07-24 09:44:38 -04:00
Jagannadha Sutradharudu Teki
1695b29a5d mmc: sdhci: Enable 8-bit bus width only for 3.0 spec onwards
CAP register don't have any information for 8-bit buswidth support
on 2.0 sdhci spec, only from 3.0 onwards bit[18] got this information.

Due to this misassignment in sdhci, mmc is setting 8-bit buswidth using
mmc_set_bus_width even if controller doesn't support.
Below change has code information.
"mmc: Properly determine maximum supported bus width"
(sha1: 7798f6dbd5)

Bug log: <mmc plus and emmc cards)
-------
zynq-uboot> mmcinfo
Error detected in status(0x208100)!
Device: zynq_sdhci
Manufacturer ID: fe
.....

So enable 8-bit support only for 3.0 spec using CAP and for below 3.0
assign mmc->host_caps = MMC_MODE_8BIT on respective platform driver
if host have a support.

Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-06-13 16:44:49 -05:00
Albert ARIBAUD
412665b461 Merge branch 'u-boot-samsung/master' into 'u-boot-arm/master' 2013-03-26 09:51:09 +01:00
Łukasz Majewski
ce0c1bc135 mmc:sdhci:fix: Change default interrupts enabled at SDHCI initialization
This patch changes sdhci_init()'s behavior to NOT enable all interrupt
sources by default. Moreover interrupt signaling has been disabled.

This patch do not enable interrupts which aren't served in u-boot
(they are defined at sdhci.h but NOT used elsewhere):
- SDHCI_INT_CARD_INSERT, SDHCI_INT_CARD_REMOVE, SDHCI_BUS_POWER,
  SDHCI_INT_CARD_REMOVE, SDHCI_INT_CARD_INT

Special care shall be put on SDHCI_INT_CARD_INT, which indicates
interrupt generated by SD card.
According to "SD Host Controller Simplified Spec. ver 3.00" when bit 8
(Card Interrupt Status Enable) at "Normal Interrupt Status Enable
Register" (offset 0x34) is set, the card interrupt detection is started.
Then eMMC card may cause the SD controller to set this bit and then this
interrupt is passed to booted OS and might cause kernel crash.

To sum up:
- Only enable interrupts, which are served at u-boot
- This cleanup as a side effect fixes SDHCI's CARD INTERRUPT problem at
  Linux kernel (versions 3.6+, sdhci controller)
- Keep masked bits at "Normal Interrupt Signal Enable Register" (0x38h)

Signed-off-by: Lukasz Majewski <l.majewski@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Cc: Lei Wen <leiwen@marvell.com>
Cc: Andy Fleming <afleming@freescale.com>
Acked-by: Jaehoon Chung <jh80.chung@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2013-03-12 19:50:49 +09:00
Nikita Kiryanov
d23d8d7e06 mmc: add support for write protection
Add generic mmc write protection functionality.

Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
Signed-off-by: Igor Grinberg <grinberg@compulab.co.il>
2013-03-08 16:41:13 -05:00
Mela Custodio
688c2d140b mmc: add no simultaenous power and vdd
Bring in the code from Linux kernel.

Added to Linux kernel by:
commit e08c1694d9e2138204f2b79b73f0f159074ce2f5
Author: Andres Salomon <dilinger@queued.net>
Date:   Fri Jul 4 10:00:03 2008 -0700

Some HW balks when writing both voltage setting and power up at the same
time to SDHCI_POWER_CONTROL register.

Signed-off-by: Rommel G Custodio <sessyargc@gmail.com>
CC: Andy Fleming <afleming@freescale.com>

v2: fix attribution and SOB
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-11-27 17:26:48 -06:00
Tushar Behera
13243f2eaf mmc: sdhci: Add a quirk to add delay during completion of sdhci_send_cmd
MMC host controller requires a delay between every sdhci_send_cmd()
execution. In s5p_mmc driver (s5p_sdhci replaces this driver), a delay
of 1000us was provided after every mmc_send_cmd() call. Adding a quirk
in current sdhci driver to replicate the behaviour.

Without this delay, MMC initialization on Origen board fails with
following error messages.

Timeout for status update!
mmc fail to send stop cmd

Signed-off-by: Tushar Behera <tushar.behera@linaro.org>
Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-10-22 02:53:36 -05:00
Jaehoon Chung
804c7f4221 mmc: sdhci: add the DMA select for SDMA
In host-control register, DMA select bit field is present.
BUt in sdhci.c, didn't select for DMA.
if set CONFIG_MMC_SDMA, we need to set SDMA-select bit.

Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-10-22 02:53:36 -05:00
Jaehoon Chung
5d48e42247 mmc: sdhci: increase the timeout value for data transfer
Timeout value is tunable.
When run read/write operation, sometime returned the timeout error.
Because the timeout value is too short.
So increased the enough timeout value.
(This timeout value is used to prevent the infinite loop.)

Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-10-22 02:53:36 -05:00
Jaehoon Chung
b09ed6e4fe mmc: s5p_sdhci: add the set_mmc_clk for cmu control
Samsung SoC use the cmu control to set clock.

Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-09-05 17:33:26 -05:00
Joe Hershberger
470dcc7511 mmc: Add a SDHCI quirk for boards that have no CD
Some boards have no Card Detect wired.  In that case, set the CD test
bits in the standard interface.

Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-09-05 17:33:25 -05:00
Joe Hershberger
073cfd1c04 mmc: Fix version check for clock API in sdhci driver
When setting up the clocks in the sdhci driver, the "spec version"
must be masked off.  Otherwise any time the vendor version is not 0,
the check will allways assume the interface is version 3.  This breaks
when the interface is actually version 1 or 2.

Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-09-05 17:33:25 -05:00
Jaehoon Chung
236bfecff8 mmc: add the quirk to use the sdhci for samsung-soc
To support the Samsung-SoC, added the basically functions.
Samsung-SoC didn't used the SDHCI_CTRL_HISPD.
And added set_control_reg callback for s3c64xx.

Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Acked-by: Lei Wen<leiwen@marvell.com>
2012-05-08 18:02:22 -05:00
Jaehoon Chung
3a6383207b mmc: sdhci: add the quirk for broken r1b response
When response type is R1b, mask value is added the SDHCI_INT_DAT_END.
but in while(), didn't check that flag.
So sdhci controller didn't work fine.
CMD6 didn't always complete.

So add the quirks for broken r1b response
and add the timeout value to prevent the infinite loop.

Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Acked-by: Lei Wen<leiwen@marvell.com>
2012-05-08 18:02:22 -05:00
Thierry Reding
48972d907a mmc: Implement card detection.
Check for card detect each time an MMC/SD device is initialized. If card
detection is not implemented, this code behaves as before and continues
assuming a card is present. If no card is detected, has_init is reset
for the MMC/SD device (to force initialization next time) and an error
is returned.

Signed-off-by: Thierry Reding <thierry.reding@avionic-design.de>
Tested-by: Jason Liu <jason.hui@linaro.org>
2012-01-08 21:28:27 -06:00
Lei Wen
3e81c77240 mmc: sdhci: fix sdma bug for large file transfer
SDHCI spec need to reset the sdma base address while the software
try to accorss the 512k bytes address boundary. When meet such
accross behavior, sdhci controller would generate a interrupt
automatically, and software need handle this.

Signed-off-by: Lei Wen <leiwen@marvell.com>
2011-11-03 02:15:00 -05:00
Lei Wen
a004abde88 mmc: sdhci: add timeout for data transfer
Signed-off-by: Lei Wen <leiwen@marvell.com>
2011-11-03 02:14:59 -05:00
Lei Wen
6cf1b17cd0 mmc: sdhci: add mmc structure for host
So that sdhci host would tell in the driver that the mmc current
attributes.

Signed-off-by: Lei Wen <leiwen@marvell.com>
2011-11-03 02:14:59 -05:00
Lei Wen
2c2ec4c969 mmc: sdhci: fix cache flush
Only flush the memory range needed.

Signed-off-by: Lei Wen <leiwen@marvell.com>
2011-11-03 02:14:59 -05:00
Lei Wen
af62a55785 MMC: add sdhci generic framework
Nowdays, there are plenty of mmc driver in uboot adopt the sd standard
host design, aka as sdhci. It is better to centralize the common logic
together to better maintenance.

Signed-off-by: Lei Wen <leiwen@marvell.com>
Acked-by: Andy Fleming <afleming@freescale.com>
2011-07-15 20:29:18 -05:00