Commit graph

113 commits

Author SHA1 Message Date
Tom Rini
b4b9a00ed5 Convert CONFIG_SYS_SPL_ARGS_ADDR to Kconfig
This converts the following to Kconfig:
   CONFIG_SYS_SPL_ARGS_ADDR

In doing so, we also consistently use this variable for SPL_OS_BOOT and
not CONFIG_SYS_FDT_BASE in some cases.

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-06-06 12:09:29 -04:00
Tom Rini
10f6e4dc3a Convert CONFIG_SYS_SPL_MALLOC_SIZE et al to Kconfig
This converts the following to Kconfig:
   CONFIG_SYS_SPL_MALLOC_SIZE
   CONFIG_SYS_SPL_MALLOC_START

We introduce a default value here as well, and CONFIG_SYS_SPL_MALLOC to
control if we have a malloc pool or not.

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-06-06 12:09:28 -04:00
Tom Rini
6600b355c7 Convert CONFIG_SPL_BSS_START_ADDR to Kconfig
This converts the following to Kconfig:
   CONFIG_SPL_BSS_START_ADDR

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-06-06 12:09:28 -04:00
Tom Rini
f113d7d303 Convert CONFIG_SPL_STACK to Kconfig
This converts the following to Kconfig:
   CONFIG_SPL_STACK

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-06-06 12:09:27 -04:00
Tom Rini
9b5f9aeb3b Convert CONFIG_SPL_BSS_MAX_SIZE et al to Kconfig
This converts the following to Kconfig:
   CONFIG_SPL_BSS_MAX_SIZE
   CONFIG_SPL_MAX_FOOTPRINT

Note that the da850evm platforms were violating the "only use one" rule
here, and so now hard-code their BSS limit.

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-06-06 12:09:10 -04:00
Tom Rini
ca8a329a1b Convert CONFIG_SPL_PAD_TO et al to Kconfig
This converts the following to Kconfig:
   CONFIG_SPL_PAD_TO
   CONFIG_SPL_MAX_SIZE
   CONFIG_TPL_PAD_TO
   CONFIG_TPL_MAX_SIZE

Note that we need to make TPL_MAX_SIZE be hex, and so move and convert the
existing places.

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-06-06 12:09:06 -04:00
Tom Rini
4a11e34bc9 Convert CONFIG_SPL_FS_LOAD_PAYLOAD_NAME et al to Kconfig
This converts the following to Kconfig:
   CONFIG_SPL_FS_LOAD_ARGS_NAME
   CONFIG_SPL_FS_LOAD_KERNEL_NAME
   CONFIG_SPL_FS_LOAD_PAYLOAD_NAME

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-06-06 12:09:00 -04:00
Tom Rini
d0ee7f295d Convert CONFIG_SYS_PBSIZE to Kconfig
This converts the following to Kconfig:
   CONFIG_SYS_PBSIZE

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-06-06 12:09:00 -04:00
Tom Rini
cf493582f8 Convert CONFIG_SYS_MAXARGS to Kconfig
This converts the following to Kconfig:
   CONFIG_SYS_MAXARGS

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-06-06 12:08:58 -04:00
Tom Rini
22bfaa1f67 configs: Resync with savedefconfig
Rsync all defconfig files using moveconfig.py

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-04-20 14:48:59 -04:00
Tom Rini
d46e86d25c configs: Resync with savedefconfig
Rsync all defconfig files using moveconfig.py

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-04-08 13:36:51 -04:00
Tom Rini
037ef53cf0 Xilinx changes for v2022.07-rc1 v2
xilinx:
 - Allow booting bigger kernels till 100MB
 
 zynqmp:
 - DT updates (reset IDs)
 - Remove unneeded low level uart initialization from psu_init*
 - Enable PWM features
 - Add support for 1EG device
 
 serial_zynq:
 - Change fifo behavior in DEBUG mode
 
 zynq_sdhci:
 - Fix BASECLK setting calculation
 
 clk_zynqmp:
 - Add support for showing video clock
 
 gpio:
 - Update slg driver to handle DT flags
 
 net:
 - Update ethernet_id code to support also DM_ETH_PHY
 - Add support for DM_ETH_PHY in gem driver
 - Enable dynamic mode for SGMII config in gem driver
 
 pwm:
 - Add driver for cadence PWM
 
 versal:
 - Add support for reserved memory
 
 firmware:
 - Handle PD enabling for SPL
 - Add support for IOUSLCR SGMII configurations
 
 include:
 - Sync phy.h with Linux
 - Update xilinx power domain dt binding headers
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Merge tag 'xilinx-for-v2022.07-rc1-v2' of https://source.denx.de/u-boot/custodians/u-boot-microblaze

Xilinx changes for v2022.07-rc1 v2

xilinx:
- Allow booting bigger kernels till 100MB

zynqmp:
- DT updates (reset IDs)
- Remove unneeded low level uart initialization from psu_init*
- Enable PWM features
- Add support for 1EG device

serial_zynq:
- Change fifo behavior in DEBUG mode

zynq_sdhci:
- Fix BASECLK setting calculation

clk_zynqmp:
- Add support for showing video clock

gpio:
- Update slg driver to handle DT flags

net:
- Update ethernet_id code to support also DM_ETH_PHY
- Add support for DM_ETH_PHY in gem driver
- Enable dynamic mode for SGMII config in gem driver

pwm:
- Add driver for cadence PWM

versal:
- Add support for reserved memory

firmware:
- Handle PD enabling for SPL
- Add support for IOUSLCR SGMII configurations

include:
- Sync phy.h with Linux
- Update xilinx power domain dt binding headers
2022-04-05 11:27:39 -04:00
Tom Rini
0a3689cb86 configs: Resync with savedefconfig
Rsync all defconfig files using moveconfig.py

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-04-01 10:33:18 -04:00
Tom Rini
15b4aed473 Convert CONFIG_CLOCKS to Kconfig
This converts the following to Kconfig:
   CONFIG_CLOCKS

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-04-01 10:28:47 -04:00
Michal Simek
24d973c0c1 arm: zynqmp: Enable PWM command and cadence ttc pwm driver
Enable PWM ttc driver and command in generic image.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Link: https://lore.kernel.org/r/a660c8f2010f4f07534753e0ac44a34b8ff0d3c3.1634303847.git.michal.simek@xilinx.com
2022-03-30 14:50:47 +02:00
Tom Rini
1d5686acfd Convert CONFIG_SYS_FAULT_ECHO_LINK_DOWN to Kconfig
This converts the following to Kconfig:
   CONFIG_SYS_FAULT_ECHO_LINK_DOWN

Cc: Ramon Fried <rfried.dev@gmail.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
2022-03-25 12:01:15 +00:00
Tom Rini
297e6eb8dc Xilinx changes for v2022.07-rc1
microblaze:
 - Add support for reserved memory
 
 xilinx:
 - Update FRU code with MAC reading
 
 zynqmp:
 - Remove double AMS setting
 - DT updates (mostly for SOMs)
 - Add support for zcu106 rev 1.0
 
 zynq:
 - Update nand binding
 
 nand:
 - Aligned zynq_nand to upstream DT binding
 
 net:
 - Add support for ethernet-phy-id
 
 mmc:
 - Workaround CD in zynq_sdhci driver also for ZynqMP
 - Add support for dynamic/run-time SD config for SOMs
 
 gpio:
 - Add driver for slg7xl45106
 
 firmware:
 - Add support for dynamic SD config
 
 power-domain:
 - Update zynqmp driver with the latest firmware
 
 video:
 - Add skeleton driver for DP and DPDMA
 
 i2c:
 - Fix i2c to work with QEMU
 
 pinctrl:
 - Add driver for zynqmp pinctrl driver
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Merge tag 'xilinx-for-v2022.07-rc1' of https://source.denx.de/u-boot/custodians/u-boot-microblaze into next

Xilinx changes for v2022.07-rc1

microblaze:
- Add support for reserved memory

xilinx:
- Update FRU code with MAC reading

zynqmp:
- Remove double AMS setting
- DT updates (mostly for SOMs)
- Add support for zcu106 rev 1.0

zynq:
- Update nand binding

nand:
- Aligned zynq_nand to upstream DT binding

net:
- Add support for ethernet-phy-id

mmc:
- Workaround CD in zynq_sdhci driver also for ZynqMP
- Add support for dynamic/run-time SD config for SOMs

gpio:
- Add driver for slg7xl45106

firmware:
- Add support for dynamic SD config

power-domain:
- Update zynqmp driver with the latest firmware

video:
- Add skeleton driver for DP and DPDMA

i2c:
- Fix i2c to work with QEMU

pinctrl:
- Add driver for zynqmp pinctrl driver
2022-03-16 12:52:02 -04:00
Neal Frager
9fb9ec5e24 arm64: zynqmp: add support for zcu106 rev1.0
This patch adds psu_init for Xilinx ZCU106 rev1.0. Xilinx ZCU106 rev1.0 has
newer x16 DDR4 memories and it is SW compatible with revA.

Signed-off-by: Neal Frager <neal.frager@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Link: https://lore.kernel.org/r/997b3e23457e4d24ce0e197d742382aaec36c2b2.1646230318.git.michal.simek@xilinx.com
2022-03-09 12:39:33 +01:00
Tom Rini
a542e4307d Convert CONFIG_BOOTP_MAY_FAIL et al to Kconfig
This converts the following to Kconfig:
   CONFIG_BOOTP_MAY_FAIL
   CONFIG_BOOTP_VENDOREX
   CONFIG_BOOTP_BOOTFILESIZE
   CONFIG_BOOTP_NISDOMAIN
   CONFIG_BOOTP_TIMEOFFSET

Cc: Ramon Fried <rfried.dev@gmail.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
2022-03-03 16:51:20 -05:00
Tom Rini
24b628a8f8 Xilinx changes for v2022.04-rc3
microblaze:
 - Fix exception handler
 
 zynqmp:
 - Show information about secure images
 - DT changes (som u-boot file removal)
 - Fix zynqmp_pm_cfg_obj_convert.py
 - Fix platform boot
 
 xilinx:
 - Fix bootm_size calculation
 - Remove GPIO_EXTRA_HEADER selection
 
 power:
 - Add zynqmp power management driver
 
 scsi:
 - Add phy support to ceva driver
 
 zynq qspi:
 - Fix unaligned accesses and check baudrate setup
 - Add support for spi memory operations
 
 net:
 - Fix 64bit calculation in axi_emac
 
 video:
 - Add missing gpio dependency for seps driver
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Merge tag 'xilinx-for-v2022.04-rc3' of https://gitlab.denx.de/u-boot/custodians/u-boot-microblaze

Xilinx changes for v2022.04-rc3

microblaze:
- Fix exception handler

zynqmp:
- Show information about secure images
- DT changes (som u-boot file removal)
- Fix zynqmp_pm_cfg_obj_convert.py
- Fix platform boot

xilinx:
- Fix bootm_size calculation
- Remove GPIO_EXTRA_HEADER selection

power:
- Add zynqmp power management driver

scsi:
- Add phy support to ceva driver

zynq qspi:
- Fix unaligned accesses and check baudrate setup
- Add support for spi memory operations

net:
- Fix 64bit calculation in axi_emac

video:
- Add missing gpio dependency for seps driver
2022-02-21 08:32:02 -05:00
Michal Simek
83d2941fe9 arm64: zynqmp: Fix dependencies around ZYNQMP_PSU_INIT_ENABLED
ZYNQMP_PSU_INIT_ENABLED is called only when BOARD_EARLY_INIT_F is defined
that's why cover this dependency in Kconfig.
 board_early_init_f() is only part related to
CONFIG_ZYNQMP_PSU_INIT_ENABLED which is disabled now that's why disable
BOARD_EARLY_INIT_F and also build board_early_init_f() only when
CONFIG_BOARD_EARLY_INIT_F is enabled.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Link: https://lore.kernel.org/r/d89253ec1590cd513dcd4bfbedebae618bd6d605.1645104518.git.michal.simek@xilinx.com
2022-02-21 13:20:19 +01:00
Michal Simek
27703ba06d arm64: zynqmp: Build psu_spl_init for SPL all the time
ZYNQMP_PSU_INIT_ENABLED specifically saying that has connection to full
U-Boot not SPL that's why build psu_spl_init for SPL all the time.

Also disable ZYNQMP_PSU_INIT_ENABLED because it ends up in situation that
psu_init() is called twice which is wrong. By default only SPL should call
it.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Link: https://lore.kernel.org/r/bf1e5d9a163f8853c7d951ad42965114ab0b1f50.1645104518.git.michal.simek@xilinx.com
2022-02-21 13:20:06 +01:00
Michal Simek
f063100593 xilinx: Enable OF_BOARD for zynq and zynqmp boards
The commit 9855034397 ("fdt: Don't call board_fdt_blob_setup() without
OF_BOARD") forced to enable OF_BOARD for platforms which provide DT
externally. Zynq/ZynqMP boards are using this feature for a long time
that's why there is a need to enable it by default.

Also code expects to return error in case of error that's why also fill it.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Link: https://lore.kernel.org/r/9f11bbffe2849f4da7d72712082d579262fe8fd8.1645104518.git.michal.simek@xilinx.com
2022-02-21 13:14:02 +01:00
Tom Rini
cccc4ab86f configs: Resync with savedefconfig
Rsync all defconfig files using moveconfig.py and update
scripts/pylint.base

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-02-09 09:28:58 -05:00
Simon Glass
6edb5dd388 sata: Rearrange Kconfig for SATA
Move the SATA options inside an 'if SATA' part, so they are grouped.

Fix the 'Complient' typo while we are here.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Stefan Roese <sr@denx.de>
2022-02-09 09:16:48 -05:00
Alper Nebi Yasak
a8c281d4b7 Convert CONFIG_REMAKE_ELF to Kconfig
This converts the following to Kconfig:
   CONFIG_REMAKE_ELF

Signed-off-by: Alper Nebi Yasak <alpernebiyasak@gmail.com>
2022-02-09 09:16:47 -05:00
Tom Rini
54c5c2b8fe configs: Resync with savedefconfig
Rsync all defconfig files using moveconfig.py

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-01-24 17:36:30 -05:00
Tom Rini
ed35de6170 Convert CONFIG_ZYNQMP_PSU_INIT_ENABLED to Kconfig
This converts the following to Kconfig:
   CONFIG_ZYNQMP_PSU_INIT_ENABLED

Signed-off-by: Tom Rini <trini@konsulko.com>
2021-12-27 16:20:18 -05:00
Tom Rini
5fd4a7ed0c Clarify CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW in Kconfig
This is a "hex" prompt but the default value was given as an int.
Switch the default to hex (0x0) and remove the defconfigs that were
using the default, but as hex before.

Signed-off-by: Tom Rini <trini@konsulko.com>
2021-12-27 08:40:33 -05:00
Tom Rini
2ffa0e87df Xilinx changes for v2022.01-rc3
sdhci:
 - Fix emmc mini case with missing firmware interface
 
 zynqmp:
 - Restore JTAG interface if required
 - Allow overriding board name
 - Add support for DLC21
 - Fix one fallthrought statement description
 - Use config macro instead of name duplication
 - Save multiboot to variable
 
 firmware:
 - Handle ipi_req errors better
 - Use local buffer in case user doesn't need it instead of NULL/0 location
 
 spi:
 - gqsi: Fix write issue at low frequencies
 
 net:
 - gem: Disable broadcasts
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Merge tag 'xilinx-for-v2022.01-rc3' of https://source.denx.de/u-boot/custodians/u-boot-microblaze

Xilinx changes for v2022.01-rc3

sdhci:
- Fix emmc mini case with missing firmware interface

zynqmp:
- Restore JTAG interface if required
- Allow overriding board name
- Add support for DLC21
- Fix one fallthrought statement description
- Use config macro instead of name duplication
- Save multiboot to variable

firmware:
- Handle ipi_req errors better
- Use local buffer in case user doesn't need it instead of NULL/0 location

spi:
- gqsi: Fix write issue at low frequencies

net:
- gem: Disable broadcasts
2021-11-16 09:51:04 -05:00
Tom Rini
9802154a94 configs: Resync with savedefconfig
Rsync all defconfig files using moveconfig.py

Signed-off-by: Tom Rini <trini@konsulko.com>
2021-11-01 12:19:22 +00:00
Michal Simek
d2d14383ba arm64: zynqmp: Add support for DLC21 (Smartlynq+) board
DLC21 is used as fast jtag cable. The patch adds support for this board
from PS perspective. The most interesting part on the board is seps525 oled
display. Also i2c, gpio, ethernet, uart, SD and eMMC are tested.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Link: https://lore.kernel.org/r/3d35cd6a11cffc7456e21a88b214cc965734e852.1634231268.git.michal.simek@xilinx.com
2021-10-21 08:51:33 +02:00
Tom Rini
cdcbd593ad configs: Resync with savedefconfig
Resync all defconfig files using moveconfig.py

Signed-off-by: Tom Rini <trini@konsulko.com>
2021-10-15 09:42:22 -04:00
Tom Rini
c0ad62c5f7 Convert CONFIG_SYS_NAND_ONFI_DETECTION to Kconfig
This converts the following to Kconfig:
   CONFIG_SYS_NAND_ONFI_DETECTION

Signed-off-by: Tom Rini <trini@konsulko.com>
2021-10-06 09:16:23 -04:00
Tom Rini
ec929484ec configs: Resync with savedefconfig
Rsync all defconfig files using moveconfig.py

Signed-off-by: Tom Rini <trini@konsulko.com>
2021-09-04 15:47:53 -04:00
Simon Glass
ea2ca7e17e spi: Rename SPI_SUPPORT to SPI
Rename these options so that CONFIG_IS_ENABLED can be used with them.

Signed-off-by: Simon Glass <sjg@chromium.org>
2021-09-04 12:26:02 -04:00
Tom Rini
7cfbba36e9 Convert CONFIG_SYS_MALLOC_LEN to Kconfig
This converts the following to Kconfig:
   CONFIG_SYS_MALLOC_LEN

Signed-off-by: Tom Rini <trini@konsulko.com>
Acked-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Rick Chen <rick@andestech.com>
2021-08-31 17:47:49 -04:00
Tom Rini
49c8ef0e45 Convert CONFIG_SYS_LOAD_ADDR to Kconfig
Now that we have consistent usage, migrate this symbol to Kconfig.

Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Rick Chen <rick@andestech.com>
2021-08-31 17:46:37 -04:00
Tom Rini
88cd7d0ea9 Convert CONFIG_SYS_I2C_EEPROM_ADDR et al to Kconfig
- Rename usages of CONFIG_SYS_DEF_EEPROM_ADDR to CONFIG_SYS_I2C_EEPROM_ADDR
  based on current usage.
- Convert CONFIG_SYS_I2C_EEPROM_ADDR, CONFIG_SYS_I2C_EEPROM_ADDR_LEN,
  CONFIG_SYS_I2C_EEPROM_BUS, CONFIG_CONFIG_SYS_EEPROM_SIZE
  CONFIG_SYS_EEPROM_PAGE_WRITE_BITS and CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS
  to Kconfig.  We move these symbols around a bit and add appropriate
  dependencies to them.  In some cases, we now add a correct default value
  as well.

Signed-off-by: Tom Rini <trini@konsulko.com>
2021-08-30 14:10:06 -04:00
Tom Rini
18f528535d configs: Resync with savedefconfig
Rsync all defconfig files using moveconfig.py

Signed-off-by: Tom Rini <trini@konsulko.com>
2021-08-30 12:40:24 -04:00
Tom Rini
b9cb74a5aa Xilinx changes for v2021.10-rc3
xilinx:
 - Disable CONFIG_ARCH_FIXUP_FDT_MEMORY
 - Print information about cpu via soc drivers and enable DISPLAY_CPUINFO
 - Wire infrastructure for DTB_RESELECT and MULTI_DTB_FIT
 
 zynq:
 - Wire single QSPI
 - Use power-source instead of io-standard properties
 - Enable nor on zc770-xm012
 
 zynqmp:
 - Change handling around multi_boot()
 - Setup offset for u-boot.itb in spi
 - Generate run time dfu_alt_info for capsule update
 - Use explicit values for enums (zynqmp_firmware.h)
 - Enable RTC/SHA1/BUTTON/BUTTON_GPIO command
 - Disable WDT driver by default
 - Bind usb/scsi via preboot because of EFI
 - DT updates/fixes
 - Add soc driver
 - Fix SPL SPI boot mode
 
 versal:
 - Add soc driver
 
 sdhci:
 - Update tap delay programming for zynq_sdhci driver
 
 cmd:
 - Fix RTC uclass handling in date command
 - Update pwm help message
 - Update reset help message
 
 watchdog:
 - Fix wwdt compilation
 
 rtc:
 - Deal with seq alias in rtc uclass
 - Add zynqmp RTC driver
 
 fdt:
 - Add kernel-doc for fdt_fixup_memory_banks()
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Merge tag 'xilinx-for-v2021.10-rc3' of https://gitlab.denx.de/u-boot/custodians/u-boot-microblaze

Xilinx changes for v2021.10-rc3

xilinx:
- Disable CONFIG_ARCH_FIXUP_FDT_MEMORY
- Print information about cpu via soc drivers and enable DISPLAY_CPUINFO
- Wire infrastructure for DTB_RESELECT and MULTI_DTB_FIT

zynq:
- Wire single QSPI
- Use power-source instead of io-standard properties
- Enable nor on zc770-xm012

zynqmp:
- Change handling around multi_boot()
- Setup offset for u-boot.itb in spi
- Generate run time dfu_alt_info for capsule update
- Use explicit values for enums (zynqmp_firmware.h)
- Enable RTC/SHA1/BUTTON/BUTTON_GPIO command
- Disable WDT driver by default
- Bind usb/scsi via preboot because of EFI
- DT updates/fixes
- Add soc driver
- Fix SPL SPI boot mode

versal:
- Add soc driver

sdhci:
- Update tap delay programming for zynq_sdhci driver

cmd:
- Fix RTC uclass handling in date command
- Update pwm help message
- Update reset help message

watchdog:
- Fix wwdt compilation

rtc:
- Deal with seq alias in rtc uclass
- Add zynqmp RTC driver

fdt:
- Add kernel-doc for fdt_fixup_memory_banks()
2021-08-27 08:33:02 -04:00
Michal Simek
229cb5c6ba xilinx: zynqmp: Enable stack relocation to DDR
There is no space in OCM for SPL stack because the space in OCM is occupied
by TF-A. That's why move relocate stack to DDR to 0x18000000 address
and also enable SPL_SIZE_LIMIT not to be more then 0xfffea000 which is
default address for TFA.

It is good to summarize current DDR usage in SPL flow.
0-0x80000 is used for BSS
 (CONFIG_SPL_BSS_START_ADDR, CONFIG_SPL_BSS_MAX_SIZE)
0x100000 is used for DTB passing address
 (CONFIG_XILINX_OF_BOARD_DTB_ADDR)
0x17fffe70 - CONFIG_SPL_STACK_R_ADDR - is used for GD
0x18000000 is used for SPL stack
 (CONFIG_SPL_STACK_R_ADDR)
0x20000000-0x21000000 is used for SPL malloc area
 (CONFIG_SYS_SPL_MALLOC_START, CONFIG_SYS_SPL_MALLOC_SIZE)

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2021-08-26 08:14:43 +02:00
Michal Simek
edd530651a xilinx: zynqmp: Enable gpio-key/button driver
Enable button uclass and also gpio-key driver by default.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2021-08-26 08:12:56 +02:00
Michal Simek
57bcae88fe arm64: zynqmp: Enable sha1sum command
Enable it for TPM usage.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2021-08-26 08:08:11 +02:00
T Karthik Reddy
57b2a43607 xilinx: Enable config to display cpuinfo
Enable CONFIG_DISPLAY_CPUINFO to display SoC family & revision.

Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com>
Reviewed-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2021-08-26 08:08:11 +02:00
T Karthik Reddy
a890a53ad2 soc: xilinx: zynqmp: Add soc_xilinx_zynqmp driver
soc_xilinx_zynqmp driver allows identification of family & revision
of zynqmp SoC. This driver is selected by CONFIG_SOC_XILINX_ZYNQMP.
Add this config to xilinx_zynqmp_virt_defconfig file.
Probe this driver using platdata U_BOOT_DEVICE structure which is
specified in mach-zynqmp/cpu.c.

Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com>
Reviewed-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2021-08-26 08:08:11 +02:00
Michal Simek
1031a11d71 xilinx: Disable ARCH_FIXUP_FDT_MEMORY
Based on DT spec you can have one memory node which multiple ranges or
multiple nodes.
fdt_fixup_memory_banks() is not implemented in a correct way when multiple
memory nodes are present because all ranges are put it to the first memory
node found. And next memory nodes are kept in DT which ends up in the same
range specification in the same DT.

Here is what it is happening.
Origin DT.
memory@0 {
        device_type = "memory";
        reg = <0x0 0x0 0x0 0x80000000>;
};

memory@800000000 {
        device_type = "memory";
        reg = <0x8 0x00000000 0x0 0x80000000>;
};

After fdt_fixup_memory_banks()

memory@0 {
        device_type = "memory";
        reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>;
};

memory@800000000 {
        device_type = "memory";
        reg = <0x8 0x00000000 0x0 0x80000000>;
};

As is visible memory@0 node got second range but there is still
memory@800000000 node present and 2G range is listed twice.

The solution can't be that second node is removed because it can be
referenced already that's why it is better for us to disable this option
for now.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2021-08-26 08:08:11 +02:00
Michal Simek
18bfe9cf5a xilinx: zynqmp: Initialize usb and scsi via preboot
Based on thread
https://lists.denx.de/pipermail/u-boot/2021-June/451828.html
especially
"Overall we have a deficiency in the UEFI implementation in that we
cannot deal with block devices added or removed after initialization."
there is a need to deal with removable media as usb/scsi/sata.

That's why bridge this gap in EFI implementation by resetting usb and
scsi resets to get all disks before efi_init_obj_list() is called.

In our standard boot flow, where we use distro boot, order is fixed as
"jtag mmc0 mmc1 qspi0 nand0 usb0 usb1 scsi0 pxe dhcp" with prioritizing
boot device added by commit 2882b39d56 ("arm64: zynqmp: Setup the first
boot_target at run time").
When device has ESP partition all devices should be detected because then
efi_disk_register() in efi_init_obj_list() is called only once.

The first such a device is sd/emmc(mmc0/mmc1) and then disks on usb/sata
are not handled at all.

The commit 6bb577dbb3 ("arm64: zynqmp: Disable
EFI_CAPSULE_ON_DISK_EARLY") also pointed out on this issue but detection of
removable media wasn't solved that's why do it now via preboot command.

I have tested cases without usb and scsi and there is no problem with
calling resets without devices itself.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2021-08-26 08:08:11 +02:00
Michal Simek
055dfdc257 arm64: zynqmp: Disable WDT_CDNS driver by default
Do not enable watchdog driver in default zynqmp configuration. The reason
is that not all distributions are handling watchdog properly and then
expires and system resets. If someone needs watchdog in their design please
enable it by hand.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2021-08-26 08:08:11 +02:00
Tom Rini
3e5b62f788 configs: Resync with savedefconfig
Rsync all defconfig files using moveconfig.py

Signed-off-by: Tom Rini <trini@konsulko.com>
2021-08-10 15:08:46 -04:00