Commit graph

100 commits

Author SHA1 Message Date
Simon Glass
3e57ad907c irq: Tidy up of-platdata irq support
This function is available but not exported. More generally it does not
really work as intended.

Reimplement it and add a sandbox test too.

Signed-off-by: Simon Glass <sjg@chromium.org>
2021-09-25 09:46:15 -06:00
Ye Li
0c00d03aca driver: misc: Add MU and S400 API to communicate with Sentinel
Add MU driver and S400 API. Need enable MISC driver to work

Signed-off-by: Ye Li <ye.li@nxp.com>
2021-08-09 14:46:50 +02:00
Asherah Connor
5830b57bf9 qemu: add MMIO driver for QFW
Add MMIO driver for QFW.

Note that there is no consumer as of this patch.

Signed-off-by: Asherah Connor <ashe@kivikakk.ee>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2021-04-12 17:45:40 -04:00
Asherah Connor
69512551aa test: qemu: add qfw sandbox driver, dm tests, qemu tests
A sandbox driver and test are added for the qfw uclass, and a test in
QEMU added for qfw functionality to confirm it doesn't break in real
world use.

Signed-off-by: Asherah Connor <ashe@kivikakk.ee>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2021-04-12 17:45:39 -04:00
Asherah Connor
5b0b43e0e2 x86: qemu: move QFW to its own uclass
We move qfw into its own uclass and split the PIO functions into a
specific driver for that uclass.  The PIO driver is selected in the
qemu-x86 board config (this covers x86 and x86_64).

include/qfw.h is cleaned up and documentation added.

Signed-off-by: Asherah Connor <ashe@kivikakk.ee>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
2021-04-12 17:44:55 -04:00
Igor Opaniuk
d1f3abe1e7 dm: i2c: allow disabling driver model in SPL
At present if U-Boot proper uses driver model for I2C, then SPL has to
also. While this is desirable, it places a significant barrier to moving
to driver model in some cases. For example, with a space-constrained SPL
it may be necessary to enable CONFIG_SPL_OF_PLATDATA which involves
adjusting some drivers.

This patch introduces a separate Kconfig symbols for enabling DM_I2C and
DM_I2C_GPIO support in SPL.

This will also help to get away from dirty workarounds to
achieve non-DM I2C support for SPL, which is currently used in some
board header files like:

ifdef CONFIG_SPL_BUILD
undef CONFIG_DM_I2C
endif

Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Heiko Schocher <hs@denx.de>
Signed-off-by: Igor Opaniuk <igor.opaniuk@foundries.io>
Reviewed-by: Tom Rini <trini@konsulko.com>
2021-02-21 06:07:30 +01:00
Simon Glass
079ac59586 test: Move some test drivers into their own file
At present several test drivers are part of the test file itself. Some of
these are useful for of-platdata tests. Separate them out so we can use
them for other things also.

A few adjustments are needed so this driver can build for sandbox_spl as
well.

Signed-off-by: Simon Glass <sjg@chromium.org>
2021-01-05 12:24:40 -07:00
Pragnesh Patel
05307213c6 misc: add driver for the SiFive otp controller
Added a misc driver to handle OTP memory in SiFive SoCs.

Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
2020-06-04 09:44:08 +08:00
Tero Kristo
3b36b38f50 misc: pmic_esm: Add support for PMIC ESM driver
The ESM (Error Signal Monitor) is used on certain PMIC versions to
handle error signals propagating from rest of the system. If these
reach the PMIC, it is typically a last resort fatal error which
requires a system reset. The ESM driver does the proper configuration
for the ESM module to reach this end goal. Initially, only TPS65941
PMIC is supported for this.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
2020-03-03 13:08:14 +05:30
Tero Kristo
344eb6d572 misc: k3_esm: Add support for Texas Instruments K3 ESM driver
The ESM (Error Signaling Module) is used to route error signals within
the K3 SoCs somewhat similar to interrupts. The handling for these is
different though, and can be routed for hardware error handling, to
be handled by safety processor or just as error interrupts handled
by the main processor. The u-boot level ESM driver is just used to
configure the ESM signals so that they get routed to proper destination.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
2020-03-03 13:08:14 +05:30
Simon Glass
015e3348fc common: Drop floppy disk support
This seems pretty old now. It has not been converted to driver model and
is not used by any boards.

Drop it.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-01-17 13:26:50 -05:00
Simon Glass
fbb0efdd27 sandbox: Add a test for IRQ
Add a simple sandbox test for this uclass.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-12-15 11:44:12 +08:00
Simon Glass
79d66a6ac1 x86: Move UCLASS_IRQ into a separate file
Update this uclass to support the needs of the Apollo Lake ITSS. It
supports four operations.

Move the uclass into a separate directory so that sandbox can use it too.
Add a new Kconfig to control it and enable this on x86.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-12-15 11:44:12 +08:00
Simon Glass
3e17ffbb44 sandbox: Add PCI driver and test for p2sb
Add a sandbox driver and PCI-device emulator for p2sb. Also add a test
which uses a simple 'adder' driver to test the p2sb functionality.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-12-15 11:44:11 +08:00
Simon Glass
5bee27aa41 pci: Add support for p2sb uclass
The Primary-to-Sideband bus (P2SB) is used to access various peripherals
through memory-mapped I/O in a large chunk of PCI space. The space is
segmented into different channels and peripherals are accessed by
device-specific means within those channels. Devices should be added in
the device tree as subnodes of the p2sb.

This adds a uclass and enables it for sandbox.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-12-15 11:44:11 +08:00
Finley Xiao
a907dc3f25 misc: add driver for the Rockchip otp controller
Newer Rockchip socs like the px30 use a different ip block to handle
one-time-programmable memory, so add a misc driver for it as well.

Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2019-11-17 17:23:15 +08:00
Tero Kristo
9d233b4e3e misc: k3_avs: add driver for K3 Adaptive Voltage Scaling Class 0
Adaptive Voltage Scaling is a technology used in TI SoCs to optimize
the operating voltage based on characterization data written to efuse
during production. Add a driver to support this feature for K3 line of
SoCs, initially for AM65x.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Keerthy <j-keerthy@ti.com>
2019-11-07 18:39:16 -05:00
Eugen Hristev
f81649586d misc: microchip_flexcom: introduce microchip_flexcom driver
The Microchip Flexcom is just a wrapper which embeds a SPI controller,
an I2C controller and an USART.
Only one function can be used at a time and is chosen at boot time according
to the device tree.
The bindings are kept as in Linux.
The driver registers to MISC_UCLASS.

Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
2019-10-24 13:01:57 +03:00
Simon Glass
75d8f49481 sandbox: pci: Create a new sandbox_pci_read_bar() function
The code in swapcase can be used by other sandbox drivers. Move it into a
common place to allow this.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
[bmeng: remove inclusion of <asm/test.h> in pci_sandbox.c]
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2019-10-08 13:57:48 +08:00
Simon Glass
aaba703fd0 spl: misc: Allow misc drivers in SPL and TPL
In some cases it is necessary to read the keyboard in early phases of
U-Boot. The cros_ec keyboard is kept in the misc directory. Update the
config to allow this.

Signed-off-by: Simon Glass <sjg@chromium.org>
2019-05-21 17:33:23 -06:00
Paul Burton
b5392c50bd misc: Add JZ47xx efuse driver
Add driver for the efuse block in the JZ47xx SOC.

Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
Signed-off-by: Ezequiel Garcia <ezequiel@collabora.com>
Reviewed-by: Marek Vasut <marex@denx.de>
2018-12-19 15:23:01 +01:00
Mario Six
ab88bd2b6a misc: Add IHS FPGA driver
Add a driver for gdsys IHS (Integrated Hardware Systems) FPGAs, which
supports initialization of the FPGA, as well as information gathering.

Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Mario Six <mario.six@gdsys.cc>
2018-11-14 09:16:27 -08:00
Mario Six
c0a2b086b2 misc: Add gdsys_soc driver
This patch adds a driver for the bus associated with a IHS FPGA.

Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Mario Six <mario.six@gdsys.cc>
2018-11-14 09:16:27 -08:00
Mario Six
313d4cc3e9 misc: Sort Makefile entries
Makefile entries should be sorted.

Reviewed-by: Anatolij Gustschin <agust@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Mario Six <mario.six@gdsys.cc>
Signed-off-by: Anatolij Gustschin <agust@denx.de>
2018-11-14 09:16:27 -08:00
Peng Fan
ef64e782ec misc: add i.MX8 misc driver
Add i.MX8 MISC driver to handle the communication between
A35 Core and SCU.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Anatolij Gustschin <agust@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
2018-10-22 12:59:01 +02:00
Liviu Dudau
0fabfeb2c7 misc: Add support for the Arm Versatile Express config bus
Add support for the Arm Versatile Express config bus that is
being used for exposing various subsystems via a generic
configuration bus. This driver adds support for generating
transactions on this configuration bus and can be used by
other drivers to abstract the communication with the actual
function providers.

Signed-off-by: Liviu Dudau <liviu.dudau@foss.arm.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
2018-10-06 09:04:18 -04:00
Tien Fong Chee
620300043c common: Generic loader for file system
This is file system generic loader which can be used to load
the file image from the storage into target such as memory.
The consumer driver would then use this loader to program whatever,
ie. the FPGA device.

Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
2018-09-28 20:22:33 -04:00
Mario Six
d2166319df misc: Add MPC83xx serdes driver
Add a driver to configure the SerDes (Serializer/Deserializer) lanes on
the MPC83xx architecture.

Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Mario Six <mario.six@gdsys.cc>
2018-09-18 08:12:21 -06:00
Mario Six
7e86242b2b misc: Add gdsys_ioep driver
Add driver for the IHS IO endpoint on IHS FPGAs.

Signed-off-by: Mario Six <mario.six@gdsys.cc>
2018-08-11 16:00:50 +02:00
Mario Six
004e67c216 test: Add tests for misc uclass
Add a set of tests for the misc uclass.

Signed-off-by: Mario Six <mario.six@gdsys.cc>
Reviewed-by: Simon Glass <sjg@chromium.org>
2018-08-11 16:00:38 +02:00
Patrick Delaunay
c3600e1f92 stm32mp1: add FUSE command support
Add support of fuse command (read/write/program/sense)
on bank 0 to access to BSEC SAFMEM (4096 OTP bits).

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
2018-05-26 18:19:18 -04:00
Mario Six
86da8c12ef gdsys: drivers: Add gdsys_rxaui_ctrl driver
Add a driver for RXAUI control on IHS FPGAs.

Signed-off-by: Mario Six <mario.six@gdsys.cc>
Reviewed-by: Simon Glass <sjg@chromium.org>
2018-05-08 18:50:23 -04:00
Tom Rini
83d290c56f SPDX: Convert all of our single license tags to Linux Kernel style
When U-Boot started using SPDX tags we were among the early adopters and
there weren't a lot of other examples to borrow from.  So we picked the
area of the file that usually had a full license text and replaced it
with an appropriate SPDX-License-Identifier: entry.  Since then, the
Linux Kernel has adopted SPDX tags and they place it as the very first
line in a file (except where shebangs are used, then it's second line)
and with slightly different comment styles than us.

In part due to community overlap, in part due to better tag visibility
and in part for other minor reasons, switch over to that style.

This commit changes all instances where we have a single declared
license in the tag as both the before and after are identical in tag
contents.  There's also a few places where I found we did not have a tag
and have introduced one.

Signed-off-by: Tom Rini <trini@konsulko.com>
2018-05-07 09:34:12 -04:00
Ahmed Mansour
44262327aa drivers/misc: Share qbman init between archs
This patch adds changes necessary to move functionality present in
PowerPC folders with ARM architectures that have DPAA1 QBMan hardware

- Create new board/freescale/common/fsl_portals.c to house shared
  device tree fixups for DPAA1 devices with ARM and PowerPC cores
- Add new header file to top includes directory to allow files in
  both architectures to grab the function prototypes
- Port inhibit_portals() from PowerPC to ARM. This function is used in
  setup to disable interrupts on all QMan and BMan portals. It is
  needed because the interrupts are enabled by default for all portals
  including unused/uninitialised portals. When the kernel attempts to
  go to deep sleep the unused portals prevent it from doing so

Signed-off-by: Ahmed Mansour <ahmed.mansour@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2018-01-10 12:28:47 -08:00
Christophe Kerello
4e280b91a1 dm: misc: add stm32 rcc driver
This patch adds the support of reset and clock control
block (rcc) found on STM32 SoCs.
This driver is similar to a MFD linux driver.

This driver supports currently STM32H7 only.
STM32F4 and STM32F7 will be migrated to this rcc MFD driver
in the future to uniformize all STM32 SoCs already upstreamed.

Signed-off-by: Christophe Kerello <christophe.kerello@st.com>
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Vikas Manocha <vikas.manocha@st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-09-22 07:40:02 -04:00
Wenyou Yang
d81a1de96e misc: Kconfig: Add SPL_I2C_EEPROM option
This option is an SPL-variant of the I2C_EEPROM option to enable
the driver for generic I2C-attached EEPROMs for SPL.

Signed-off-by: Wenyou Yang <wenyou.yang@microchip.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-09-11 22:44:30 -04:00
Marek Behún
aa5eb9a3ac drivers/misc: Add basic support for ATSHA204A Crypto module
This module can be found on the Turris Omnia board connected
via the I2C interface.

Among some cryptographic functions, the chip has a 512 bit
One Time Programmable memory, 88 byte configuration memory
and 512 byte general purpose memory.

The Turris Omnia stores serial number and device MAC address in
the OTP memory.

This commit adds basic support for reading the EEPROM and also
exposes the chips Random Number Generator.

The driver is based on code by
  Josh Datko, Cryptotronix, jbd@cryptotronix.com
and also
  Tomas Hlavacek, CZ.NIC, tomas.hlavacek@nic.cz

Signed-off-by: Tomas Hlavacek <tomas.hlavacek@nic.cz>
Signed-off-by: Marek Behun <marek.behun@nic.cz>

 create mode 100644 drivers/misc/atsha204a-i2c.c
 create mode 100644 include/atsha204a-i2c.h
Signed-off-by: Stefan Roese <sr@denx.de>
2017-07-12 06:57:38 +02:00
Philipp Tomsich
49cd8e85eb rockchip: efuse: add (misc) driver for RK3399 non-secure efuse block
This adds a simple driver for reading the efuse block of the RK3399.
It should be easy enough to add drivers for other devices (e.g. the
RK3328, RK3368, etc.) by passing the device details via driver_data.

Unlike the kernel driver (using the nvmem subsystem), we don't expose
the efuse as multiple named cells, but rather as a linear memory that
can be read using misc_read(...).

The primary use case (as of today) is the generation of a 'serial#'
(and a 'cpuid#') environment variable for the RK3399-Q7 (Puma)
system-on-module.

Note that this adds a debug-only (i.e. only if DEBUG is defined)
command 'rk3399_dump_efuses' that dumps the efuse block's content.
N.B.: The name 'rk3399_dump_efuses' was intentionally chosen to
      include a SoC-name (together with a comment in the function) to
      remind whoever adds support for additional SoCs that this
      function currently makes assumptions regarding the size of the
      fuse-box based on the RK3399. The hope is that the function is
      adjusted to reflect any changes resulting from generalising the
      driver for multiple SoCs and is then renamed.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>

Reviewed-by: Simon Glass <sjg@chromium.org>
2017-06-07 07:29:17 -06:00
Simon Glass
ae189ba1ac Drop the pdsp188x driver
This is not used in U-Boot.

Signed-off-by: Simon Glass <sjg@chromium.org>
2017-04-30 13:41:02 -04:00
Uri Mashiach
2d8d190c83 status_led: Kconfig migration
Move all of the status LED feature to drivers/led/Kconfig.
The LED status definitions were moved from the board configuration
files to the defconfig files.

TBD: Move all of the definitions in the include/status_led.h to the
relevant board's defconfig files.

Tested boards: CL-SOM-AM57x, CM-T335

Signed-off-by: Uri Mashiach <uri.mashiach@compulab.co.il>
2017-01-21 15:12:33 -05:00
Stephen Warren
bd3ee84ac7 misc: implement Tegra CAR core driver
The Tegra CAR (Clock And Reset) module provides control of most clocks
and reset signals within the Tegra SoC. This change implements a driver
for this module. However, since the module implements multiple kinds of
services (clocks, resets, perhaps more), all this driver does is bind
various sub-devices, which in turn provide the real services. This driver
is essentially an "MFD" (Multi-Function Device) in Linux kernel speak.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2016-09-27 09:11:02 -07:00
York Sun
b63a950629 armv8: ls2080a: Remove debug server support
Debug server feature has been dropped from roadmap.

Signed-off-by: York Sun <york.sun@nxp.com>
2016-09-14 14:07:19 -07:00
Stefan Roese
4cf9e464f7 misc: Add simple driver for some Nuvoton NCT6102D devices
This simple driver provides some functions to control some of the
integrated devices. The watchdog is enabled per default. This driver
adds a function to disable the watchdog. Also the internal legacy
UART (io address 0x3f8/0x2f8) is enabled per default.

Signed-off-by: Stefan Roese <sr@denx.de>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Cc: Simon Glass <sjg@chromium.org>
2016-08-16 11:44:09 +08:00
Stephen Warren
73dd5c4cfe misc: add Tegra BPMP driver
The Tegra BPMP (Boot and Power Management Processor) is a separate
auxiliary CPU embedded into Tegra to perform power management work, and
controls related features such as clocks, resets, power domains, PMIC I2C
bus, etc. This driver provides the core low-level communication path by
which feature-specific drivers (such as clock) can make requests to the
BPMP. This driver is similar to an MFD driver in the Linux kernel. It is
unconditionally selected by CONFIG_TEGRA186 since virtually any Tegra186
build of U-Boot will need the feature.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2016-08-15 10:26:12 -07:00
Max Filippov
b25732c22b drivers/sysreset: group sysreset drivers
Create drivers/sysreset and move sysreset-uclass and all sysreset
drivers there.

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2016-08-12 09:22:17 -04:00
Simon Glass
2c9dfb5807 sandbox: Don't bring in the eeprom emulator in SPL
This driver should not be used in SPL since we do not have I2C support
enabled in SPL on sandbox.

Signed-off-by: Simon Glass <sjg@chromium.org>
2016-07-14 20:40:24 -06:00
Simon Glass
bab8233a1d dm: sandbox: Add a simple driver to test of-platdata
Add a driver which uses of-platdata to obtain its platform data. This can
be used to test the feature in sandbox. It displays the contents of its
platform data.

Signed-off-by: Simon Glass <sjg@chromium.org>
2016-07-14 20:40:24 -06:00
Stephen Warren
1163625898 Rename reset to sysreset
The current reset API implements a method to reset the entire system.
In the near future, I'd like to introduce code that implements the device
tree reset bindings; i.e. the equivalent of the Linux kernel's reset API.
This controls resets to individual HW blocks or external chips with reset
signals. It doesn't make sense to merge the two APIs into one since they
have different semantic purposes. Resolve the naming conflict by renaming
the existing reset API to sysreset instead, so the new reset API can be
called just reset.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Simon Glass <sjg@chromium.org>
2016-05-26 20:48:31 -06:00
Miao Yan
1868659002 cmd: qfw: rename qemu_fw_cfg.[c|h] to qfw.[c|h]
Make file names consistent with CONFIG_QFW and CONFIG_CMD_QFW

Signed-off-by: Miao Yan <yanmiaobest@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-05-23 15:18:00 +08:00
Miao Yan
fcf5c04193 x86: qemu: split qfw command interface and qfw core
This patch splits qfw command interface and qfw core function into two
files, and introduces a new Kconfig option (CONFIG_QFW) for qfw core.

Now when qfw command interface is enabled, it will automatically select
qfw core. This patch also makes the ACPI table generation select
CONFIG_QFW.

Signed-off-by: Miao Yan <yanmiaobest@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-05-23 15:18:00 +08:00