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1186 commits

Author SHA1 Message Date
Stefan Roese
1d7b874e9c ppc4xx: Cleanup of 4xx PCI and PCIe support (renaming)
Signed-off-by: Stefan Roese <sr@denx.de>
2007-10-31 21:20:49 +01:00
Stefan Roese
4f14ed6230 ppc4xx: Add initial fdt support to 4xx (first needed on 405EX)
Signed-off-by: Stefan Roese <sr@denx.de>
2007-10-31 21:20:49 +01:00
Stefan Roese
19e93b1e16 ppc4xx: 4xx_pcie: Change PCIe status output to match common style
Signed-off-by: Stefan Roese <sr@denx.de>
2007-10-31 21:20:49 +01:00
Stefan Roese
ff68f66bcb ppc4xx: 4xx_pcie: Disable debug output as default
Signed-off-by: Stefan Roese <sr@denx.de>
2007-10-31 21:20:49 +01:00
Stefan Roese
97923770cb ppc4xx: 4xx_pcie: More general cleanup and 405EX PCIe support added
Signed-off-by: Stefan Roese <sr@denx.de>
2007-10-31 21:20:49 +01:00
Stefan Roese
4dbee8a90d ppc4xx: 4xx_pcie: Change CFG_PCIE_MEMSIZE to 128MB on Yucca & Katmai
128MB seems to be the smallest possible value for the memory size
for on PCIe port. With this change now the BAR's of the PCIe cards
are accessible under U-Boot.

One big note: This only works for PCIe port 0 & 1. For port 2 this
currently doesn't work, since the base address is now 0xc0000000
(0xb0000000 + 2 * 0x08000000), and this is already occupied by
CFG_PCIE0_CFGBASE. But solving this issue for port 2 would mean
to change the base addresses completely and this change would have
too much impact right now.

This patch adds debug output to the 4xx pcie driver too.

Signed-off-by: Stefan Roese <sr@denx.de>
2007-10-31 21:20:49 +01:00
Stefan Roese
6d95289281 ppc4xx: 4xx_pcie: Fix problem with SDRN access using port number as idx
Signed-off-by: Stefan Roese <sr@denx.de>
2007-10-31 21:20:49 +01:00
Stefan Roese
3048bcbf0b ppc4xx: Rename 405gp_pci to 4xx_pci since its used on all 4xx platforms
These files were introduced with the IBM 405GP but are currently used on all
4xx PPC platforms. So the name doesn't match the content anymore. This patch
renames the files to 4xx_pci.c/h.

Signed-off-by: Stefan Roese <sr@denx.de>
2007-10-31 21:20:49 +01:00
Stefan Roese
94276eb0a7 ppc4xx: Add a comment for 405EX PCIe endpoint configuration
Signed-off-by: Stefan Roese <sr@denx.de>
2007-10-31 21:20:49 +01:00
Stefan Roese
03d344bb6a ppc4xx: Make 440SPe PCIe code more generic to use on different 4xx PPCs (3)
(3) This patch introduces macros like SDRN_PESDR_DLPSET(port) to access
    the SDR registers of the PCIe ports. This makes the overall design
    clearer, since it removed a lot of switch statements which are not
    needed anymore.

    Also, the functions ppc4xx_init_pcie_rootport() and
    ppc4xx_init_pcie_entport() are merged into a single function
    ppc4xx_init_pcie_port(), since most of the code was duplicated.
    This makes maintainance and porting to other 4xx platforms
    easier.

Signed-off-by: Stefan Roese <sr@denx.de>
2007-10-31 21:20:49 +01:00
Stefan Roese
026f711068 ppc4xx: Make 440SPe PCIe code more generic to use on different 4xx PPCs (2)
This patch is the first patch of a series to make the 440SPe PCIe code
usable on different 4xx PPC platforms. In preperation for the new 405EX
which is also equipped with PCIe interfaces.

(2) This patch renames the functions from 440spe_ to 4xx_ with a
    little additional cleanup

Signed-off-by: Stefan Roese <sr@denx.de>
2007-10-31 21:20:49 +01:00
Stefan Roese
c7c6da2302 ppc4xx: Make 440SPe PCIe code more generic to use on different 4xx PPCs (1)
This patch is the first patch of a series to make the 440SPe PCIe code
usable on different 4xx PPC platforms. In preperation for the new 405EX
which is also equipped with PCIe interfaces.

(1) This patch renames the files from 440spe_pcie to 4xx_pcie

Signed-off-by: Stefan Roese <sr@denx.de>
2007-10-31 21:20:48 +01:00
TsiChungLiew
c67e12e705 ColdFire 5329: Assign correct SDRAM size and fix cache
Signed-off-by: TsiChungLiew <Tsi-Chung.Liew@freescale.com>
2007-10-25 17:12:36 -05:00
TsiChungLiew
2acefa72ee ColdFire 5282: Fix external flash boot and return dramsize
Signed-off-by: TsiChungLiew <Tsi-Chung.Liew@freescale.com>
2007-10-25 17:09:17 -05:00
Jean-Christophe PLAGNIOL-VILLARD
e9d0d52799 delta: Fix OHCI_REGS_BASE undeclared and wait_ms implicit declaration
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
2007-10-24 00:29:14 +02:00
Jean-Christophe PLAGNIOL-VILLARD
9c4884f54d fix warning: no return statement in function returning non-void
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
2007-10-24 00:29:06 +02:00
Marcel Ziswiler
2a4741d9a1 fix pxa255_idp board
The pxa255_idp being an old unmaintained board showed several issues:
1. CONFIG_INIT_CRITICAL was still defined.
2. Neither CONFIG_MAC_PARTITION nor CONFIG_DOS_PARTITION was defined.
3. Symbol flash_addr was undeclared.
4. The boards lowlevel_init function was still called memsetup.
5. The TEXT_BASE was still 0xa3000000 rather than 0xa3080000.
6. Using -march=armv5 instead of -march=armv5te resulted in lots of
'target CPU does not support interworking' warnings on recent compilers.
7. The PXA's serial driver redefined FFUART, BTUART and STUART used as
indexes rather than the register definitions from the pxa-regs header
file. Renamed them to FFUART_INDEX, BTUART_INDEX and STUART_INDEX to
avoid any ambiguities.
8. There were several redefinition warnings concerning ICMR, OSMR3,
OSCR, OWER, OIER, RCSR and CCCR in the PXA's assembly start file.
9. The board configuration file was rather outdated.
10. The part header file defined the vendor, product and revision arrays
as unsigned chars instead of just chars in the block_dev_desc_t
structure.

Signed-off-by: Marcel Ziswiler <marcel@ziswiler.com>
2007-10-23 16:40:40 +02:00
Shinya Kuribayashi
00101dd7a3 [MIPS] Add PIC-related switches to PLATFORM_{CPP,LD}FLAGS and cleanup
Signed-off-by: Shinya Kuribayashi <shinya.kuribayashi@necel.com>
2007-10-21 21:30:42 +09:00
Shinya Kuribayashi
22069215eb [MIPS] Fix $gp usage
Now we load $gp with _GLOBAL_OFFSET_TABLE_, but this is incorrect use.
As a general principle, we should use _gp for $gp.

Thanks to linker script's help we fortunately have _gp which equals to
_GLOBAL_OFFSET_TABLE_. But once _gp gets out of alignment, we will not
be able to access to GOT entires, global variables and procedure entry
points. The right thing to do is to use _gp.

This patch also introduce a new symbol `.gpword _GLOBAL_OFFSET_TABLE_'
which holds the offset from _gp. When updating GOT entries, we use this
offset and _gp to calculate the final _GLOBAL_OFFSET_TABLE_.

This patch is originally submitted by Vlad Lungu <vlad@comsys.ro>, then
I made some change to leave over num_got_entries.

Signed-off-by: Shinya Kuribayashi <shinya.kuribayashi@necel.com>
Cc: Vlad Lungu <vlad@comsys.ro>
2007-10-21 10:55:36 +09:00
urwithsughosh@gmail.com
df90968b48 Setting MSR[DE] in do_reset
Hello,
   This patch ensures the soft reset of the board for the 85xx boards
   by setting the MSR[DE] in the do_reset function.

Signed-off-by: Sughosh Ganu <urwithsughosh@gmail.com>
2007-10-19 13:13:44 -05:00
urwithsughosh@gmail.com
1e701e7013 MSR overwrite fix
Hello,
  This patch fixes the MSR overwrite in the start.S when moving out of
  the last 4K page.

Signed-off-by: Sughosh Ganu <urwithsughosh@gmail.com>
2007-10-19 13:13:27 -05:00
Kumar Gala
e1ce3cb617 Remove magic numbers from cache related operations for mpc85xx
The mpc85xx start code uses some magic numbers that we actually
have #defines for in <config.h> so use those instead.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2007-10-19 11:25:01 -05:00
Andy Fleming
d4d1e9bee7 Merge branch 'denx' 2007-10-19 11:24:22 -05:00
Jon Loeliger
9553df86d3 Initial mpc8610hpcd cpu/, README and include/ files.
Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com>
Signed-off-by: Mahesh Jade <mahesh.jade@freescale.com>
Signed-off-by: Jason Jin <Jason.jin@freescale.com>
Signed-off-by: Jon Loeliger <jdl@freescale.com>
2007-10-17 15:01:47 -05:00
Jon Loeliger
2491167c24 86xx: Allow for fewer DDR slots per memory controller.
As a direct correlation exists between DDR DIMM slots
and SPD EEPROM addresses used to configure them, use
the individually defined SPD_EEPROM_ADDRESS* values to
determine if a DDR DIMM slot should have its SPD
configuration read or not.

Effectively, this now allows for 1 or 2 DIMM slots
per memory controller.

Signed-off-by: Jon Loeliger <jdl@freescale.com>
2007-10-16 16:36:36 +02:00
Rodolfo Giometti
4d4a945e18 PXA USB OHCI: "usb stop" implementation.
Some USB keys need to be switched off before loading the kernel
otherwise they can remain in an undefined status which prevents them
to be correctly recognized by the kernel.

Signed-off-by: Rodolfo Giometti <giometti@linux.it>
2007-10-15 12:57:41 +02:00
Jean-Christophe PLAGNIOL-VILLARD
68f14f77ca Fix warning differ in signedness in cpu/pxa/mmc.c
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
2007-10-13 23:57:25 +02:00
Wolfgang Denk
8f05a661e9 Merge branch 'merge' of git://www.denx.de/git/u-boot-microblaze 2007-10-13 22:57:43 +02:00
Peter Pearse
e81a95a9e7 Merge with git://www.denx.de/git/u-boot.git 2007-10-04 11:00:44 +01:00
Stefan Roese
527c80f012 Merge with git://www.denx.de/git/u-boot.git 2007-10-02 11:47:13 +02:00
Stefan Roese
738815c0cc ppc4xx: Coding style cleanup
Signed-off-by: Stefan Roese <sr@denx.de>
2007-10-02 11:44:46 +02:00
Grzegorz Bernacki
2db6478406 Program EPLD to force full duplex mode for PHY.
EPLD forces modes of PHY operation. By default full duplex is turned off.
This fix turns it on.

Signed-off-by: Grzegorz Bernacki <gjb@semihalf.com>
2007-10-02 11:30:37 +02:00
Jean-Christophe PLAGNIOL-VILLARD
86ec86c043 Fix missing DECLARE_GLOBAL_DATA_PTR on CONFIG_LPC2292 in serial
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
2007-09-28 01:08:38 +02:00
Ed Swarthout
1487adbdcf 85xx io out functions need sync after write.
This fixes the mc146818 rtc_read/write functions for 85xx.

Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com>
2007-09-26 16:50:02 -05:00
Michal Simek
1c1100d2fc [PATCH] Add support for design without interrupt controller
Polling timer
2007-09-24 00:21:19 +02:00
Michal Simek
0731933ec8 [FIX] resolve problem with cpu without barrel shifter 2007-09-24 00:19:48 +02:00
Michal Simek
db14d77995 [FIX] repair email address 2007-09-24 00:18:46 +02:00
Michal Simek
b90c045f03 synchronizition with mainline 2007-09-24 00:08:37 +02:00
Michal Simek
6b6f287a33 Merge ../u-boot 2007-09-24 00:04:22 +02:00
Nobuhiro Iwamatsu
b02bad1286 sh: Update core code of SuperH.
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2007-09-23 02:12:30 +09:00
Nobuhiro Iwamatsu
b8685affe6 Merge git://www.denx.de/git/u-boot
Conflicts:

	CREDITS
2007-09-23 01:29:43 +09:00
Peter Pearse
bd86220f58 Move coloured led API to status_led.h
Improve indentation in drivers/at45.c
2007-09-18 13:07:54 +01:00
Peter Pearse
afd477b227 Merge with git://www.denx.de/git/u-boot.git 2007-09-18 11:12:58 +01:00
Wolfgang Denk
1218abf1b5 Fix cases where DECLARE_GLOBAL_DATA_PTR was not declared as global
Signed-off-by: Wolfgang Denk <wd@denx.de>
2007-09-15 20:48:41 +02:00
Peter Pearse
d94c79e470 Final tidy 2007-09-11 15:35:01 +01:00
Peter Pearse
9d3cb9febe Merge with git://www.denx.de/git/u-boot.git 2007-09-11 14:26:23 +01:00
Michal Simek
9c73f4b811 Merge git://www.denx.de/git/u-boot 2007-09-11 00:29:27 +02:00
Grzegorz Bernacki
7a888d6b3c [MPC512x] Streamline frame handling in the FEC driver
- convert frame size settings to be derived from a single base
- set frame size to the recommended default value

Signed-off-by: Grzegorz Bernacki <gjb@semihalf.com>
2007-09-10 17:39:08 +02:00
Peter Pearse
7d54d64e9c Merge with git://www.denx.de/git/u-boot.git 2007-09-10 10:11:15 +01:00
Kyungmin Park
e251e00d0d Remove compiler warning: target CPU does not support interworking
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
2007-09-10 09:26:35 +02:00