Commit graph

163 commits

Author SHA1 Message Date
Jason Jin
c0391111c3 Fix the incorrect DDR clk freq reporting on 8536DS
On 8536DS board, When the DDR clk is set async mode(SW3[6:8] != 111),
The display is still sync mode DDR freq. This patch try to fix
this. The display DDR freq is now the actual freq in both
sync and async mode.

Signed-off-by: Jason Jin <Jason.jin@freescale.com>
2008-10-07 15:37:08 -05:00
Kumar Gala
bac6a1d1fa 85xx: Remove setting of *cache-line-size in device trees
ePAPR says if the *cache-block-size is the same as *cache-line-size
than we don't need the *cache-line-size property.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2008-10-07 10:28:59 -05:00
Andrew Klossner
5251469943 Fix printf errors under -DDEBUG
Fix printf format-string/arg mismatches under -DDEBUG.

These warnings occur with DEBUG defined for a platform using
cpu/mpc85xx.  Users of other architectures can unearth similar
problems by adding the line "CFLAGS += -DDEBUG=1" in config.mk right
after "CFLAGS += $(call cc-option,-fno-stack-protector)".

Signed-off-by: Andrew Klossner <andrew@cesa.opbu.xerox.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2008-09-09 17:02:41 -05:00
Kumar Gala
e0ff3d350d 85xx: Ensure timebase is zero on secondary cores
The e500um says the timebase is volatile out of reset.  To ensure
TB sync works we need to make sure its zero.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2008-09-09 16:52:45 -05:00
Sergei Poselenov
6cc64f9b5f Removed hardcoded MxMR loop value from upmconfig() for MPC85xx.
Signed-off-by: Sergei Poselenov <sposelenov@emcraft.com>
2008-09-08 19:48:55 -05:00
Andy Fleming
75b9d4ae0d Pass in tsec_info struct through tsec_initialize
The tsec driver contains a hard-coded array of configuration information
for the tsec ethernet controllers.  We create a default function that works
for most tsecs, and allow that to be overridden by board code.  It creates
an array of tsec_info structures, which are then parsed by the corresponding
driver instance to determine configuration.  Also, add regs, miiregs, and
devname fields to the tsec_info structure, so that we don't need the kludgy
"index" parameter.

Signed-off-by: Andy Fleming <afleming@freescale.com>
Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
2008-09-02 21:18:15 -07:00
Kumar Gala
9cff4448a9 mpc85xx: remove redudant code with lib_ppc/interrupts.c
For some reason we duplicated the majority of code in lib_ppc/interrupts.c
not show how that happened, but there is no good reason for it.

Use the interrupt_init_cpu() and timer_interrupt_cpu() since its why
they exist.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2008-08-27 11:44:10 -05:00
Kumar Gala
ef50d6c06e mpc85xx: Add support for the MPC8536
The MPC8536 Adds SDHC and SATA controllers to the PQ3 family.  We
also have SERDES init code for the 8536.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Signed-off-by: Srikanth Srinivasan <srikanth.srinivasan@freescale.com>
Signed-off-by: Dejan Minic <minic@freescale.com>
Signed-off-by: Jason Jin <Jason.jin@freescale.com>
Signed-off-by: Dave Liu <daveliu@freescale.com>
2008-08-27 11:43:54 -05:00
Kumar Gala
129ba616b3 mpc85xx: Add support for the MPC8572DS reference board
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2008-08-27 11:43:53 -05:00
Kumar Gala
457caecdbc FSL DDR: Remove old SPD support from cpu/mpc85xx
All 85xx boards have been converted to the new code so we can
remove the old SPD DDR setup code.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2008-08-27 11:43:53 -05:00
Kumar Gala
2a6c2d7ab2 FSL DDR: Add 85xx specific register setting
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2008-08-27 11:43:48 -05:00
Kumar Gala
6fb1b73468 FSL DDR: Add e500 TLB helper for DDR code
Provide a helper function that board code can call to map TLBs when
setting up DDR.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2008-08-27 11:43:48 -05:00
Kumar Gala
58e5e9aff1 FSL DDR: Rewrite the FSL mpc8xxx DDR controller setup code.
The main purpose of this rewrite it to be able to share the same
initialization code on all FSL PowerPC products that have DDR
controllers.  (83xx, 85xx, 86xx).

The code is broken up into the following steps:
	GET_SPD
	COMPUTE_DIMM_PARMS
	COMPUTE_COMMON_PARMS
	GATHER_OPTS
	ASSIGN_ADDRESSES
	COMPUTE_REGS
	PROGRAM_REGS

This allows us to share more code an easily allow for board specific code
overrides.

Additionally this code base adds support for >4G of DDR and provides a
foundation for supporting interleaving on processors with more than one
controller.

Signed-off-by: James Yang <James.Yang@freescale.com>
Signed-off-by: Jon Loeliger <jdl@freescale.com>
Signed-off-by: Becky Bruce <becky.bruce@freescale.com>
Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2008-08-27 02:05:58 +02:00
Kumar Gala
ba37aa0328 fdt: rework fdt_fixup_ethernet() to use env instead of bd_t
Move to using the environment variables 'ethaddr', 'eth1addr', etc..
instead of bd->bi_enetaddr, bi_enet1addr, etc.

This makes the code a bit more flexible to the number of ethernet
interfaces.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2008-08-21 02:07:43 +02:00
Kumar Gala
902ca09246 85xx: Rename CONFIG_NR_CPUS to CONFIG_NUM_CPUS
Use CONFIG_NUM_CPUS to match existing define used by 86xx.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Acked-by: Jon Loeliger <jdl@freescale.com>
2008-08-12 00:09:29 +02:00
Wolfgang Denk
1d28d48e3d Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx 2008-07-15 21:37:23 +02:00
Kumar Gala
73f15a060f 85xx: Cleanup L2 cache size detection
The L2 size detection code was a bit confusing and we kept having to add
code to it to handle new processors.  Change the sense of detection so we
look for the older processors that aren't changing.

Also added support for 1M cache size on 8572.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2008-07-14 20:14:20 -05:00
Paul Gortmaker
71074abbe0 8xxx-fdt: set ns16550 clock from CFG_NS16550_CLK, not bi_busfreq
Some boards that have external 16550 UARTs don't have a direct
tie between bi_busfreq and the clock used for the UARTs.  Boards
that do have such a tie should set CFG_NS16550_CLK to be
get_bus_freq(0) -- which most of them do already.

Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
Acked-by: Kim Phillips <kim.phillips@freescale.com>
2008-07-14 18:56:51 -05:00
Andrew Klossner
24ef76f320 Change the temp map to ROM to align addresses to page size.
With a page size of BOOKE_PAGESZ_16M, both the real and effective
addresses must be multiples of 16MB.  The hardware silently truncates
them so the code happens to work.  This patch clarifies the situation
by establishing addresses that the hardware doesn't need to truncate.

Signed-off-by: Andrew Klossner <andrew@cesa.opbu.xerox.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2008-07-14 18:46:32 -05:00
Kim Phillips
06b4186c10 mpc85xx: use IS_E_PROCESSOR macro
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2008-07-14 17:01:34 -05:00
Kim Phillips
6b70ffb9d1 fdt: add crypto node handling for MPC8{3, 5}xxE processors
Delete the crypto node if not on an E-processor.  If on 8360 or 834x family,
check rev and up-rev crypto node (to SEC rev. 2.4 property values)
if on an 'EA' processor, e.g. MPC8349EA.

Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2008-07-14 17:01:29 -05:00
Kumar Gala
348753d416 Fix some more printf() format problems.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2008-07-14 23:01:01 +02:00
Andrew Klossner
dc4b0b38d4 Fix printf errors.
The compiler will help find mismatches between printf formats and
arguments if you let it.  This patch adds the necessary attributes to
declarations in include/common.h, then begins to correct the resulting
compiler warnings.  Some of these were bugs, e.g., "$d" instead of
"%d" and incorrect arguments.  Others were just annoying, like
int-long mismatches on a system where both are 32 bits.  It's worth
fixing the annoying errors to catch the real ones.

Signed-off-by: Andrew Klossner <andrew@cesa.opbu.xerox.com>
2008-07-09 23:55:46 +02:00
Wolfgang Denk
9692cab76f Merge branch 'master' of git://www.denx.de/git/u-boot-net 2008-07-09 23:22:54 +02:00
Ben Warren
dd35479a50 Add mechanisms for CPU and board-specific Ethernet initialization
This patch is the first step in cleaning up net/eth.c, by moving Ethernet
initialization to CPU or board-specific code.  Initial implementation is
only on the Freescale TSEC controller, but others will be added soon.

Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
2008-07-06 00:20:59 -07:00
Wolfgang Denk
e093a24762 Coding Style Cleanup
Signed-off-by: Wolfgang Denk <wd@denx.de>
2008-06-28 23:34:37 +02:00
Anatolij Gustschin
96026d42fa Fix 4xx build issue
Building for 4xx doesn't work since commit 4dbdb768:

In file included from 4xx_pcie.c:28:
include/asm/processor.h:971: error: expected ')' before 'ver'
make[1]: *** [4xx_pcie.o] Error 1

This patch fixes the problem.

Signed-off-by: Anatolij Gustschin <agust@denx.de>
Acked-by: Stefan Roese <sr@denx.de>
Acked-by: Kumar Gala <galak@kernel.crashing.org>
2008-06-19 22:48:45 +02:00
Kumar Gala
859a86a25c 85xx/86xx: Move to dynamic mgmt of LAWs
With the new LAW interface (set_next_law) we can move to letting the
system allocate which LAWs are used for what purpose.  This makes life
a bit easier going forward with the new DDR code.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Signed-off-by: Andy Fleming <afleming@freescale.com>
Acked-by: Jon Loeliger <jdl@freescale.com>
Acked-by: Becky Bruce <becky.bruce@freescale.com>
2008-06-11 01:52:23 -05:00
Kumar Gala
f060054dad FSL LAW: Keep track of LAW allocations
Make it so we keep track of which LAWs have allocated and provide
a function (set_next_law) which can allocate a LAW for us if one is
free.

In the future we will move to doing more "dynamic" LAW allocation
since the majority of users dont really care about what LAW number
they are at.

Also, add CONFIG_MPC8540 or CONFIG_MPC8560 to those boards which needed them

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2008-06-11 01:50:53 -05:00
Sergei Poselenov
740280e68c Added the upmconfig() function for 85xx.
Signed-off-by: Sergei Poselenov <sposelenov@emcraft.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2008-06-11 00:29:29 -05:00
Wolfgang Grandegger
6beecfbb54 MPC85xx: Beautify boot output of L2 cache configuration
The boot output is now aligned poperly with other boot output
lines, e.g.:

  FLASH: 128 MB
  L2:    512 KB enabled

Signed-off-by: Wolfgang Grandegger <wg@grandegger.com>
2008-06-10 18:22:26 -05:00
Kumar Gala
730b2fcf6f 85xx: Add setting of cache props in the device tree.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2008-06-10 18:22:25 -05:00
Kumar Gala
4dbdb7681e 85xx: expose cpu identification
The current cpu identification code is used just to return the name
of the processor at boot.  There are some other locations that the name
is useful (device tree setup).  Expose the functionality to other bits
of code.

Also, drop the 'E' suffix and add it on by looking at the SVR version
when we print this out.  This is mainly to allow the most flexible use
of the name.  The device tree code tends to not care about the 'E' suffix.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2008-06-10 18:22:25 -05:00
Kumar Gala
ee1e35bede 85xx: Only use PORPLLSR[DDR_Ratio] on platforms that define it
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2008-06-09 13:31:20 -05:00
Becky Bruce
3b9519fc50 MPC85xx: Change traps.c to not reference non-addressable memory
Currently, END_OF_RAM is used by the trap code to determine if
we should attempt to access the stack pointer or not. However,
on systems with a lot of RAM, only a subset of the RAM is
guaranteed to be mapped in and accessible.  Change END_OF_RAM
to use get_effective_memsize() instead of using the raw ram
size out of the bd.

Signed-off-by: Becky Bruce <becky.bruce@freescale.com>
2008-06-09 13:31:20 -05:00
Wolfgang Denk
0ad4770f8e Merge branch 'socrates' of /home/wd/git/u-boot/projects 2008-05-21 01:13:52 +02:00
Wolfgang Denk
53677ef18e Big white-space cleanup.
This commit gets rid of a huge amount of silly white-space issues.
Especially, all sequences of SPACEs followed by TAB characters get
removed (unless they appear in print statements).

Also remove all embedded "vim:" and "vi:" statements which hide
indentation problems.

Signed-off-by: Wolfgang Denk <wd@denx.de>
2008-05-21 00:14:08 +02:00
Sergei Poselenov
793670c3c0 Fixed reset for socrates
Signed-off-by: Sergei Poselenov <sposelenov@emcraft.com>
2008-05-20 23:27:50 +02:00
Kumar Gala
70a0f81412 85xx: Add -mno-spe to e500/85xx builds
Newer gcc's might be configured to enable autovectorization by default.
If we happen to build with one of those compilers we will get SPE
instructions in random code.

-mno-spe disables the compiler for automatically generating SPE
instructions without our knowledge.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2008-04-29 20:08:43 +02:00
Kumar Gala
45239cf415 85xx/86xx: Rename ext_refrec to timing_cfg_3 to match docs
All the 85xx and 86xx UM describe the register as timing_cfg_3
not as ext_refrec.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2008-04-29 11:44:29 -05:00
Kumar Gala
cf6cc01427 85xx: Additional fixes and cleanup of MP code
* adjust __spin_table alignment to match ePAPR v0.94 spec
* loop over all cpus when determing who is up.  This fixes an issue if
  the "boot cpu" isn't core0.  The "boot cpu" will already be in the
  cpu_up_mask so there is no harm
* Added some protection in the code to ensure proper behavior.  These
  changes are explicitly needed but don't hurt:
  - Added eieio to ensure the "hot word" of the table is written after
    all other table updates have occurred.
  - Added isync to ensure we don't prefetch loading of table entries
    until we a released

These issues we raised by Dave Liu.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2008-04-29 09:42:19 -05:00
Kumar Gala
022f121635 85xx: Round up frequency calculations to get reasonable output
eg. because of rounding error we can get 799Mhz instead of 800Mhz.

Introduced DIV_ROUND_UP and roundup taken from linux kernel.

Signed-off-by: Dejan Minic <minic@freescale.com>
Signed-off-by: Srikanth Srinivasan <srikanth.srinivasan@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Acked-by: Andy Fleming <afleming@freescale.com>
2008-04-24 15:42:35 +02:00
Kumar Gala
0878af169b 85xx: Fix size of cpu-release-addr property
The cpu-release-addr is defined as always being a 64-bit quanity regardless
if we are running on a 32-bit or 64-bit machine.
2008-04-18 17:44:50 -05:00
Timur Tabi
88353a9851 Fix calculation of I2C clock for some 85xx chips
Some 85xx chips use CCB as the base clock for the I2C.  Some use CCB/2, and
some use CCB/3.  There is no pattern that can be used to determine which
chips use which frequency, so the only way to determine is to look up the
actual SOC designation and use the right value for that SOC.

Update immap_85xx.h to include the GUTS PORDEVSR2 register.

Signed-off-by: Timur Tabi <timur@freescale.com>
2008-04-18 17:43:09 -05:00
Kumar Gala
97b3ecb575 85xx: Fix detection of MP cpu spin up
We were looking at the wrong memory offset to determine of a secondary
cpu had been spun up or not.  Also added a warning message if the
all the secondary cpus we expect don't spin up.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2008-04-11 17:32:56 -05:00
Kumar Gala
f3e04bdc3f 85xx: Use SVR_SOC_VER instead of SVR_VER
The recent change introduced by 'Update SVR numbers to expand support'
now requires that we use SVR_SOC_VER instead of SVR_VER if we want
to compare against a particular processor id.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2008-04-11 17:32:51 -05:00
Kumar Gala
dd6c910aad 85xx: Add cpu_mp_lmb_reserve helper to reserve boot page
Provide a board_lmb_reserve helper function to ensure we reserve
the page of memory we are using for the boot page translation code.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2008-03-26 11:43:04 -05:00
Kumar Gala
79679d8002 85xx: Update multicore boot mechanism to ePAPR v0.81 spec
The following changes are needed to be inline with ePAPR v0.81:

* r4, r5 and now always set to 0 on boot release
* r7 is used to pass the size of the initial map area (IMA)
* EPAPR_MAGIC value changed for book-e processors
* changes in the spin table layout
* spin table supports a 64-bit physical release address

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2008-03-26 11:43:04 -05:00
Kumar Gala
a5af4b358a 85xx: Fix merge duplication
ft_fixup_cpu() got duplicated in some merge snafu.  Remove the duplicate.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2008-03-26 11:43:04 -05:00
James Yang
a3e77fa535 85xx: Speed up get_ddr_freq() and get_bus_freq()
get_ddr_freq() and get_bus_freq() used get_sys_info() each time they were
called.  However, get_sys_info() recalculates extraneous information when
called each time.  Have get_ddr_freq() and get_bus_freq() return memoized
values from global_data instead.

Signed-off-by: James Yang <James.Yang@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2008-03-26 11:43:04 -05:00