Commit graph

22492 commits

Author SHA1 Message Date
Claudiu Manoil
5be00a0164 net: fsl_mdio: Fix warnings for __iomem pointers
Add the __iomem address space marker for the tsec pointers
to struct tsec_mii_mng memory mapped register regions.
This solves the sparse warnings for mixig normal pointers with
__iomem pointers for tsec. E.g.:

fsl_mdio.c:34:19: warning: incorrect type in argument 1 (different
address spaces)
fsl_mdio.c:34:19:    expected unsigned int volatile [noderef]
<asn:2>*addr
fsl_mdio.c:34:19:    got unsigned int *<noident>
[...]

tsec.c:91:35: warning: incorrect type in argument 1 (different address
spaces)
tsec.c:91:35:    expected struct tsec_mii_mng *phyregs
tsec.c:91:35:    got struct tsec_mii_mng [noderef] <asn:2>*phyregs_sgmii
[...]

tsec.c:680:19: warning: incorrect type in assignment (different address
spaces)
tsec.c:680:19:    expected struct tsec_mii_mng *regs
tsec.c:680:19:    got struct tsec_mii_mng [noderef] <asn:2>*<noident>
[...]

Signed-off-by: Claudiu Manoil <claudiu.manoil@freescale.com>
2013-11-22 17:03:15 -06:00
Claudiu Manoil
aec84bf671 net: tsec: Cleanup tsec regs init and fix __iomem warns
Remove tsec_t typedef.  Define macros as getters of
tsec and mdio register memory regions, for consistent
initialization of various 'regs' fields and also to
manage overly long initialization lines.
Use the __iomem address space marker to address sparse
warnings in tsec.c where IO accessors are used, like:

tsec.c:394:19: warning: incorrect type in argument 1 (different
address spaces)
tsec.c:394:19:    expected unsigned int volatile [noderef]
<asn:2>*addr
tsec.c:394:19:    got unsigned int *<noident>
[...]

Add the __iomem address space marker for the tsec pointers
to struct tsec_mii_mng memory mapped register regions.
This solves the sparse warnings for mixig normal pointers
with __iomem pointers for tsec.

Signed-off-by: Claudiu Manoil <claudiu.manoil@freescale.com>
2013-11-22 17:03:15 -06:00
Claudiu Manoil
b200204e8e net: tsec: Fix priv pointer in tsec_mcast_addr()
Access to privlist[1] (hardcoded referece to the 2nd tsec's
priv area) is neither correct nor does it make sense in the
current context.  Each tsec dev has access to its own priv
instance only, and hence to its own set of group address
registers (GADDR) to filter multicast addresses.

This fix leads to removal of the unused (faulty) privlist[]
and related global static vars.  Note that mcast() can be
called only after eth_device allocation and init, and hence
after priv area allocation, so dev->priv is correctly
initialized upon mcast() call.

Signed-off-by: Claudiu Manoil <claudiu.manoil@freescale.com>
Patch: 278990
2013-11-22 17:02:56 -06:00
Claudiu Manoil
876d4515e3 net: tsec: Fix and cleanup tsec_mcast_addr()
There are several implementation issues for tsec_mcast_addr()
addressed by this patch:
* unmanaged, not portable r/w access to registers; fixed with
setbits_be32()/ clrbits_be32()
* use of volatile pointers
* unnecessary forced cast to u8 for the ether_crc() result
* removed redundant parens
* corrected some comment slips

Signed-off-by: Claudiu Manoil <claudiu.manoil@freescale.com>
Patch: 279000
2013-11-22 16:57:47 -06:00
Claudiu Manoil
9c4cffacec net: Fix mcast function pointer prototype
This fixes the following compiler warnings when activating
CONFIG_MCAST_TFTP:

tsec.c: In function 'tsec_mcast_addr':
tsec.c:130:2: warning: passing argument 2 of 'ether_crc' makes pointer
from integer without a cast [enabled by default]
In file included from /work/u-boot-net/include/common.h:874:0,
                 from tsec.c:15:
/work/u-boot-net/include/net.h:189:5: note: expected 'const unsigned
char *' but argument is of type 'u8'
tsec.c: In function 'tsec_initialize':
tsec.c:646:13: warning: assignment from incompatible pointer type
[enabled by default]
eth.c: In function 'eth_mcast_join':
eth.c:358:2: warning: passing argument 2 of 'eth_current->mcast' makes
integer from pointer without a cast [enabled by default]
eth.c:358:2: note: expected 'u32' but argument is of type 'u8 *'

In the eth_mcast_join() implementation, eth_current->mcast()
takes a u8 pointer to the multicast mac address and not a ip
address value as implied by its prototype.

Fix parameter type mismatch for tsec_macst_addr() (tsec.c):
ether_crc() takes a u8 pointer not a u8 value.
mcast() is given a u8 pointer to the multicats mac address.
Update parameter type for the rest of mcast() instances.

Signed-off-by: Claudiu Manoil <claudiu.manoil@freescale.com>
Patch: 278989
2013-11-22 16:57:13 -06:00
Alexey Brodkin
ed102be70f net: designware: Fix alignment of buffer descriptors
It's important that buffer descriptors are aligned in accordance to GMAC
data bus width (32/64/128-bit). It's safe to align to 128-bit (16-bytes)
for every bus width type.

If buffer descriptor is improperly aligned GMAC discards lower bits of
provided address and as a result reads from improper location that
doesn't match expected fields.

Commit ef76025a99 "net: Multiple
updates/enhancements to designware.c" introduced another structure
member "link_printed" right before buffer descriptors while "padding"
member was left untouched. This together with alignment of structure
itself to 16-byte boundary forces buffer descriptoprs always to be
4-byte aligned that causes driver complete disfunction if GMAC bus width
is 64 or 128-bit.

Proposed change makes sure all buffer descriptors are 16-byte (128-bit)
aligned.

Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
Patch: 277902
2013-11-22 16:50:55 -06:00
Alexey Brodkin
227ad7b2b6 net: designware: Respect "bus mode" register contents on SW reset
"bus mode" register contains lots of fields and some of them don't
expect to be written with 0 (zero). So since we're only interested in
resetting MAC (which is done with setting the least significant bit of
this register with "0") I believe it's better to modify only 1 bit of
the register.

Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
Acked-by: Vipin Kumar <vipin.kumar@st.com>
Patch: 277864
2013-11-22 16:50:54 -06:00
Nobuhiro Iwamatsu
47ce889048 net: sh-eth: Add support R8A7791
R8A7791 has the same sh-ether IP core as other SH/rmobile.
This patch adds support of R8A7791.

Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
CC: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
CC: Joe Hershberger <joe.hershberger@gmail.com>
2013-11-22 16:50:54 -06:00
Heiko Schocher
dfcaa61c33 net, phy: fix AR8031 phy_mask
AR8035 driver will be never applied because of wrong mask for
AR8031 driver. Fix this.

Signed-off-by: Heiko Schocher <hs@denx.de>
Reported-by: Pavel Nakonechny <pavel.nakonechny@skitlab.ru>
Cc: Andy Fleming <afleming@freescale.com>
Cc: Joe Hershberger <joe.hershberger@gmail.com>
Patch: 276944
2013-11-22 16:50:54 -06:00
Thierry Reding
65a6691ed3 net: rtl8169: Add support for RTL8168evl/8111evl
This chip is compatible with other RTL8168 chips and can be found on the
NVIDIA Cardhu and Beaver boards.

Signed-off-by: Thierry Reding <treding@nvidia.com>
Patch: 276475
2013-11-22 16:50:53 -06:00
Thierry Reding
7a36b9c1ac net: rtl8169: Fix format string
currticks() is defined as get_timer(0), which returns an unsigned long,
so use %lu instead of %d to print the result.

Signed-off-by: Thierry Reding <treding@nvidia.com>
Patch: 276473
2013-11-22 16:50:53 -06:00
Stefano Babic
26b807c4f8 net: add support for extended registers to mdio command
Some phys (Micrel) have additional registers that can
be accessed using a special sequence. This patch allows
to use standard "mdio" command to accesss these registers.

Signed-off-by: Stefano Babic <sbabic@denx.de>
2013-11-22 16:50:52 -06:00
Stefano Babic
9ced16fefa net: add function to read/write extended registers in Micrel Phy
Signed-off-by: Stefano Babic <sbabic@denx.de>
2013-11-22 16:50:52 -06:00
Stefano Babic
b71841b978 net: add extended function to phy API
Some phys (Micrel) has extended registers that must be
accessed in a special way. Add pointers to the phy driver
structure to allow to use these functions with mdio command.

Signed-off-by: Stefano Babic <sbabic@denx.de>
2013-11-22 16:50:52 -06:00
Stefano Babic
e8194d58bd net: fix mask for phy Micrel KSZ9031
Signed-off-by: Stefano Babic <sbabic@denx.de>
2013-11-22 16:50:51 -06:00
Stefano Babic
71817a16f1 phy: add missing constants for Micrel KSZ9031
Signed-off-by: Stefano Babic <sbabic@denx.de>
2013-11-22 16:50:51 -06:00
Bhupesh Sharma
4220504767 net/phy: realtek: Fix the PHY ID mask to ensure the correct Realtek PHY is detected
The 'get_phy_driver' code in 'drivers/net/phy/phy.c' uses the following
method to determine which driver is to be loaded for a particular PHY
module:

list_for_each(entry, &phy_drivers) {
	drv = list_entry(entry, struct phy_driver, list);
	if ((drv->uid & drv->mask) == (phy_id & drv->mask))
		return drv;
}

This means that a drv->mask of 0xfffff0 will return incorrect phy driver
for the logic above, even if the drv->uid is anything other than
something ending with a 0x0.

For e.g. if the RTL8211E drv->uid is 0x1cc915 and drv->mask is 0xffffff
and the RTL8211B drv->uid is 0x1cc910 and drv->mask is 0xffffff0, then
the phy driver selected will always be RTL8211B even though the
underlying phy connected on the board is a 8211E module.

This patch fixes this issue.

Signed-off-by: Bhupesh Sharma <bhupesh.sharma@freescale.com>
2013-11-22 16:50:51 -06:00
Arpit Goel
e97a78cfed net: phy/vitesse: Add support for VSC8514 phy module
This patch adds support for VSC8514 PHY module which can be
found on Freescale's T1040RDB boards.

Signed-off-by: Arpit Goel <B44344@freescale.com>
Signed-off-by: Bhupesh Sharma <bhupesh.sharma@freescale.com>
2013-11-22 16:50:50 -06:00
Nobuhiro Iwamatsu
8707678cc4 net: sh-eth: Add support R8A7790
R8A7790 has the same sh-ether IP core as other SH/rmobile.
This patch adds support of R8A7790.

Signed-off-by: Hisashi Nakamura <hisashi.nakamura.ak@renesas.com>
Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
2013-11-22 16:50:50 -06:00
Nobuhiro Iwamatsu
92f0713408 net: sh-eth: Add invalidate cache control for rmobile (ARM SoC)
The sh-eth of rmobile needs to use invalidate_cache* function.
This patch adds invalidate_cache* function.

Signed-off-by: Hisashi Nakamura <hisashi.nakamura.ak@renesas.com>
Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
Patch: 268948
2013-11-22 16:50:49 -06:00
Nobuhiro Iwamatsu
f8b7507d41 net: sh-eth: Add control for padding size of packet descriptor
sh-eth can change the alignment size of a packet descriptor according to BUS
size. This patch adds this function.

Signed-off-by: Hisashi Nakamura <hisashi.nakamura.ak@renesas.com>
Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
2013-11-22 16:50:49 -06:00
Nobuhiro Iwamatsu
870cc23f07 net: sh-eth: Change cache API of SH
The cache API of SH was changed from dcache_wback_range to flush_dcache_range.
sh-eth uses dcache_wback_range. This patch changes to flush_dcache_range.

Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
2013-11-22 16:50:49 -06:00
Sascha Silbe
0611c6017c NET: mvgbe: avoid unused variable warning when used without phylib support
Avoid a recently introduced unused variable warning for boards that
use mvgbe but not phylib.

Signed-off-by: Sascha Silbe <t-uboot@infra-silbe.de>
Patch: 266334
2013-11-22 16:50:34 -06:00
Stephan Bauroth
57d33d4b40 net: trivial: Fix typos in mii field descriptions
Signed-off-by: Stephan Bauroth <stephan.bauroth@iav.de>
Patch: 265707
2013-11-22 16:50:04 -06:00
Shaohui Xie
f55a776cd0 phy: introduce structure fixed-link
fixed-link is used in kernel for PHY-less MAC, so introduce this
structure that U-boot can use it to fixup dtb dynamically.

Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
2013-11-22 12:43:36 -08:00
Shaohui Xie
70672a2959 powerpc/p4080: enable support for PCIe SATA
Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Acked-by: York Sun <yorksun@freescale.com>
2013-11-22 12:43:15 -08:00
Shengzhou Liu
626ee1e32e phylib: update atheros ar803x phy
As AR8031 and AR8033 have same PHY ID 0x4dd074, they use the
common driver. Currently AR8031_driver didn't work for AR8033,
hence updated it to have it work on AR8031/AR8033.

Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
2013-11-22 14:39:54 -06:00
rockly
f754f5dc6f net: tftp: Make sure timeout will not effect wrap offset
When the block 0 store to the memory of client and timeout at this
moment. Because of no ACK packet, the server will send block 0 again,
if this client reconnect to the server at this time,
TftpBlockWrapOffset will become larger than it should be.

Signed-off-by: Rockly <rocklygnome@gmail.com>
Patch: 264417
2013-11-22 14:39:31 -06:00
Albert ARIBAUD
d44a5f5128 Merge branch 'u-boot-microblaze/zynq' into 'u-boot-arm/master' 2013-11-22 10:19:35 +01:00
Simon Glass
ed072b96ef sandbox: Make map_to_sysmem() use a constant pointer
Very often a constant pointer is passed to this function, so we should
declare this, since map_to_sysmem() does not change the pointer.

Signed-off-by: Simon Glass <sjg@chromium.org>
2013-11-21 16:54:26 -07:00
Simon Glass
370b6c5c4d sandbox: Correct data sizes and printf() strings in fdtdec.c
There are a few wwrnings in this file when building for sandbox. Addresses
coming from the device tree need to be treated as ulong as elsewhere in
U-Boot and we must use map_sysmem() to convert to a pointer when needed.

Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Hung-ying Tyan <tyanh@chromium.org>
2013-11-21 16:54:26 -07:00
Simon Glass
0eb2acee39 sandbox: config: Don't use 64-bit physical memory
Sandbox uses an emulated memory map which is quite small. We don't need the
CONFIG_PHYS_64BIT option since we can address memory with a 32-bit offset
into our ram_buf.

Adjust the phys_addr_t and phys_size_t types accordingly.

Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Hung-ying Tyan <tyanh@chromium.org>
2013-11-21 16:54:26 -07:00
Simon Glass
cbe5cdfcd3 sandbox: Use system headers first for sandbox's os.c
This file must be compiled with system headers, even if U-Boot has headers
of the same name. The existing solution for this is good enough for libfdt,
but fails when we have headers like stdint.h in U-Boot.

Use -idirafter instead of -I, and remove the -nostdinc and other things
that we don't want for this file. The best way to do this is to keep a
copy of the original flags, rather than trying to filter them later.

Signed-off-by: Simon Glass <sjg@chromium.org>
2013-11-21 16:54:26 -07:00
Simon Glass
2a54d1599f sandbox: Use uint64_t instead of u64 for time
The uint64_t type is defined in linux/types.h, so is safer than u64, which
is not actually a Linux type.

Change-Id: Ifc9a369e6543250c49117b8d3cb3a676eee43e04
Signed-off-by: Simon Glass <sjg@chromium.org>
2013-11-21 16:54:25 -07:00
Stephen Warren
8426d8b089 buildman: make board selector argument a regex
A common use-case is to build all boards for a particular SoC. This can
be achieved by:

./tools/buildman/buildman -b mainline_dev tegra20

However, when the SoC is a member of a family of SoCs, and each SoC has
a different name, it would be even more useful to build all boards for
every SoC in that family. This currently isn't possible since buildman's
board selection command-line arguments are compared to board definitions
using pure string equality.

To enable this, compare using a regex match instead. This matches
MAKEALL's handling of command-line arguments. This enables:

(all Tegra)
./tools/buildman/buildman -b mainline_dev tegra

(all Tegra)
./tools/buildman/buildman -b mainline_dev '^tegra.*$'

(all Tegra20, Tegra30 boards, but not Tegra114)
./tools/buildman/buildman -b mainline_dev 'tegra[23]'

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Simon Glass <sjg@chromium.org>
2013-11-21 13:35:58 -07:00
Andreas Bießmann
61242ac5f9 buildman: fix README
This is a trivial fix for c'n'p error.

Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2013-11-21 13:35:58 -07:00
Albert ARIBAUD
5c8fdd91dc patman: add Commit-notes tag and section
Sometimes a commit should have notes enclosed with it rather
than withing the cover letter -- possibly even because there
is no cover letter. Add a 'Commit-notes' tag, similar to the
'Series-notes' one; lines between this tag and the next END
line are inserted in the patch right after the '---' commit
delimiter.

Change-Id: I01e99ae125607dc6dec08f3be8a5a0b37f0a483d
Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
Signed-off-by: Simon Glass <sjg@chromium.org>
(Updated README)
2013-11-21 13:35:51 -07:00
pekon gupta
2c17e6d1d9 am335x: fix GPMC config for NAND and NOR SPL boot
GPMC controller is common IP to interface with both NAND and NOR flash devices.
Also, it supports max 8 chip-selects, which can be independently connected to
any of the devices.
But ROM code expects the boot-device to be connected to only chip-select[0].
Thus to resolve conflict between NOR and NAND boot. This patch:
- combines NOR and NAND configs spread in board files to common gpmc_init()
- configures GPMC based on boot-mode selected for SPL boot.

Signed-off-by: Pekon Gupta <pekon@ti.com>
2013-11-21 13:33:41 -06:00
pekon gupta
3f719069c8 mtd: nand: omap: add CONFIG_NAND_OMAP_ECCSCHEME for selection of ecc-scheme
This patch adds new CONFIG_NAND_OMAP_ECCSCHEME, replacing other distributed
CONFIG_xx used for selecting NAND ecc-schemes.
This patch aims at solving following issues.

1) Currently ecc-scheme is tied to SoC platform, which prevents user to select
   other ecc-schemes also supported in hardware. like;
 - most of OMAP3 SoC platforms use only 1-bit Hamming ecc-scheme, inspite
   the fact that they can use higher ecc-schemes like 8-bit ecc-schemes with
   software based error detection (OMAP_ECC_BCH4_CODE_HW_DETECTION_SW).
 - most of AM33xx SoC plaforms use 8-bit BCH ecc-scheme for now, but hardware
   supports BCH16 ecc-scheme also.

2) Different platforms use different CONFIG_xx to select ecc-schemes, which
   adds confusion for user while migrating platforms.
 - *CONFIG_NAND_OMAP_ELM* which enables ELM hardware engine, selects only
    8-bit BCH ecc-scheme with h/w based error-correction (OMAP_ECC_BCH8_CODE_HW)
    whereas ELM hardware engine supports other ecc-schemes also like; BCH4,
    and BCH16 (in future).
 - *CONFIG_NAND_OMAP_BCH8* selects 8-bit BCH ecc-scheme with s/w based error
    correction (OMAP_ECC_BCH8_CODE_HW_DETECTION_SW).
 - *CONFIG_SPL_NAND_SOFTECC* selects 1-bit Hamming ecc-scheme using s/w library

Thus adding new *CONFIG_NAND_OMAP_ECCSCHEME* de-couples ecc-scheme dependency
on SoC platform and NAND driver. And user can select ecc-scheme independently
foreach board.
However, selection some hardware based ecc-schemes (OMAP_ECC_BCHx_CODE_HW) still
depends on presence of ELM hardware engine on SoC. (Refer doc/README.nand)

Signed-off-by: Pekon Gupta <pekon@ti.com>
2013-11-21 13:33:41 -06:00
pekon gupta
d016dc42ce mtd: nand: omap: enable BCH ECC scheme using ELM for generic platform
BCH8_ECC scheme implemented in omap_gpmc.c driver has following favours
+-----------------------------------+-----------------+-----------------+
|ECC Scheme                         | ECC Calculation | Error Detection |
+-----------------------------------+-----------------+-----------------+
|OMAP_ECC_BCH8_CODE_HW              |GPMC             |ELM H/W engine   |
|OMAP_ECC_BCH8_CODE_HW_DETECTION_SW |GPMC             |S/W BCH library  |
+-----------------------------------+-----------------+-----------------+

Current implementation limits the BCH8_CODE_HW only for AM33xx device family.
(using CONFIG_AM33XX). However, other SoC families (like TI81xx) also have
ELM hardware module, and can support ECC error detection using ELM.

This patch
- removes CONFIG_AM33xx
	Thus this driver can be reused by all devices having ELM h/w engine.
- adds omap_select_ecc_scheme()
	A common function to handle ecc-scheme related configurations. This
	can be used both during device-probe and via user-space u-boot commads
	to change ecc-scheme. During device probe ecc-scheme is selected based
	on CONFIG_NAND_OMAP_ELM or CONFIG_NAND_OMAP_BCH8
- enables CONFIG_BCH
	S/W library (lib/bch.c) required by OMAP_ECC_BCHx_CODE_HW_DETECTION_SW
  	is enabled by CONFIG_BCH.
- enables CONFIG_SYS_NAND_ONFI_DETECTION
	for auto-detection of ONFI compliant NAND devices
- updates following README doc
	doc/README.nand
	board/ti/am335x/README
	doc/README.omap3

Signed-off-by: Pekon Gupta <pekon@ti.com>
[scottwood@freescale.com: fixed unused variable warning]
Signed-off-by: Scott Wood <scottwood@freescale.com>
2013-11-21 13:33:41 -06:00
pekon gupta
beba5f04f2 mtd: nand: omap: make am33xx/elm.c as common driver for all OMAPx and AMxxxx platforms
ELM hardware engine which is used for ECC error detection, is present on all
latest OMAP SoC (like OMAP4xxx, OMAP5xxx, DRA7xxx, AM33xx, AM43xx). Thus ELM
driver should be moved to common drivers/mtd/nand/ folder so that all SoC
having on-chip ELM hardware engine can re-use it.
This patch has following changes:
- mv arch/arm/include/asm/arch-am33xx/elm.h arch/arm/include/asm/omap_elm.h
- mv arch/arm/cpu/armv7/am33xx/elm.c drivers/mtd/nand/omap_elm.c
- update Makefiles
- update #include <asm/elm.h>
- add CONFIG_NAND_OMAP_ELM to compile driver/mtd/nand/omap_elm.c
	and include in all board configs using AM33xx SoC platform.

Signed-off-by: Pekon Gupta <pekon@ti.com>
2013-11-21 13:33:41 -06:00
Wu, Josh
c0dc3dec69 mtd: atmel_nand: use dev_xxx instead of printk
Signed-off-by: Josh Wu <josh.wu@atmel.com>
2013-11-21 13:33:41 -06:00
Wu, Josh
c55cc573ea mtd: atmel_nand: don't print bit correction message in driver
Since for some MLC nand, bit errors happened too often. Just disable it
to avoid noise

Signed-off-by: Josh Wu <josh.wu@atmel.com>
2013-11-21 13:33:41 -06:00
Wu, Josh
d02a60a16e sama5d3xek: support larger than 4G nand flash
Signed-off-by: Josh Wu <josh.wu@atmel.com>
2013-11-21 13:33:41 -06:00
Wu, Josh
16dddef605 mtd: atmel_nand: enable PMECC support for 8k bytes page NAND flash
increase the delay to 75us to support the 8k bytes page nand flash

Signed-off-by: Josh Wu <josh.wu@atmel.com>
2013-11-21 13:33:41 -06:00
Prabhakar Kushwaha
affd520f8c board/c29xpcie: Add support of 8K page size NAND flash
Defines constants required to support 8K page size NAND flash.

Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
2013-11-21 13:33:40 -06:00
Prabhakar Kushwaha
71220f80e7 mtd/ifc: Add support of 8K page size NAND flash
Current IFC driver supports till 4K page size NAND flash.
Add support of 8K NAND flash
  - Program Spare region size in csor_ext
  - Add nand_ecclayout for 4 bit & 8 bit ecc
  - Defines constants
  - Add support of 8K NAND boot.

Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
CC: Liu Po <po.liu@freescale.com>
2013-11-21 13:33:40 -06:00
Prabhakar Kushwaha
68ec9c85a9 mtd: move & update nand_ecclayout structure (plus board changes)
nand_ecclayout is present in mtd.h at Linux.
Move this structure to mtd.h to comply with Linux.

Also, increase the ecc placement locations to 640 to suport device having
writesize/oobsize of 8KB/640B. This means that the maximum oobsize has gone
up to 640 bytes and consequently the maximum ecc placement locations have
also gone up to 640.

Changes from Prabhabkar's version (squashed into one patch to preserve
bisectability):
 - Added _LARGE to MTD_MAX_*_ENTRIES

   This makes the names match current Linux source, and resolves
   a conflict between
   http://patchwork.ozlabs.org/patch/280488/
   and
   http://patchwork.ozlabs.org/patch/284513/

   The former was posted first and is closer to matching Linux, but
   unlike Linux it does not add _LARGE to the names.  The second adds
   _LARGE to one of the names, and depends on it in a subsequent patch
   (http://patchwork.ozlabs.org/patch/284512/).

 - Made max oobfree/eccpos configurable, and used this on tricorder,
   alpr, ASH405, T4160QDS, and T4240QDS (these boards failed to build
   for me without doing so, due to a size increase).

   On tricorder SPL, this saves 2576 bytes (and makes the SPL build
   again) versus the new default of 640 eccpos and 32 oobfree, and
   saves 336 bytes versus the old default of 128 eccpos and 8 oobfree.

Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
CC: Vipin Kumar <vipin.kumar@st.com>
[scottwood@freescale.com: changes as described above]
Signed-off-by: Scott Wood <scottwood@freescale.com>
Cc: Thomas Weber <weber@corscience.de>
Cc: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
Cc: Stefan Roese <sr@denx.de>
Cc: York Sun <yorksun@freescale.com>
Cc: Tom Rini <trini@ti.com>
Reviewed-by: Stefan Roese <sr@denx.de>
2013-11-21 13:32:43 -06:00
Tom Rini
c2e5e802ec Merge branch 'master' of git://git.denx.de/u-boot-mips 2013-11-17 14:11:34 -05:00
Masahiro Yamada
4678d74256 fs: descend into sub directories when it is necessary
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2013-11-17 14:11:34 -05:00