Commit graph

10 commits

Author SHA1 Message Date
Wolfgang Denk
00c60f9131 Minor Coding Style Cleanup.
Signed-off-by: Wolfgang Denk <wd@denx.de>
2012-07-22 21:58:26 +02:00
Wolfgang Denk
3fe63839f3 Minor Coding Style cleanup
Signed-off-by: Wolfgang Denk <wd@denx.de>
2012-07-10 09:18:33 +02:00
York Sun
48f6a5c348 powerpc/mpc85xx: Ignore E bit for SVR_SOC_VER()
We don't care E bit of SVR in most cases. Clear E bit for SVR_SOC_VER().
This will simplify the coding. Use IS_E_PROCESSOR() to identify SoC with
encryption. Remove all _E entries from SVR list and CPU list.

Signed-off-by: York Sun <yorksun@freescale.com>
2012-07-06 17:30:33 -05:00
Shengzhou Liu
d3de823e54 powerpc/p1010rdb: add readme document for p1010rdb
Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
2012-07-06 17:30:31 -05:00
Shengzhou Liu
487e8abbaa powerpc/p1010rdb: update mux config of p1010rdb board
On p1010rdb some signals are muxed for tdm/can/uart/flash.
If we don't set fsl_p1010mux:tdm_can to "can" or "tdm" explicitly,
defaultly we keep spi chip selection to spi-flash instead of to
tdm/slic and disable uart1 when not using flexcan, as well disable sdhc.

Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
2012-07-06 17:30:29 -05:00
Timur Tabi
5d065c3e10 powerpc/85xx: don't display address map size (32-bit vs. 36-bit) during boot
Most 85xx boards can be built as a 32-bit or a 36-bit.  Current code sometimes
displays which of these is actually built, but it's inconsistent.  This is
especially problematic since the "default" build for a given 85xx board can
be either one, so if you don't see a message, you can't always know which
size is being used.  Not only that, but each board includes code that displays
the message, so there is duplication.

The 'bdinfo' command has been updated to display this information, so
we don't need to display it at boot time.  The board-specific code is
deleted.

Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-04-24 23:58:34 -05:00
York Sun
1ba62f1017 powerpc/mpc8xxx: Fix CONFIG_DDR_RAW_TIMING for two boards
P1010RDB and p1_pc_rdb_pc has incorrect configuration for
CONFIG_DDR_RAW_TIMING. It should be CONFIG_SYS_DDR_RAW_TIMING.
Incorrect setting causes DDR failure in case of SPD absent.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-04-24 23:58:30 -05:00
Ramneek Mehresh
a311db6941 powerpc/85xx: Make inclusion of USB device fixup conditional
Include call to usb device-fixup only when CONFIG_HAS_FSL_DR_USB is
defined for the platform - P1020RDB, P1010RDB, P1020-PC

Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-11-08 08:36:04 -06:00
Mike Frysinger
464c79207c punt unused clean/distclean targets
The top level Makefile does not do any recursion into subdirs when
cleaning, so these clean/distclean targets in random arch/board dirs
never get used.  Punt them all.

MAKEALL didn't report any errors related to this that I could see.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-10-15 22:20:36 +02:00
Poonam Aggrwal
49249e137d powerpc/85xx: Add basic support for P1010RDB
Boot methods supported: NOR Flash, SPI Flash and SDCARD
This patch adds the following basic interfaces:
DDR3, eTSEC, DUART, I2C, SD/MMC, USB, SATA, PCIe, NOR Flash, SPI Flash.

P1010RDB Overview
-----------------
1Gbyte DDR3 (on board DDR)
Local Bus (IFC):
	32Mbyte 16bit NOR flash
	32Mbyte SLC NAND Flash
	64KB CPLD device(GPCM interface)
SPI Flash:
	128 Mbit SPI Flash memory
SD/MMC:
	connector to interface with the SD memory card
SATA:
	1 internal SATA connect to 2.5. 160G SATA2 HDD
	1 eSATA connector to rear panel
USB 2.0:
	x1 USB 2.0 port: connected via a UTMI PHY to Mini-AB interface.
	x1 USB 2.0 port: directly connected to Mini-AB interface Ethernet
eTSEC:
	eTSEC1: Connected to RGMII PHY VSC8641XKO
	eTSEC2: Connected to SGMII PHY VSC8221
	eTSEC3: Connected to SGMII PHY VSC8221
eCAN:
	Two DB-9 female connectors for Field bus interface
UART:
	supports two UARTs up to 115200 bps for console
TDM:
	2 FXS ports connected via an external SLIC to the TDM interface.
SLIC:
	SPI SLIC
I2C:
	Serial EEprom
	Real time clock
	256 Kbit M24256 I2C EEPROM
PCIe:
	PCIe and mPCIe connectors.

Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Dipen Dudhat <dipen.dudhat@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com>
Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@freescale.com>
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-09-29 19:01:04 -05:00