Commit graph

7 commits

Author SHA1 Message Date
Fabio Estevam
41c881c0ca mx53: Turn off child clocks before reconfigure perclk_root
In addition to ensuring that PERCLK remains at least 2.5 times slower
than the AHB clock, certain steps need to be followed to ensure robust
operation of PERCLK when reconfiguring the PERCLK clock source.

To properly configure the PERCLK clock source, the following steps are
required:

1.In the CCGR registers, gate the clocks to all PERCLK-dependent
  modules.
2.Select the desired input clock for the PERCLK root clock (to be either
  source from the peripherals main source clock or the
  lp_apm clock source). Refer to the CMCBR register,  perclk_lp_apm_sel bit.
3.Configure the perclk_pred1, perclk_pred2, and perclk_podf dividers
  to the desired setting.  Refer to the CBCDR register for details.
4.In the CCGR registers, enable the desired clocks for the
  PERCLK-dependent module clocks.

If these steps aren't followed, GPT timer may stop and the kernel stops
at "Calibrating delay loop".

Signed-off-by: Terry Lv <r65388@freescale.com>
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2011-11-04 22:06:37 +01:00
Stefano Babic
a4814a69d3 Makefile : fix generation of cpu related asm-offsets.h
commit 0edf8b5b2f breaks
building on a different directory with the O= parameter.
The patch wil fix this issue, generating always asm-offsets.h before
the other targets.

Signed-off-by: Stefano Babic <sbabic@denx.de>
CC: Matthias Weisser <weisserm@arcor.de>
CC: Wolfgang Denk <wd@denx.de>
2011-09-07 21:41:27 +02:00
David Jander
9db1bfa110 ARM: MX51: PLL errata workaround
This is a port of the official PLL errata workaround from Freescale to
mainline u-boot.
The PLL's in the i.MX51 processor can go out of lock due to a metastable
condition in an analog flip-flop when used at high frequencies.
This workaround implements an undocumented feature in the PLL (dither
mode), which causes the effect of this failure to be much lower (in terms
of frequency deviation), avoiding system failure, or at least decreasing
the likelihood of system failure.

Signed-off-by: David Jander <david@protonic.nl>
2011-09-04 11:36:11 +02:00
David Jander
6e25b6ce5d ARM: MX5: Fix broken leftover TO-2 errata workaround
This check was broken. r3 does not contain the silicon revision anymore, so
we need to reload it. Also, this errata only applies to i.MX51.

Signed-off-by: David Jander <david@protonic.nl>
Acked-by: Stefano Babic <sbabic@denx.de>
2011-07-18 14:41:48 +02:00
Liu Hui-R64343
595f3e5645 MX5: Add initial support for MX53 processor
Add initial support for Freescale MX53 processor,

- Add the iomux support and the pin definition,
- Add the regs definition, clean up some unused def from mx51,
- Add the low level init support, make use the freq input of setup_pll macro

Signed-off-by: Jason Liu  <r64343@freescale.com>
2011-02-02 00:54:41 +01:00
Jason Liu
65e62d6941 MX5: Remove dead code with ENABLE_IMPRECISE_ABORT
This code section is dead due to we never define
ENABLE_IMPRECISE_ABORT for MX5

Signed-off-by: Jason Liu <r64343@freescale.com>
2010-10-19 12:28:08 +02:00
Jason Liu
ff9f475d5d MX5: rename mx51 to mx5
Rename mx51 to mx5 in order to support more mx51
like-style SOCs such as MX53 and the followings.

Signed-off-by: Jason Liu <r64343@freescale.com>
2010-10-18 10:43:19 +02:00
Renamed from arch/arm/cpu/armv7/mx51/lowlevel_init.S (Browse further)