Commit graph

88117 commits

Author SHA1 Message Date
Bin Meng
17cd80237b video: kconfig: Fix wrong text for the PCI default FB size
There is an example in the VIDEO_PCI_DEFAULT_FB_SIZE help text to
tell people how to calculate its value but the resolution given
does not match the value. Fix it.

Signed-off-by: Bin Meng <bmeng@tinylab.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
2023-08-01 13:33:05 +02:00
Bin Meng
e1b46977de video: bochs: Remove the x86 dependency
Now that the driver is legacy free, remove the x86 dependency so
that it can be used on non-x86 architectures.

Signed-off-by: Bin Meng <bmeng@tinylab.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>  # qemu-x86_64
2023-08-01 13:32:25 +02:00
Bin Meng
ffe1c8379e video: bochs: Avoid using IO instructions to access VGA IO port
At present the driver uses IO instructions to access the legacy
VGA IO ports, which unfortunately limits the driver to work only
on x86. It turns out the IO instruction is not necessary as Bochs
VGA card remaps the legacy VGA IO ports (0x3c0 -> 0x3df) to its
memory mapped register space from offset 0x400.

Update the driver to use MMIO access for VGA IO port.

Signed-off-by: Bin Meng <bmeng@tinylab.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>  # qemu-x86_64
2023-08-01 13:31:29 +02:00
Bin Meng
caae795a1c video: bochs: Drop the useless argument of bochs_vga_write()
bochs_vga_write() takes 'index' as one argument, but never uses it.

While we are here, use macros instead of magic numbers for the
VGA IO port register name and value.

Signed-off-by: Bin Meng <bmeng@tinylab.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>  # qemu-x86_64
2023-08-01 13:30:41 +02:00
Bin Meng
5ee029a190 video: bochs: Drop inclusion of <asm/mtrr.h>
The driver does not call any MTRR APIs.

Signed-off-by: Bin Meng <bmeng@tinylab.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>  # qemu-x86_64
2023-08-01 13:29:14 +02:00
Bin Meng
08ece5b3ec dm: video: Cosmetic style fix
Some coding convention fixes for video_post_bind().

Signed-off-by: Bin Meng <bmeng@tinylab.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>  # qemu-x86_64
2023-08-01 13:28:59 +02:00
Simon Glass
db971a7587 x86: Add a little more info to cbsysinfo
Show the number of records in the table and the total table size in
bytes.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2023-08-01 10:08:49 +08:00
Simon Glass
d560f7cae0 x86: Return mtrr_add_request() to its old purpose
This function used to be for adding a list of requests to be actioned on
relocation. Revert it back to this purpose, to avoid problems with boards
which need control of their MTRRs (i.e. those which don't use FSP).

The mtrr_set_next_var() function is available when the next free
variable-MTRR must be set, so this can be used instead.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Fixes: 3bcd6cf89e ("x86: mtrr: Skip MSRs that were already programmed..")
Fixes: 596bd0589a ("x86: mtrr: Do not clear the unused ones..")
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2023-08-01 10:06:46 +08:00
Bin Meng
bff002d45b video: vesa: Use mtrr_set_next_var() for graphics memory
At present this uses mtrr_add_request() & mtrr_commit() combination
to program the MTRR for graphics memory. This usage has two major
issues as below:

- mtrr_commit() will re-initialize all MTRR registers from index 0,
  using the settings previously added by mtrr_add_request() and saved
  in gd->arch.mtrr_req[], which won't cause any issue but is unnecessary
- The way such combination works is based on the assumption that U-Boot
  has full control with MTRR programming (e.g.: U-Boot without any blob
  that does all low-level initialization on its own, or using FSP2 which
  does not touch MTRR), but this is not the case with FSP. FSP programs
  some MTRRs during its execution but U-Boot does not have the settings
  saved in gd->arch.mtrr_req[] and when doing mtrr_commit() it will
  corrupt what was already programmed previously.

Correct this to use mtrr_set_next_var() instead.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2023-08-01 10:06:46 +08:00
Bin Meng
0f497b2b8c video: ivybridge: Use mtrr_set_next_var() for graphics memory
At present this uses mtrr_add_request() & mtrr_commit() combination
to program the MTRR for graphics memory. This usage has two major
issues as below:

- mtrr_commit() will re-initialize all MTRR registers from index 0,
  using the settings previously added by mtrr_add_request() and saved
  in gd->arch.mtrr_req[], which won't cause any issue but is unnecessary
- The way such combination works is based on the assumption that U-Boot
  has full control with MTRR programming (e.g.: U-Boot without any blob
  that does all low-level initialization on its own, or using FSP2 which
  does not touch MTRR), but this is not the case with FSP. FSP programs
  some MTRRs during its execution but U-Boot does not have the settings
  saved in gd->arch.mtrr_req[] and when doing mtrr_commit() it will
  corrupt what was already programmed previously.

Correct this to use mtrr_set_next_var() instead.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2023-08-01 10:06:46 +08:00
Bin Meng
b5126f26d0 video: broadwell: Use mtrr_set_next_var() for graphics memory
At present this uses mtrr_add_request() & mtrr_commit() combination
to program the MTRR for graphics memory. This usage has two major
issues as below:

- mtrr_commit() will re-initialize all MTRR registers from index 0,
  using the settings previously added by mtrr_add_request() and saved
  in gd->arch.mtrr_req[], which won't cause any issue but is unnecessary
- The way such combination works is based on the assumption that U-Boot
  has full control with MTRR programming (e.g.: U-Boot without any blob
  that does all low-level initialization on its own, or using FSP2 which
  does not touch MTRR), but this is not the case with FSP. FSP programs
  some MTRRs during its execution but U-Boot does not have the settings
  saved in gd->arch.mtrr_req[] and when doing mtrr_commit() it will
  corrupt what was already programmed previously.

Correct this to use mtrr_set_next_var() instead.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2023-08-01 10:06:46 +08:00
Bin Meng
3dfa411501 x86: fsp: Use mtrr_set_next_var() for graphics memory
At present this uses mtrr_add_request() & mtrr_commit() combination
to program the MTRR for graphics memory. This usage has two major
issues as below:

- mtrr_commit() will re-initialize all MTRR registers from index 0,
  using the settings previously added by mtrr_add_request() and saved
  in gd->arch.mtrr_req[], which won't cause any issue but is unnecessary
- The way such combination works is based on the assumption that U-Boot
  has full control with MTRR programming (e.g.: U-Boot without any blob
  that does all low-level initialization on its own, or using FSP2 which
  does not touch MTRR), but this is not the case with FSP. FSP programs
  some MTRRs during its execution but U-Boot does not have the settings
  saved in gd->arch.mtrr_req[] and when doing mtrr_commit() it will
  corrupt what was already programmed previously.

Correct this to use mtrr_set_next_var() instead.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2023-08-01 10:06:46 +08:00
Bin Meng
41fbb34469 x86: Change testing logic of mtrr commit
On Coral U-Boot SPL programs some MTRRs and FSPv2 in U-Boot proper
needs to program MTRRs too. With current testing logic of mtrr
commit in init_cache_f_r(), the mtrr commit is skipped which won't
work as the queued mtrr requests include setup for DRAM regions.

Change the logic to allow such configuration.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Tweak to put back CONFIG_FSP_VERSION2 at top:
Signed-off-by: Simon Glass <sjg@chromium.org>
2023-08-01 10:06:46 +08:00
Tom Rini
4e619e8d4f Merge tag 'u-boot-rockchip-20230731' of https://source.denx.de/u-boot/custodians/u-boot-rockchip
- Update dwc3 generic driver and update support for rk3568/rk3328;
- Add boards:
        rk3566: Pine64 Quartz64-A/B, SOQuartz on Model A/Blade/CM4-IO
        rk3568: Radxa E25 Carrier Board
        rk3588: Radxa ROCK5A
- Fixes and updates for chromebook veryon/jerry/speedy;
- SPI support fixes for rk3399/rk3568/rk3588;
- rk3588 usbdp phy support;
- dts and config updates for different boards;
2023-07-31 11:33:51 -04:00
Jonas Karlman
1f54f71b18 board: rockchip: Add Radxa E25 Carrier Board
Radxa E25 is a network application carrier board for the Radxa CM3I SoM
with a RK3568 SoC. It features dual 2.5G ethernet, mini PCIe, M.2 B Key,
USB3, eMMC, SD, nano SIM card slot and a 26-pin GPIO header.

Features tested on a Radxa E25 v1.4:
- SD-card boot
- eMMC boot
- USB host
- PCIe/Ethernet adapters is detected
- SATA

Device tree is imported from linux next-20230728.

Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Tested-by: FUKAUMI Naoki <naoki@radxa.com>
2023-07-31 20:34:32 +08:00
Jagan Teki
b6fd3c63f4 configs: rockchip: Enable USB2PHY for RK3328 boards
Enable USB2PHY for all RK3328 boards.

=> usb start
starting USB...
Bus usb@ff5c0000: USB EHCI 1.00
Bus usb@ff5d0000: USB OHCI 1.0
Bus usb@ff600000: generic_phy_get_bulk : no phys property
Register 2000140 NbrPorts 2
Starting the controller
USB XHCI 1.10
Bus usb@ff580000: USB DWC2
scanning bus usb@ff5c0000 for devices... 2 USB Device(s) found
scanning bus usb@ff5d0000 for devices... 1 USB Device(s) found
scanning bus usb@ff600000 for devices... 2 USB Device(s) found
scanning bus usb@ff580000 for devices... 2 USB Device(s) found
       scanning usb for storage devices... 2 Storage Device(s) found
=> usb tree
USB device tree:
  1  Hub (480 Mb/s, 0mA)
  |  u-boot EHCI Host Controller
  |
  +-2  Mass Storage (480 Mb/s, 500mA)
       TS-RDF5A Transcend 000000000009

  1  Hub (12 Mb/s, 0mA)
      U-Boot Root Hub

  1  Hub (5 Gb/s, 0mA)
  |  U-Boot XHCI Host Controller
  |
  +-2  Mass Storage (5 Gb/s, 224mA)
       SanDisk Dual Drive 040130e3ee554b7078843f4eb331646

  1  Hub (480 Mb/s, 0mA)
  |   U-Boot Root Hub
  |
  +-2  Human Interface (12 Mb/s, 98mA)
       Logitech USB Receiver

=> dm tree -s
 Class     Index  Probed  Driver                Name
-----------------------------------------------------------
 syscon        1  [ + ]   syscon                |-- syscon@ff450000
 phy           0  [ + ]   rockchip_usb2phy      |   `-- usb2phy@100
 clk           2  [ + ]   rockchip_usb2phy_clo  |       |-- usb480m_phy
 phy           1  [ + ]   rockchip_usb2phy_por  |       |-- otg-port
 phy           2  [ + ]   rockchip_usb2phy_por  |       `-- host-port
 sysinfo       0  [ + ]   sysinfo_smbios        |-- smbios
 usb           3  [ + ]   dwc2_usb              |-- usb@ff580000
 usb_hub       3  [ + ]   usb_hub               |   `-- usb_hub
 usb_dev_ge    0  [ + ]   usb_dev_generic_drv   |       `-- generic_bus_3_dev_2
 usb           0  [ + ]   ehci_generic          |-- usb@ff5c0000
 usb_hub       0  [ + ]   usb_hub               |   `-- usb_hub
 usb_mass_s    0  [ + ]   usb_mass_storage      |       `-- usb_mass_storage
 blk           2  [ + ]   usb_storage_blk       |           |-- usb_mass_storage.lun0
 partition     4  [ + ]   blk_partition         |           |   |-- usb_mass_storage.lun0:1
 partition     5  [ + ]   blk_partition         |           |   `-- usb_mass_storage.lun0:2
 bootdev       3  [   ]   usb_bootdev           |           `-- usb_mass_storage.lun0.bootdev
 usb           1  [ + ]   ohci_generic          `-- usb@ff5d0000
 usb_hub       1  [ + ]   usb_hub                   `-- usb_hub

Cc: Tianling Shen <cnsztl@gmail.com>
Cc: David Bauer <mail@david-bauer.net>
Cc: Loic Devulder <ldevulder@suse.com>
Cc: Chen-Yu Tsai <wens@csie.org>
Cc: Banglang Huang <banglang.huang@foxmail.com>
Cc: Matwey V. Kornilov <matwey.kornilov@gmail.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-07-31 20:33:18 +08:00
Jagan Teki
c016525858 clk: rockchip: rk3328: Handle usb480m phy clock
Handle USB480M clock ID in set_rate() and set_parent()
to allow the dt assigned-clocks and assigned-clock-parents
work on rk3328.dtsi

Cc: Lukasz Majewski <lukma@denx.de>
Cc: Sean Anderson <seanga2@gmail.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-07-31 20:33:18 +08:00
Jagan Teki
9aa93d8403 phy: rockchip-inno-usb2: Add USB2 PHY for RK3328
USB2.0 Host and OTG controllers in RK3328 are using USB2PHY.

Add support for it.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Xavier Drudis Ferran <xdrudis@tinet.cat>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-07-31 20:33:18 +08:00
Jagan Teki
5d334b70cc configs: Enable DWC3 USB 3.0 on RK3328 boards
Enable USB 3.0 in all RK3328 boards.

=> usb start
starting USB...
Bus usb@ff5c0000: ehci_generic usb@ff5c0000: Failed to get clocks (ret=-19)
Port not available.
Bus usb@ff5d0000: USB OHCI 1.0
Bus usb@ff600000: Register 2000140 NbrPorts 2
Starting the controller
USB XHCI 1.10
Bus usb@ff580000: 1 USB Device(s) found
       scanning usb for storage devices... 1 Storage Device(s) found
=> usb tree
USB device tree:
  1  Hub (12 Mb/s, 0mA)
      U-Boot Root Hub

  1  Hub (5 Gb/s, 0mA)
  |  U-Boot XHCI Host Controller
  |
  +-2  Mass Storage (5 Gb/s, 224mA)
       SanDisk Dual Drive 040130e3ee554b7078843f4eb331646

  1  Hub (480 Mb/s, 0mA)
      U-Boot Root Hub

Cc: Tianling Shen <cnsztl@gmail.com>
Cc: David Bauer <mail@david-bauer.net>
Cc: Loic Devulder <ldevulder@suse.com>
Cc: Chen-Yu Tsai <wens@csie.org>
Cc: Banglang Huang <banglang.huang@foxmail.com>
Cc: Matwey V. Kornilov <matwey.kornilov@gmail.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-07-31 20:33:18 +08:00
Jagan Teki
185571b6ec usb: dwc3-generic: Restrict single ctrl node for RK3328
Like Rockchip RK3568, the RK3328 also have single node to
represent the glue and ctrl for USB 3.0.

So, use the driver data to use single ctrl for RK3328 DWC3.

Reviewed-by: Marek Vasut <marex@denx.de>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-07-31 20:33:18 +08:00
Jagan Teki
559911ff2e configs: Drop unused XHCI_DWC3 for RK3328 boards
Driver support for rk3328 is not supported so drop this
unused XHCI_DWC3.

Cc: Tianling Shen <cnsztl@gmail.com>
Cc: David Bauer <mail@david-bauer.net>
Cc: Loic Devulder <ldevulder@suse.com>
Cc: Chen-Yu Tsai <wens@csie.org>
Cc: Banglang Huang <banglang.huang@foxmail.com>
Cc: Matwey V. Kornilov <matwey.kornilov@gmail.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-07-31 20:33:18 +08:00
Jagan Teki
b71f74eab4 arm64: dts: rockchip: Drop unused rk3328-xhci node
rk3328-xhci has been added due to the fact that the upstream
dwc3 is unsupported. Moreover, the driver for rk3328-xhci is
not added to the code tree.

By considering these facts and unsupported rk3328-xhci this
patch is dropping all related code from DT. However, the DWC3
is fixed now in dwc3-generic and RK3328 USB 3.0 is functional
in upcoming patches.

Let's drop it.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-07-31 20:33:18 +08:00
Jonas Karlman
fea7a29cc8 power: regulator: rk8xx: Add 500us delay after LDO regulator is enabled
A quick power cycle of a LDO regulator during dw-mmc signal voltage
change has shown that SD-card does not always get recognized.

Linux driver use an enable_time of 400us for LDO regulators. Apply a
500us delay when a LDO regulator is enabled to fix possible issues.

Fixes: 94afc1cb46 ("power: regulator: rk8xx: update the driver for rk808 and rk818")
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: elaine.zhang<elaine.zhang@rock-chips.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-07-31 20:33:18 +08:00
Chris Packham
5c1c6b7306 arm: mvebu: x240: Use i2c-gpio instead of built in controller
There is an Errata with the built-in I2C controller where various I2C
hardware errors cause a complete lockup of the CPU (which eventually
results in an watchdog reset).

Put the I2C MPP pins into GPIO mode and use the i2c-gpio driver instead.
This uses a bit-banged implementation of an I2C controller and avoids
triggering the Errata.

Signed-off-by: Chris Packham <judge.packham@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
2023-07-31 13:50:57 +02:00
Chris Packham
414236b887 i2c: i2c-gpio: Correctly handle new {sda, scl}-gpios bindings
gpio_request_list_by_name() returns the number of gpios requested.
Notably it swallows the underlying -ENOENT when the "gpios" property
does not exist.

Update the i2c-gpio driver to check for ret == 0 before trying the new
sda-gpios/scl-gpios properties.

Signed-off-by: Chris Packham <judge.packham@gmail.com>
2023-07-31 13:50:57 +02:00
Eugen Hristev
b8fc65473a board: rockchip: add Radxa ROCK5A Rk3588 board
ROCK 5A is a Rockchip RK3588S based SBC (Single Board Computer) by Radxa.

There are tree variants depending on the DRAM size : 4G, 8G and 16G.

Specifications:

     Rockchip Rk3588S SoC
     4x ARM Cortex-A76, 4x ARM Cortex-A55
     4/8/16GB memory LPDDR4x
     Mali G610MC4 GPU
     MIPI CSI 2 multiple lanes connector
     4-lane MIPI DSI connector
     Audio – 3.5mm earphone jack
     eMMC module connector
     uSD slot (up to 128GB)
     2x USB 2.0, 2x USB 3.0
     2x micro HDMI 2.1 ports, one up to 8Kp60, the other up to 4Kp60
     Gigabit Ethernet RJ45 with optional PoE support
     40-pin IO header including UART, SPI, I2C and 5V DC power in
     USB PD over USB Type-C
     Size: 85mm x 56mm (Raspberry Pi 4 form factor)

Kernel commits:
d1824cf95799 ("arm64: dts: rockchip: Add rock-5a board")
991f136c9f8d ("arm64: dts: rockchip: Update sdhci alias for rock-5a")
304c8a759953 ("arm64: dts: rockchip: Remove empty line from rock-5a")
cda0c2ea65a0 ("arm64: dts: rockchip: Fix RX delay for ethernet phy on rk3588s-rock5a")

Signed-off-by: Eugen Hristev <eugen.hristev@collabora.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-07-31 17:34:43 +08:00
Eugen Hristev
7031224000 ARM: dts: rockchip: rk3588: Move bootph-all props to common file
Move bootph-all prop to common SoC dt file, because they are typically used
by multiple boards.
Unreferenced nodes are removed from the SPL device tree during a
normal build.

Suggested-by: Jonas Karlman <jonas@kwiboo.se>
Signed-off-by: Eugen Hristev <eugen.hristev@collabora.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-07-31 17:34:43 +08:00
Jonas Karlman
def50c66cc rockchip: rk3568-rock-3a: Fix pcie2x1 and pcie3x2 pinctrl override
The pcie pinctrl override added in the commit a76aa6ffa6 ("rockchip:
rk3568-rock-3a: Enable PCIe and NVMe support") is causing a pinmux issue
on linux when using a EFI boot flow.

The pcie reset-gpios must however be configured with gpio function, or
the device will freeze running pci enum and nothing is connected.

Adjust the pinctrl override in u-boot.dtsi to fix this issue. PCIe/NVMe
continues to work in both U-Boot and linux after this change.

Also revert disable of sdmmc2 and uart1 to fix use of wifi in linux when
using a EFI boot flow.

Fixes: a76aa6ffa6 ("rockchip: rk3568-rock-3a: Enable PCIe and NVMe support")
Fixes: 073d911ae6 ("rockchip: rk3568-rock-3a: Sync device tree from linux")
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
2023-07-31 17:34:43 +08:00
Jonas Karlman
747f9f2663 rockchip: rk3588-rock-5b: Fix SPI Flash alias
The commit fd6e425be2 ("rockchip: rk3588-rock-5b: Enable boot from SPI
NOR flash") enabled SPI flash support by adding a spi0 alias.

Correct this by adding spi0-spi5 aliases in rk3588s-u-boot.dtsi and
SF_DEFAULT_BUS=5 and SPL_DM_SEQ_ALIAS=y in defconfig. Also enabled
support for parsing and auto discovery of parameters, SFDP.

Fixes: fd6e425be2 ("rockchip: rk3588-rock-5b: Enable boot from SPI NOR flash")
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-07-31 17:34:43 +08:00
Jonas Karlman
52f6b96d27 rockchip: rk3568-rock-3a: Fix SPI Flash alias
The commit 64f79f88a7 ("rockchip: rk3568-rock-3a: Enable boot from SPI
NOR flash") enabled SPI flash support by overriding the spi0 alias.

Correct this by adding a new spi4 alias in rk356x-u-boot.dtsi and
SF_DEFAULT_BUS=4 and SPL_DM_SEQ_ALIAS=y in defconfig. Also enabled
support for parsing and auto discovery of parameters, SFDP.

Fixes: 64f79f88a7 ("rockchip: rk3568-rock-3a: Enable boot from SPI NOR flash")
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-07-31 17:34:43 +08:00
Jonas Karlman
6ed39520a7 doc: rockchip: Update SPI flashing instruction
Update documentation on how to write a bootable u-boot-rockchip-spi.bin
image into SPI flash. This removes the reference to a hardcoded and now
obsolete 0x60000 payload offset.

Also remove an obsolete reference to pad_cat.

Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Quentin Schulz <foss+u-boot@0leil.net>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-07-31 17:34:43 +08:00
Jonas Karlman
ee75f16868 rockchip: rk3399-roc-pc: Fix SPL max size and SPI flash payload offset
TPL max size is limited to 184 KB, SPL is loaded to 0x0 and TF-A is
loaded to 0x40000, this limit SPL max size to 256 KB. With BootRom only
reading first 2 KB per 4 KB page of SPI flash, 880 KB may be needed for
TPL+SPL in a worst-case scenario. (184 KB + 256 KB) x 2 = 880 KB

Use 0xE0000 (896 KB) as the payload offset in SPI flash, this allows
for a payload of 3168 KB before env offset start to overlap.

Also add CONFIG_ROCKCHIP_SPI_IMAGE=y to build a bootable SPI flash
image, u-boot-rockchip-spi.bin.

Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Quentin Schulz <foss+u-boot@0leil.net>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-07-31 17:34:43 +08:00
Jonas Karlman
263f81d3a5 rockchip: rk3399-pinephone-pro: Fix SPL max size and SPI flash payload offset
TPL max size is limited to 184 KB, SPL is loaded to 0x0 and TF-A is
loaded to 0x40000, this limit SPL max size to 256 KB. With BootRom only
reading first 2 KB per 4 KB page of SPI flash, 880 KB may be needed for
TPL+SPL in a worst-case scenario. (184 KB + 256 KB) x 2 = 880 KB

Use 0xE0000 (896 KB) as the payload offset in SPI flash, this allows
for a payload of 3168 KB before env offset start to overlap.

Also add CONFIG_ROCKCHIP_SPI_IMAGE=y to build a bootable SPI flash
image, u-boot-rockchip-spi.bin.

Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Quentin Schulz <foss+u-boot@0leil.net>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-07-31 17:34:43 +08:00
Jonas Karlman
cc11d5c4ba rockchip: rk3399-pinebook-pro: Fix SPL max size and SPI flash payload offset
TPL max size is limited to 184 KB, SPL is loaded to 0x0 and TF-A is
loaded to 0x40000, this limit SPL max size to 256 KB. With BootRom only
reading first 2 KB per 4 KB page of SPI flash, 880 KB may be needed for
TPL+SPL in a worst-case scenario. (184 KB + 256 KB) x 2 = 880 KB

Use 0xE0000 (896 KB) as the payload offset in SPI flash, this allows
for a payload of 3168 KB before env offset start to overlap.

Also add CONFIG_ROCKCHIP_SPI_IMAGE=y to build a bootable SPI flash
image, u-boot-rockchip-spi.bin.

Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Quentin Schulz <foss+u-boot@0leil.net>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-07-31 17:34:43 +08:00
Jonas Karlman
ada6328738 rockchip: rk3399-rockpro64: Fix SPL max size and SPI flash payload offset
TPL max size is limited to 184 KB, SPL is loaded to 0x0 and TF-A is
loaded to 0x40000, this limit SPL max size to 256 KB. With BootRom only
reading first 2 KB per 4 KB page of SPI flash, 880 KB may be needed for
TPL+SPL in a worst-case scenario. (184 KB + 256 KB) x 2 = 880 KB

Use 0xE0000 (896 KB) as the payload offset in SPI flash, this allows
for a payload of 3168 KB before env offset start to overlap.

Also remove CONFIG_LTO=y now that there is sufficient space for SPL in
SPI flash, and to fix a build issue reported by Peter Robinson.

Fixes: 5713135ecc ("rockchip: rockpro64: Build u-boot-rockchip-spi.bin")
Reported-by: Peter Robinson <pbrobinson@gmail.com>
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Quentin Schulz <foss+u-boot@0leil.net>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-07-31 17:34:43 +08:00
Jonas Karlman
f40dcc7d1e rockchip: rk356x-u-boot: Use relaxed u-boot,spl-boot-order
BootRom will try to load TPL+SPL from media in the following order:
- SPI NOR Flash
- SPI NAND Flash
- NAND Flash
- eMMC
- SDMMC

SPL will try to load FIT from media in the order defined in the device
tree u-boot,spl-boot-order property.

Change the default order to load FIT from to:
- same media as TPL+SPL
- SDMMC
- eMMC

Boards with strict load order requirements should override the
u-boot,spl-boot-order property in the board specific u-boot.dtsi.

Fixes: 42f67fb51c ("rockchip: rk3568: Fix boot device detection")
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-07-31 17:34:43 +08:00
Jonas Karlman
a3ef37a08d rockchip: rk356x-u-boot: Add bootph-all to common pinctrl nodes
Add bootph-all prop to common pinctrl nodes for eMMC, FSPI, SD-card and
UART2 that are typically used by multiple boards. Unreferenced nodes are
removed from the SPL device tree during a normal build.

Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-07-31 17:34:43 +08:00
Jonas Karlman
23ad80a360 rockchip: rk3566-radxa-cm3-io: Sync dts from linux v6.4
Sync rk3566-radxa-cm3-io.dts from linux v6.4.

Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-07-31 17:34:42 +08:00
Jonas Karlman
0e3480c1f7 rockchip: rk356x: Sync dtsi from linux v6.4
Sync rk356x.dtsi from linux v6.4.

Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-07-31 17:34:42 +08:00
Jonas Karlman
6855fa625c board: rockchip: Add Pine64 SOQuartz on CM4-IO
The Pine64 SOQuartz compute module is mostly pin-compatible with the RPi
CM4 form factor. Therefore, it can slot into the official Raspberry Pi
CM4 IO carrier board. Add this configuration to U-Boot.

Features tested with a SOQuartz 4GB v1.1 2022-07-11:
- SD-card boot
- eMMC boot
- USB host

Device tree is imported from linux v6.4.

Co-developed-by: Nicolas Frattaroli <frattaroli.nicolas@gmail.com>
Signed-off-by: Nicolas Frattaroli <frattaroli.nicolas@gmail.com>
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-07-31 14:41:36 +08:00
Jonas Karlman
d0026e5908 board: rockchip: Add Pine64 SOQuartz on Blade
The Pine64 SOQuartz Blade board is a carrier board for the SOQuartz
CM4-compatible compute module. It features PoE, an M.2 slot, an SD card
slot, HDMI, USB, serial and ethernet.

Features tested with a SOQuartz 4GB v1.1 2022-07-11:
- SD-card boot
- eMMC boot
- PCIe/NVMe
- USB host

Device tree is imported from linux v6.4.

Co-developed-by: Nicolas Frattaroli <frattaroli.nicolas@gmail.com>
Signed-off-by: Nicolas Frattaroli <frattaroli.nicolas@gmail.com>
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-07-31 14:41:35 +08:00
Jonas Karlman
651492bfb2 board: rockchip: Add Pine64 SOQuartz on Model A
The Pine64 SOQuartz Model A board is a carrier board for the SOQuartz
CM4-compatible compute module. It exposes PCIe, ethernet, USB, HDMI,
CSI, DSI, eDP and a 40 pin GPIO header, and is powered by 12V DC.

Features tested with a SOQuartz 4GB v1.1 2022-07-11:
- SD-card boot
- eMMC boot
- PCIe/NVMe/AHCI
- USB host

Device tree is imported from linux v6.4.

Co-developed-by: Nicolas Frattaroli <frattaroli.nicolas@gmail.com>
Signed-off-by: Nicolas Frattaroli <frattaroli.nicolas@gmail.com>
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-07-31 14:41:35 +08:00
Jonas Karlman
f52452bbea board: rockchip: Add Pine64 Quartz64-B Board
The Pine64 Quartz64 Model B is a credit-card sized single-board
computer based on the Rockchip RK3566 SoC. The board features an M.2
PCIe slot, USB3, USB2, eMMC, SD, ethernet, HDMI, analog audio out, a
40 pin GPIO header and a DSI and CSI port, as well as on-board Wi-Fi.

Features tested on a Quartz64-B 4GB v1.4 2022-06-06:
- SD-card boot
- eMMC boot
- SPI Flash boot
- PCIe/NVMe
- USB host

Device tree is imported from linux v6.4.

Co-developed-by: Nicolas Frattaroli <frattaroli.nicolas@gmail.com>
Signed-off-by: Nicolas Frattaroli <frattaroli.nicolas@gmail.com>
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-07-31 14:41:35 +08:00
Jonas Karlman
9c1b5d163e board: rockchip: Add Pine64 Quartz64-A Board
The Pine64 Quartz64 Model A is a single-board computer based on the
Rockchip RK3566 SoC. The board features USB3, SATA, PCIe, HDMI, USB2.0,
CSI, DSI, eDP, eMMC, SD, and an e-paper parallel port, as well as a
20 pin GPIO header.

Features tested on a Quartz64-A 8GB v2.0 2021-04-27:
- SD-card boot
- eMMC boot
- PCIe/NVMe/AHCI
- USB host

Device tree is imported from linux v6.4.

Co-developed-by: Nicolas Frattaroli <frattaroli.nicolas@gmail.com>
Signed-off-by: Nicolas Frattaroli <frattaroli.nicolas@gmail.com>
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-07-31 14:41:35 +08:00
Jonas Karlman
f8a2d1c108 rockchip: rk3568: Use dwc3-generic driver
Change RK3568 devices to use the newer dwc3-generic driver instead of
the old xhci-dwc3 driver for USB 3.0 support.

Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-07-31 14:40:38 +08:00
Jonas Karlman
caaeac8846 usb: dwc3-generic: Add rk3568 support
RK3568 share glue and ctrl in a single node. Use glue_get_ctrl_dev to
return the glue node as the ctrl node.

Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Marek Vasut <marex@denx.de>
2023-07-31 14:40:38 +08:00
Jonas Karlman
6913c30516 usb: dwc3-generic: Relax unsupported dr_mode check
When dr_mode is peripheral or otg and U-Boot has not been built with
DM_USB_GADGET support, booting such device may end up with:

  dwc3_glue_bind_common: subnode name: usb@fcc00000
  Error binding driver 'dwc3-generic-wrapper': -6
  Some drivers failed to bind
  initcall sequence 00000000effbca08 failed at call 0000000000a217c8 (err=-6)
  ### ERROR ### Please RESET the board ###

Instead fail gracfully with ENODEV to allow board continue booting.

  dwc3_glue_bind_common: subnode name: usb@fcc00000
  dwc3_glue_bind_common: unsupported dr_mode 3

Also use CONFIG_IS_ENABLED(USB_HOST) and change switch to if statements
to improve readability of the code.

Fixes: 446e3a205b ("dwc3-generic: Handle the PHYs, the clocks and the reset lines")
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Marek Vasut <marex@denx.de>
2023-07-31 14:40:38 +08:00
Jonas Karlman
4412a2bf0b usb: dwc3-generic: Return early when there is no child node
The current error check for device_find_first_child is not working as
expected, the documentation for device_find_first_child mention:

  @devp: Returns first child device, or NULL if none
  Return: 0

Change to return early when there is no child node to avoid any possible
null pointer dereference.

Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Marek Vasut <marex@denx.de>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-07-31 14:40:38 +08:00
Jonas Karlman
bec51f3fb3 Revert "arm: dts: rockchip: radxa-cm3-io, rock-3a: enable regulators for usb"
Remove regulator-boot-on prop from regulators now that the phy core has
support for phy-supply after the commit c57e0dcd93 ("phy: add support
for phy-supply").

This reverts commit 7911f409ff.

Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-07-31 14:40:38 +08:00
Alper Nebi Yasak
42cb8f0112 rockchip: chromebook_speedy: Enable sound
Commit ec107f04b6 ("rockchip: chromebook_minnie: Enable sound") and
commit 2d0c01b8f0 ("sound: rockchip: Add sound support for jerry")
enable audio support for chromebook_minnie and chromebook_jerry. Enable
it for chromebook_speedy as well, but put the non-upstream sound node
in the board -u-boot.dtsi instead.

Signed-off-by: Alper Nebi Yasak <alpernebiyasak@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-07-31 14:40:13 +08:00