Add support for both the BananaPi BPI-CM4 module and the BananaPi
baseboard which is compatible with the RaspberryPi CM4IO baseboard.
The BananaPi BPI-CM4 module follows the CM4 specifications at [1],
but with a single HDMI port and a single DSI output.
The current CM4IO baseboard DT should work fine on the Raspberry CM4
baseboard and other derivatives baseboards, but proper DT should
be written for other baseboards.
[1] https://datasheets.raspberrypi.com/cm4io/cm4io-datasheet.pdf
Link: https://lore.kernel.org/r/20230307-u-boot-cm4-v1-2-43f5a393cd37@linaro.org
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
Mask macro PART_ACCESS_MASK filter out access bits of emmc register and
macro EXT_CSD_EXTRACT_BOOT_PART() extracts boot part bits of emmc register.
So use EXT_CSD_EXTRACT_BOOT_PART() when extracting boot partition.
Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Add board code for R8A779G0 V4H White Hawk board.
Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Signed-off-by: Hai Pham <hai.pham.ud@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
[Marek: Synchronize configuration symbols which are now switched to Kconfig
Mallocate gd->bd->bi_boot_params, i.e. drop the assignment
Sort headers, use clrbits_le32(), use BIT macros where appropriate
Use CONFIG_SYS_CLK_FREQ for counter frequency instead of custom macro]
Add board code for R8A779F0 S4 Spider board.
Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Signed-off-by: Hai Pham <hai.pham.ud@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
[Marek: Synchronize configuration symbols which are now switched to Kconfig
Mallocate gd->bd->bi_boot_params, i.e. drop the assignment
Sort headers, use clrbits_le32(), use BIT macros where appropriate
Use CONFIG_SYS_CLK_FREQ for counter frequency instead of custom macro]
This adds R-Car Generation 4 (Gen4) support as Renesas ARM64 SoC.
In this version, reusing R-Car Gen3 lowlevel initialize routine [1]
and R-Car Gen3 memory map tables [2] .
[1] arch/arm/mach-rmobile/lowlevel_init_gen3.S
[2] arch/arm/mach-rmobile/memmap-gen3.c
Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Signed-off-by: Hai Pham <hai.pham.ud@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
[Marek: - Enable DTO support by default
- Sort the Kconfig lists
- Select RCAR_64 Kconfig option to pull in all the shared
Kconfig options with Gen3, and use where applicable to
deduplicate entries.
- Fix reference [2] typo in commit message
- Drop config options moved to Kconfig, rename rest to CFG_
accordingly to synchronize with upstream changes. Drop
removed CONFIG_VERY_BIG_RAM.
- Move board size limit to arch/Kconfig
- Move GICR_BASE to headers instead of common config]
There is no need for the board file to instantiate a PL01X platform
device anymore. This is all taken care of by the DM code which now will
probe the device based on the DT node.
Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Beacon Embedded has an i.MX8M Plus development kit which consists
of a SOM + baseboard. The SOM includes Bluetooth, WiFi, QSPI, eMMC,
and one Ethernet PHY. The baseboard includes audio, HDMI, USB-C Dual
Role port, USB Hub with five ports, a PCIe slot, and a second Ethernet
PHY. The device trees are already queued for inclusion in Linux 6.3.
Signed-off-by: Adam Ford <aford173@gmail.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Add support for Data Modul i.MX8M Plus eDM SBC board. This is an
evaluation board for various custom display units. Currently
supported are serial console, ethernet, eMMC, SD, SPI NOR, USB.
Signed-off-by: Marek Vasut <marex@denx.de>
change prints to show which DDR configuration (single/dual rank) is used
Signed-off-by: Emanuele Ghidoli <emanuele.ghidoli@toradex.com>
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Deduplicate similar DDRC configurations and LPDDR4 training patterns
by patching a single configuration.
The aim is to reduce the SPL memory footprint and simplify maintenance
of lpddr4_timing.c
Signed-off-by: Emanuele Ghidoli <emanuele.ghidoli@toradex.com>
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Update LPDDR4 configuration and training using updated spreadsheet and
tools from NXP using data from previous spreadsheet and verified
toward datasheet:
- MX8M_Plus_LPDDR4_RPA_v9.xlsx
- mscale_ddr_tool_v3.30.exe
From:
https://community.nxp.com/t5/i-MX-Processors-Knowledge-Base/i-MX-8M-Family-DDR-Tool-Release/ta-p/1104467
Some register values differ due to these fixes/modifications:
- corrected calculation of T_CKPDX parameter (equal to tCKCKEH for LPDDR4)
- corrected ECC related items, none of which affect normal operation
when ECC is not enabled
- corrected formula for calculation of tRTP in cell D122
Signed-off-by: Emanuele Ghidoli <emanuele.ghidoli@toradex.com>
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Change tRFCmin (tRFCab) from 280 ns to 380 ns to be compliant with
current and futures memories.
Fixes: 2bc2f817ce ("board: toradex: add verdin imx8m plus support")
Signed-off-by: Emanuele Ghidoli <emanuele.ghidoli@toradex.com>
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Add support to Verdin IMX8MP V1.1B SKU which uses
MT53E1G32D2FW-046 WT:B memory.
Compared to the 8 GB memory (MT53E2G32D4NQ-046 WT:A) used on
Verdin IMX8MP V1.0A it has 16 row addresses instead of 17.
In fact, the new memory, is a 2 GB/rank memory. The 8 GB memory is a
4 GB/rank memory.
Manually tweaking Host Interface addresses vs LPDDR4 signals mapping it
is possible to have a single configuration working with both memories:
- Old configuration: HIF bit 30 -> rank, HIF bit 29 -> Row 16
- New configuration: HIF bit 29 -> rank, HIF bit 30 -> Row 16
With this change the memory space from the host processor is contiguous
for both the configurations and the correct memory size is computed
using get_ram_size() at runtime.
Support for single rank memories still works thanks to the fact
dual ranks training fails (ddr_init->ddr_cfg_phy) toward single rank
memories.
Signed-off-by: Emanuele Ghidoli <emanuele.ghidoli@toradex.com>
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
---------------------------------
CI: https://source.denx.de/u-boot/custodians/u-boot-imx/-/pipelines/15819
i.MX patches queued for next:
- Conversions to DM_SERIAL
- Fixes for Toradex boards
- Gateworks Boards
- i.MX8ULP
- EQoS support / fixes, changes in boards
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Merge tag 'u-boot-imx-next-20230331' of https://gitlab.denx.de/u-boot/custodians/u-boot-imx into next
u-boot-imx-next-20230331 for next
---------------------------------
CI: https://source.denx.de/u-boot/custodians/u-boot-imx/-/pipelines/15819
i.MX patches queued for next:
- Conversions to DM_SERIAL
- Fixes for Toradex boards
- Gateworks Boards
- i.MX8ULP
- EQoS support / fixes, changes in boards
The FEC interface mode is now configured in common board_interface_eth_init()
and called by FEC MAC driver when appropriate. Drop the board side duplicates
if the same functionality.
Signed-off-by: Marek Vasut <marex@denx.de>
The EQoS interface mode is now configured in common board_interface_eth_init()
and called by EQoS MAC driver when appropriate. Drop the board side duplicates
if the same functionality.
Signed-off-by: Marek Vasut <marex@denx.de>
We have a few places here that the function declarations do not
match their prototypes, correct them.
Signed-off-by: Ying-Chun Liu (PaulLiu) <paulliu@debian.org>
Cc: Tom Rini <trini@konsulko.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: NXP i.MX U-Boot Team <uboot-imx@nxp.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reported-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
The following expression is used to construct the device tree name:
fdtfile=${soc}-colibri-${fdt_board}.dtb
- soc is set dynamically (either imx8qxp or imx8dx)
- fdt_board can be modified by the user (eval-v3, aster, iris/iris-v2)
Signed-off-by: Andrejs Cainikovs <andrejs.cainikovs@toradex.com>
Refactor the detection of QXP vs. DX SoC into its own helper function.
Signed-off-by: Max Krummenacher <max.krummenacher@toradex.com>
Signed-off-by: Andrejs Cainikovs <andrejs.cainikovs@toradex.com>
All Colibri iMX8X variants have 2nd RGMII on SoC, so add the address
for 2nd ethernet.
Signed-off-by: Andrejs Cainikovs <andrejs.cainikovs@toradex.com>
Since commit 1fa43cad86 ("video: Drop references to CONFIG_VIDEO et al")
the mx51evk_video.c is no longer used.
Remove the unused file.
Signed-off-by: Fabio Estevam <festevam@denx.de>
Since commit 1fa43cad86 ("video: Drop references to CONFIG_VIDEO et al")
the mx53loco_video.c is no longer used.
Remove the unused file.
Signed-off-by: Fabio Estevam <festevam@denx.de>
Now that the gwventana_emmc_defconfig is the same as the
gwventana_gw5904_defconfig we can remove the latter.
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
The i.MX8MP DHCOM SoM may be populated with either KSZ9131RNXI RGMII PHY
or LAN8740Ai RMII PHY attached to EQoS MAC, and either external RGMII PHY
or LAN8740Ai RMII PHY attached to FEC MAC. The SoM configuration can be
detected for each MAC by reading RX_CTL pull resistor state early on boot.
Make use of this, detect the exact PHY configuration, and patch control DT
accordingly so that the ethernet is configured correctly in U-Boot.
Signed-off-by: Marek Vasut <marex@denx.de>
The DH electronics i.MX8M Plus DHCOM SoM currently supports only 4 GiB
of DRAM population option. Add another population option with 2 GiB of
DRAM. The chips used on the 2 GiB option are 2x K4F6E3S4HM-MGCJ .
Signed-off-by: Marek Vasut <marex@denx.de>
[upstream of vendor commit 19a96f7c40a8fc1d0a6546ac2418d966e5840a99]
The Clearfog devices have only one SDHC device. This is either eMMC if
it is populated on the SOM or SDHC if not. The Linux device tree assumes
the SDHC case. Detect if the device is an eMMC and fixup the device-tree
so it will be detected by Linux.
Ported from vendor repo at https://github.com/SolidRun/u-boot
Signed-off-by: Martin Rowe <martin.p.rowe@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
The usage of DM_PMIC is preferred, so convert to it.
This also brings the benefit of causing a significant amount
of code removal.
Signed-off-by: Fabio Estevam <festevam@denx.de>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
The usage of DM_PMIC is preferred, so convert to it.
This also brings the benefit of causing a significant amount
of code removal.
Signed-off-by: Fabio Estevam <festevam@denx.de>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
I don't have access to the mx6sxsabreauto board, so remove myself
from the MAINTAINERS entry and add Peng instead.
Signed-off-by: Fabio Estevam <festevam@denx.de>
Acked-by: Peng Fan <peng.fan@nxp.com>
When using dual boot mode, the DDR won't be reset when APD power off
or reboot. It has possibility that obsolete fdt data existing on
fdt_addr_r address. Then even nothing in EFI partitions, the distro boot
still continue to parse fdt and get uboot crashed.
Clear the data at fdt_addr_r, so the fdt header check in above case
will not pass.
Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Bit0: Port 0 behavior when bandwidth maximized. Set to 1 to allow overflow
With overflow set, we see some issue that A35 may not able to get enough
bandwidth and A35 will report hrtimer takes too much time, workqueue
lockup. With overflow cleared, the issues are gone.
Reviewed-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
To resolve DCNANO underrun issue, change the DDR Port 0 arbitration
from round robin fashion to fixed priority level 1, while other ports
are not assigned any priority, so they will be serviced in round robin
fashion if there is no active request from Port 0.
Signed-off-by: Ye Li <ye.li@nxp.com>
Acked-by: Peng Fan <peng.fan@nxp.com>
This patch is used to support DBD owner fuse changed to S400 only.
The XRDC PDAC2 for LPAV pbridge5 and MSC1/2/3 for GPIO and LPAV are not
configured by S400 default setting. So these PDAC and MSC are invalid,
only DBD owner can access the corresponding resources.
We have to configure necessary PDAC and MSC for SPL before DDR
initialization.
Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
To fit the DBD_EN fused part, we re-design the TRDC and XRDC assignment.
M33 will be the TRDC owner and needs to configure TRDC. A35 is the
XRDC owner, ATF will configure XRDC.
The handshake between U-boot and M33 image is used to sync TRDC and
XRDC configuration completion. Once the handshake is done, A35 and M33
can access the allowed resources in others domain.
The handshake is needed when M33 is booted or DBD_EN fused, because both
cases will enable the TRDC. If handshake is timeout, the boot will hang.
We use SIM GPR0 to pass the info from SPL to u-boot, because before the
handshake, u-boot can't access SEC SIM and FSB.
Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Jacky Bai <ping.bai@nxp.com>
In both SPL and u-boot, after probing the S400 MU, get the chip revision,
lifecycle and UID from Sentinel.
Update get_cpu_rev to use the chip revision not hard coded it for A0
Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Move to using .env file for setting up environment variables for am65x.
Signed-off-by: Nikhil M Jain <n-jain1@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Include ti_armv7_common.env and ti/mmc.env, which includes' K3 common
environment variables used across different K3 boards.
This patch depends on
https://lore.kernel.org/all/20230315052745.110502-1-n-francis@ti.com/
Signed-off-by: Nikhil M Jain <n-jain1@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Move to using .env file for setting up environment variables for J721E
and J7200.
Signed-off-by: Neha Malcom Francis <n-francis@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Move to using .env file for setting up environment variables for J721S2.
Signed-off-by: Neha Malcom Francis <n-francis@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
For non TI boards it is not possible to enable the do_board_detect()
call as TI_I2C_BOARD_DETECT is defined in board/ti/common/Kconfig.
I want to use do_board_detect() to dectect boards and properties based
on some SPI communication with a FPGA.
Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Kconfig does not support using 'select' to select a 'choice'. A choice
can be configured by either setting the choice symbol to 'y' in a
configuration file or by setting a 'default' of the choice.
In board/ti/*/Kconfig the SOC_K3_* choice is already set to 'y' in their
corresponding configs/*_defconfig file. So remove selecting it.
Signed-off-by: Neha Malcom Francis <n-francis@ti.com>
The M.2 slots of the related IOT2050 variant need to be configured
according to the plugged cards. This tries to detect the card using the
M.2 configuration pins of the B-key slot. If that fails, a U-Boot
environment variable can be set to configure manually. This variable is
write-permitted also in secure boot mode as it is not able to undermine
the integrity of the booted system.
The configuration is then applied to mux the serdes and to fix up the
device tree passed to or loaded by the bootloader. The fix-ups are
coming from device tree overlays that are embedded into the firmware
image and there also integrity protected. The OS remains free to load
a device tree to which they do not apply: U-Boot will not fail to boot
in that case.
Based on original patch by Chao Zeng.
Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
User-button is controlled by the mcu domain gpio number 25.
But main0 main1 mcu domain all have gpio number 25.
To identify where the gpio is from, Using gpio controll base as the prefix
to indicate the gpio resource.
Signed-off-by: chao zeng <chao.zeng@siemens.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Use external blob otpcmd.bin to replace the 0xff filled OTP programming
command block to create a firmware image that provisions the OTP on
first boot. This otpcmd.bin is generated from the customer keys using
steps described in the meta-iot2050 integration layer for the device.
Based on original patch by Baocheng Su.
Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
