Enable and use the clock driver routine
defined in clock driver toset required
clock appropriately.
Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
axi_emac, emaclite and gem have the same issue with registering
multiple instances with mdio busses. mdio bus name has to be uniq but
drivers are setting up only one name for all.
Use mdio_register_seq() and pass dev->seq number to allow multiple
mdio instances registration.
Reported-by: Phani Kiran Kara <phanikiran.kara@gmail.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
axi_emac, emaclite and gem have the same issue with registering
multiple instances with mdio busses. mdio bus name has to be uniq but
drivers are setting up only one name for all.
Use mdio_register_seq() and pass dev->seq number to allow multiple
mdio instances registration.
Reported-by: Phani Kiran Kara <phanikiran.kara@gmail.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Series-to: u-boot
Series-cc: Phani Kiran Kara <phanikiran.kara@gmail.com>
It is confusing that mdio commands work and report phy id as
decimal value when mii is working with hex values.
For example:
ZynqMP> mdio list
gem:
21 - TI DP83867 <--> ethernet@ff0e0000
ZynqMP> mdio read ethernet@ff0e0000 0
Reading from bus gem
PHY at address 21:
0 - 0x1140
ZynqMP> mii dump 21 0
Incorrect PHY address. Range should be 0-31
...
ZynqMP> mii dump 15
0. (1140) -- PHY control register --
(8000:0000) 0.15 = 0 reset
U-Boot normally takes hex values that's why this patch is changing mdio
command to handle hex instead of changing mii command to handle decimal
values.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Correct the SGMII enable bit position to 27 instead
of 31.
Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Modify the nwcfg bit definitions to have 32-bit
by removing the extra nibble.
Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Now, include/linux/errno.h is a wrapper of <asm-generic/errno.h>.
Replace all include directives for <asm-generic/errno.h> with
<linux/errno.h>.
<asm-generic/...> is supposed to be included from <asm/...> when
arch-headers fall back into generic implementation. Generally, they
should not be directly included from .c files.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
[trini: Add drivers/usb/host/xhci-rockchip.c]
Signed-off-by: Tom Rini <trini@konsulko.com>
Add the ability to pass the phy-handle node offset
to the phy driver. This allows the phy driver
to access the DT subnode's data and parse accordingly.
Signed-off-by: Dan Murphy <dmurphy@ti.com>
Tested-by: Michal Simek <michal.simek@xilinx.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
PCS auto negotaiation bit should be enabled
along with SGMII autonegotation enabled
in phy.
Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Return error from probe in case of invalid phy address.
This fixes the issue of uboot crash if phy is not detected.
Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Provide board specific option how to read MAC address from ROM.
Do it in generic way to be reusable by differnet boards.
If this is not enough board specific functions can be created.
Signed-off-by: Joe Hershberger <joe.hershberger@gmail.com> # driver part
Signed-off-by: Michal Simek <monstr@monstr.eu>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Add support of SGMII interface for zynq GEM.
Read xlnx,emio property from DT.
Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
MDC setting depends on pclk input clocks which varies across SoC. This
driver is used by xilinx zynq and zynqmp SOC.
Input clock frequence on silicon is 125MHz where divider 64 put
frequency below 2.5MHz requires by spec (125/64=1.95).
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Use core to call net_process_received_packet() instead of call inside
the driver.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
recv function should return 0 instead of frame_len not to
proceed the same packet again in core.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Do not set interface via configs. Read information from DT.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Jagan Teki <jteki@openedev.com>
- Enable DM_ETH by default for Zynq and ZynqMP
- Remove board_eth_init code
- Change miiphy_read function to return value instead of error code
based on DM requirement
- Do not enable EMIO DT support by default
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Jagan Teki <jteki@openedev.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
This function was used for OF init before DM.
Remove this function as the part of move to DM.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Jagan Teki <jteki@openedev.com>
Enable access to MDIO before zynq_gem_init is called.
It enables read information about phy earlier.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Move phy init code out of zynq_gem_init. DM drivers are normally calling
this code from probe function.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Next step to move driver to driver model. Do not use eth_device
structure. Use private structure instead.
Add iobase to private structure to store gem iobase.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Add return value for phy detection algorithm to stop init function when
phy is not found.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Jagan Teki <jteki@openedev.com>
Based on spec:
"MDC must not exceed 2.5 MHz (MDC is only active during MDIO read and
write operations)"
Zynq is running on 111MHz. Current setting is 32 which is 111/32=3.47
which is above of 2.5MHz.
Using 48 divider will give us correct setting according spec
(111/48=2.31).
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Using set and clear macro is incorrect because it is not overwritting
origin mdc clock division setup.
For example origin setup is 8(0b001) and new setup is 64(0b100) which
means 0b101 is setup which is 96 divider.
Using writel to rewrite all setting like for 1000Mbit/s case.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Zynq has no priority queues.
ZynqMP has one priority queue and this change is required
to get ethernet working.
This patch was not needed on ep108 for uknown reason even
it should be used.
Tested on Zynq and ZynqMP.
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Target is duplicating packets. IP prefetches another BD and process it
when the first one is sent. Adding one dummy BD to the chain fix the
problem with packet duplication.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
BD_SEPRN_SPACE should not have hard coded value and it will be
calculated based on the number of buffer descriptors that we
would like to use.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Previous loop was completely bogus. Iterration should go just over
statistic counters.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Extend comments with register offset to help with debuggging.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
MII is setup by default for all cases. The most of boards are using
RGMII but PHY drivers are not doing any specific setting that's why MII
setting was working fine. With TI DP83867 is necessary to setup
paramaters based on interface type.
Use one setting per board for it which is something what will be removed
when driver is moved to DM.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Add debug messages to phyread/write to help with PHY debug.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Fix below warnings happening for xilinx_zynqmp_ep_defconfig
drivers/net/zynq_gem.c: In function ‘zynq_gem_init’:
drivers/net/zynq_gem.c:330:7: warning: cast from pointer to integer
of different size [-Wpointer-to-int-cast]
((u32)(priv->rxbuffers) +
^
In file included from drivers/net/zynq_gem.c:19:0:
drivers/net/zynq_gem.c:336:10: warning: cast from pointer to integer
of different size [-Wpointer-to-int-cast]
writel((u32)priv->rx_bd, ®s->rxqbase);
^
./arch/arm/include/asm/io.h:146:34: note: in definition of macro ‘writel’
#define writel(v,c) ({ u32 __v = v; __iowmb(); __arch_putl(__v,c); __v; })
^
drivers/net/zynq_gem.c: In function ‘zynq_gem_send’:
drivers/net/zynq_gem.c:399:9: warning: cast from pointer to integer
of different size [-Wpointer-to-int-cast]
writel((u32)priv->tx_bd, ®s->txqbase);
^
./arch/arm/include/asm/io.h:146:34: note: in definition of macro ‘writel’
#define writel(v,c) ({ u32 __v = v; __iowmb(); __arch_putl(__v,c); __v; })
^
drivers/net/zynq_gem.c:404:22: warning: cast from pointer to integer
of different size [-Wpointer-to-int-cast]
priv->tx_bd->addr = (u32)ptr;
^
drivers/net/zynq_gem.c:409:9: warning: cast from pointer to integer
of different size [-Wpointer-to-int-cast]
addr = (u32) ptr;
^
drivers/net/zynq_gem.c:414:9: warning: cast from pointer to integer
of different size [-Wpointer-to-int-cast]
addr = (u32)priv->rxbuffers;
^
drivers/net/zynq_gem.c: In function ‘zynq_gem_recv’:
drivers/net/zynq_gem.c:454:31: warning: cast to pointer from integer
of different size [-Wint-to-pointer-cast]
net_process_received_packet((u8 *)addr, frame_len);
^
drivers/net/zynq_gem.c: In function ‘zynq_gem_initialize’:
drivers/net/zynq_gem.c:533:35: warning: cast from pointer to integer
of different size [-Wpointer-to-int-cast]
priv->rx_bd = (struct emac_bd *)((u32)bd_space + BD_SEPRN_SPACE);
^
drivers/net/zynq_gem.c:533:16: warning: cast to pointer from integer
of different size [-Wint-to-pointer-cast]
priv->rx_bd = (struct emac_bd *)((u32)bd_space + BD_SEPRN_SPACE);
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
We have flipped CONFIG_SPL_DISABLE_OF_CONTROL. We have cleansing
devices, $(SPL_) and CONFIG_IS_ENABLED(), so we are ready to clear
away the ugly logic in include/fdtdec.h:
#ifdef CONFIG_OF_CONTROL
# if defined(CONFIG_SPL_BUILD) && !defined(SPL_OF_CONTROL)
# define OF_CONTROL 0
# else
# define OF_CONTROL 1
# endif
#else
# define OF_CONTROL 0
#endif
Now CONFIG_IS_ENABLED(OF_CONTROL) is the substitute. It refers to
CONFIG_OF_CONTROL for U-boot proper and CONFIG_SPL_OF_CONTROL for
SPL.
Also, we no longer have to cancel CONFIG_OF_CONTROL in
include/config_uncmd_spl.h and scripts/Makefile.spl.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
