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1000 commits

Author SHA1 Message Date
Masahiro Yamada
6825a95b0b kbuild: use Linux Kernel build scripts
Now we are ready to switch over to real Kbuild.

This commit disables temporary scripts:
  scripts/{Makefile.build.tmp, Makefile.host.tmp}
and enables real Kbuild scripts:
  scripts/{Makefile.build,Makefile.host,Makefile.lib}.

This switch is triggered by the line in scripts/Kbuild.include
  -build := -f $(if $(KBUILD_SRC),$(srctree)/)scripts/Makefile.build.tmp obj
  +build := -f $(if $(KBUILD_SRC),$(srctree)/)scripts/Makefile.build obj

We need to adjust some build scripts for U-Boot.
But smaller amount of modification is preferable.

Additionally, we need to fix compiler flags which are
locally added or removed.

In Kbuild, it is not allowed to change CFLAGS locally.
Instead, ccflags-y, asflags-y, cppflags-y,
CFLAGS_$(basetarget).o, CFLAGS_REMOVE_$(basetarget).o
are prepared for that purpose.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Tested-by: Gerhard Sittig <gsi@denx.de>
2014-02-19 11:07:50 -05:00
Masahiro Yamada
9e4140329e kbuild: change out-of-tree build
This commit changes the working directory
where the build process occurs.

Before this commit, build process occurred under the source
tree for both in-tree and out-of-tree build.

That's why we needed to add $(obj) prefix to all generated
files in makefiles like follows:
  $(obj)u-boot.bin:  $(obj)u-boot

Here, $(obj) is empty for in-tree build, whereas it points
to the output directory for out-of-tree build.

And our old build system changes the current working directory
with "make -C <sub-dir>" syntax when descending into the
sub-directories.

On the other hand, Kbuild uses a different idea
to handle out-of-tree build and directory descending.

The build process of Kbuild always occurs under the output tree.
When "O=dir/to/store/output/files" is given, the build system
changes the current working directory to that directory and
restarts the make.

Kbuild uses "make -f $(srctree)/scripts/Makefile.build obj=<sub-dir>"
syntax for descending into sub-directories.
(We can write it like "make $(obj)=<sub-dir>" with a shorthand.)
This means the current working directory is always the top
of the output directory.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Tested-by: Gerhard Sittig <gsi@denx.de>
2014-02-19 11:07:50 -05:00
Prabhakar Kushwaha
1b4175d6fa driver/ifc:Change accessor function to take care of endianness
IFC registers can be of type Little Endian or big Endian depending upon
Freescale SoC. Here SoC defines the register type of IFC IP.

So update acessor functions with common IFC acessor functions to take care
both type of endianness.

Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Acked-by: York Sun <yorksun@freescale.com>
2014-02-03 08:38:51 -08:00
Nikhil Badola
a4f7cba64e powerpc/usb: Enable dual phy for T1040
Define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE macro for enabling dual
phy in t1040

Signed-off-by: Nikhil Badola <nikhil.badola@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-02-03 08:38:49 -08:00
Prabhakar Kushwaha
5b7672fc49 boards/t1040qds: Adds ethernet support for T1040
Enable entherent for T1040QDS. It enables FM1@DTSEC3, FM1@DTSEC4, FM1@DTSEC5
    Define MDIO related configs
    Added eth.c file
    Update t1040.c to support RGMII and SGMII
    Update t1040qds.c to support ethernet
    Define the PHY address

Signed-off-by: Arpit Goel <B44344@freescale.com>
Signed-off-by: Bhupesh Sharma <bhupesh.sharma@freescale.com>
Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
[York Sun: remove dash from commit message]
Signed-off-by: York Sun <yorksun@freescale.com>
2014-02-03 08:38:48 -08:00
Prabhakar Kushwaha
96bda02c9e powerpc/mpc85xx: Update serdes protocols for T1040
T1040 has only one SerDes block. so update the code accordingly.

Also, add support of SerDes Protocol 0x00, 0x06, 0x40, 0x69 0x85,
0xA7 and 0xAA

Signed-off-by: Arpit Goel <B44344@freescale.com>
Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-02-03 08:38:48 -08:00
poonam aggrwal
4393fd40ad powerpc/mpc85xx: Update LIODNs for T1040
Removed LIODNs for RMAN, RIO, 10G. T1040 has 10 QMAN portals so assigned
LIODNs accordingly.

Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-02-03 08:38:48 -08:00
Masahiro Yamada
b2a6dfe4f8 powerpc: mpc5xxx: remove redundant CONFIG_MPC5xxx definition
We do not have to define CONFIG_MPC5xxx in board config headers
(and start.S) because it is defined in arch/powerpc/cpu/mpc5xxx/config.mk.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2014-01-24 16:59:21 -05:00
Masahiro Yamada
84acd1e179 powerpc: mpc86xx: move CONFIG_MPC86xx definition to CPU config.mk
Define CONFIG_MPC86xx in arch/powerpc/cpu/mpc86xx/config.mk
because all target boards with mpc86xx cpu define it.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2014-01-24 16:59:08 -05:00
Masahiro Yamada
d40ddae4b3 powerpc: mpc85xx: move CONFIG_MPC85xx definition to CPU config.mk
Define CONFIG_MPC85xx in arch/powerpc/cpu/mpc85xx/config.mk
because all target boards with mpc85xx cpu define it.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2014-01-24 16:59:08 -05:00
Masahiro Yamada
4b0065c644 powerpc: mpc5xx: remove redundant CONFIG_5xx definition
We do not have to define CONFIG_5xx in a source file
because it is defined in arch/powerpc/cpu/mpc5xx/config.mk.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2014-01-24 16:59:08 -05:00
Masahiro Yamada
07344edde2 powerpc: mpc8xx: remove redundant CONFIG_8xx definition
We do not have to define CONFIG_8xx in source files
because it is defined in arch/powerpc/cpu/mpc8xx/config.mk

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2014-01-24 16:59:08 -05:00
Masahiro Yamada
36aa822880 powerpc: delete unused header files
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2014-01-24 16:59:07 -05:00
Masahiro Yamada
d937326ffc Remove obsolete _LINUX_CONFIG_H macro
Commit 643aae1406
deleted include/linux/config.h but missed to
delete _LINUX_CONFIG_H macro.
It is no longer used at all.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2014-01-24 16:59:07 -05:00
Haijun.Zhang
f28bea0003 eSDHC: Calculate envaddr accroding to the address format
On BSC9131, BSC9132, P1010 : For High Capacity SD Cards (> 2 GBytes), the
32-bit source address specifies the memory address in block address
format. Block length is fixed to 512 bytes as per the SD High Capacity
specification. So we need to convert the block address format
to byte address format to calculate the envaddr.

If there is no enough space for environment variables or envaddr
is larger than 4GiB, we relocate the envaddr to 0x400. The address
relocated is in the front of the first partition that is assigned
for sdboot only.

Signed-off-by: Haijun Zhang <haijun.zhang@freescale.com>
Acked-by: Pantelis Antoniou <panto@antoniou-consulting.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-01-22 08:56:44 -08:00
Po Liu
6609916efb powerpc:mpc85xx: Add ifc nand boot support for TPL/SPL
Using the TPL method for nand boot by sram was already
supported. Here add some code for mpc85xx ifc nand boot.

	- For ifc, elbc, esdhc, espi, all need the SPL without
	section .resetvec.
	- Use a clear function name for nand spl boot.
	- Add CONFIG_SPL_DRIVERS_MISC_SUPPORT to compile the fsl_ifc.c
	in spl/Makefile;

Signed-off-by: Po Liu <Po.Liu@freescale.com>
Acked-by: Scott Wood <scottwood@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-01-21 13:42:01 -08:00
York Sun
b518816423 powerpc/mpc85xx: Fix a typo in workaround message for DDR erratum A003474
Unfortunately a typo presents "DDR-A003473" instead of "DDR-A003474".

Signed-off-by: York Sun <yorksun@freescale.com>
2014-01-21 13:40:18 -08:00
Shengzhou Liu
842eaa1361 powerpc/85xx: update erratum a006379
Enable Erratum A006379 for T2080, T2081, T4160, B4420.

Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-01-21 13:39:19 -08:00
Ramneek Mehresh
3f283f4bdc powerpc/83xx: Add support for get_svr() for 83xx devices
Defines get_svr() for 83xx devices

Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-01-21 13:35:43 -08:00
Shengzhou Liu
2ffa96d815 powerpc/t208x: fix macro CONFIG_SYS_FSL_NUM_USB_CTRLS
CONFIG_SYS_FSL_NUM_USB_CTRLS is no longer used,
update it to new CONFIG_USB_MAX_CONTROLLER_COUNT.

Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
2014-01-02 14:10:13 -08:00
Priyanka Jain
b135991a3c powerpc/mpc85xx: Add support for single source clocking
Single-source clocking is new feature introduced in T1040.
In this mode, a single differential clock is supplied to the
DIFF_SYSCLK_P/N inputs to the processor, which in turn is
used to supply clocks to the sysclock, ddrclock and usbclock.

So, both ddrclock and syclock are driven by same differential
sysclock in single-source clocking mode whereas in normal clocking
mode, generally separate DDRCLK and SYSCLK pins provides
reference clock for sysclock and ddrclock

DDR_REFCLK_SEL rcw bit is used to determine DDR clock source
-If DDR_REFCLK_SEL rcw bit is 0, then DDR PLLs are driven in
 normal clocking mode by DDR_Reference clock

-If DDR_REFCLK_SEL rcw bit is 1, then DDR PLLs are driven in
 single source clocking mode by DIFF_SYSCLK

Add code to determine ddrclock based on DDR_REFCLK_SEL rcw bit.

Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com>
2014-01-02 14:10:13 -08:00
Masahiro Yamada
e8a8b8246a Makefile: Select objects by CONFIG_ rather than $(ARCH) or $(CPU)
Convert like follows:

 CPU mpc83xx  -> CONFIG_MPC83xx
 CPU mpc85xx  -> CONFIG_MPC85xx
 CPU mpc86xx  -> CONFIG_MPC86xx
 CPU mpc5xxx  -> CONFIG_MPC5xxx
 CPU mpc8xx   -> CONFIG_8xx
 CPU mpc8260  -> CONFIG_8260
 CPU ppc4xx   -> CONFIG_4xx
 CPU x86      -> CONFIG_X86
 ARCH x86     -> CONFIG_X86
 ARCH powerpc -> CONFIG_PPC

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2013-12-16 08:59:42 -05:00
Miao Yan
871a57bb81 common/cmd_bootm: extend do_bootm_vxworks to support the new VxWorks boot interface.
The next version VxWorks adopts device tree (for PowerPC and ARM) as its hardware
description mechanism. For PowerPC, the boot interface conforms to
the ePAPR standard, which is:

   void (*kernel_entry)(ulong fdt_addr,
          ulong r4 /* 0 */,
          ulong r5 /* 0 */,
          ulong r6 /* EPAPR_MAGIC */, ulong r7 /* IMA size */,
          ulong r8 /* 0 */, ulong r9 /* 0 */)

For ARM, the boot interface is:

   void (*kernel_entry)(void *fdt_addr)

Signed-off-by: Miao Yan <miao.yan@windriver.com>
[trini: Fix build error when !CONFIG_OF_FDT is set, typo on PowerPC,
missing extern ft_fixup_num_cores]
Signed-off-by: Tom Rini <trini@ti.com>
2013-12-16 08:59:05 -05:00
Masahiro Yamada
de04d64eda PowerPC: merge commonly-defined flags
PLATFORM_RELFLAGS += -meabi
PLATFORM_CPPFLAGS += -ffixed-r2
were defined in all arch/powerpc/${CPU}/config.mk.

This commit moves them to arch/powerpc/config.mk.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2013-12-13 09:17:32 -05:00
Prabhakar Kushwaha
e03c76c303 powerpc/mpc85xx: Update CONFIG_SYS_FSL_TBCLK_DIV for T1040
The default value of CONFIG_SYS_FSL_TBCLK_DIV is 16.

So, update its value as default.

Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Acked-by: York Sun <yorksun@freescale.com>
2013-12-11 11:12:54 -08:00
Shaohui Xie
c1015c67f4 powerpc/t4240: Add a frequency setting case for fman1
A new valid setting case added for fman1, it uses platform frequency.

Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Acked-by: York Sun <yorksun@freescale.com>
2013-12-11 11:12:04 -08:00
York Sun
1df99080cb powerpc/mpc8349: Use generic mpc85xx DDR driver
MPC8349 has been using mpc85xx DDR driver through a symbolic link to
mpc85xx_ddr_gen2.c. After consolidating the drivers to a single set
under driver/ddr/fsl/, the link is replaced by referring driver
directly. We now can simply enable the macro and use the driver.
Other mpc83xx SoCs still use their own driver.

Signed-off-by: York Sun <yorksun@freescale.com>
2013-12-04 14:55:05 -08:00
Zang Roy-R61911
e88f421e7a T4240: Address T4240/T4160 Rev2.0 DDR clock change
MEM_PLL_RAT on T4240/T4160 Rev2.0 uses a value which is half of Rev1.0.
It's 12 in Rev1.0, for Rev2.0 it uses 6.

Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Acked-by: York Sun <yorksun@freescale.com>
2013-12-04 14:54:42 -08:00
Dave Liu
24936ed1c9 powerpc/corenet: CPC1 speculation disable
In PBL RAMBOOT(SPI/SD/NAND boot) mode, CPC1 used as SRAM, should disable
CPC1 speculation and keep it till relocation. Otherwise, speculation
transactions will go to DDR controller, it will cause problem.

Signed-off-by: Dave Liu <daveliu@freescale.com>
Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Acked-by: York Sun <yorksun@freescale.com>
2013-12-04 14:54:10 -08:00
Shengzhou Liu
629d6b32d6 powerpc/mpc85xx: Add T2080/T2081 SoC support
Add support for Freescale T2080/T2081 SoC.

T2080 includes the following functions and features:
- Four dual-threads 64-bit Power architecture e6500 cores, up to 1.8GHz
- 2MB L2 cache and 512KB CoreNet platform cache (CPC)
- Hierarchical interconnect fabric
- One 32-/64-bit DDR3/3L SDRAM memory controllers with ECC and interleaving
- Data Path Acceleration Architecture (DPAA) incorporating acceleration
- 16 SerDes lanes up to 10.3125 GHz
- 8 mEMACs for network interfaces (four 1Gbps MACs and four 10Gbps/1Gbps MACs)
- High-speed peripheral interfaces
  - Four PCI Express controllers (two PCIe 2.0 and two PCIe 3.0 with SR-IOV)
  - Two Serial RapidIO 2.0 controllers/ports running at up to 5 GHz
- Additional peripheral interfaces
  - Two serial ATA (SATA 2.0) controllers
  - Two high-speed USB 2.0 controllers with integrated PHY
  - Enhanced secure digital host controller (SD/SDHC/SDXC/eMMC)
  - Enhanced serial peripheral interface (eSPI)
  - Four I2C controllers
  - Four 2-pin UARTs or two 4-pin UARTs
  - Integrated Flash Controller supporting NAND and NOR flash
- Three eight-channel DMA engines
- Support for hardware virtualization and partitioning enforcement
- QorIQ Platform's Trust Architecture 2.0

Differences between T2080 and T2081:
  Feature               T2080 T2081
  1G Ethernet numbers:  8     6
  10G Ethernet numbers: 4     2
  SerDes lanes:         16    8
  Serial RapidIO,RMan:  2     no
  SATA Controller:      2     no
  Aurora:               yes   no
  SoC Package:          896-pins 780-pins

Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Acked-by: York Sun <yorksun@freescale.com>
2013-11-25 11:44:25 -08:00
Shengzhou Liu
82a55c1ef8 net/fman: Add support for 10GEC3 and 10GEC4
There are more than two 10GEC in single FMAN in some SoCs(e.g. T2080).
This patch adds support for 10GEC3 and 10GEC4.

Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
2013-11-25 11:43:47 -08:00
York Sun
0b66513b27 Driver/IFC: Move Freescale IFC driver to a common driver
Freescale IFC controller has been used for mpc8xxx. It will be used
for ARM-based SoC as well. This patch moves the driver to driver/misc
and fix the header file includes.

Signed-off-by: York Sun <yorksun@freescale.com>
2013-11-25 11:43:47 -08:00
York Sun
9a17eb5b7e Driver/DDR: combine ccsr_ddr for 83xx, 85xx and 86xx
Fix ccsr_ddr structure to avoid using typedef. Combine DDR2 and DDR3
structure for 83xx, 85xx and 86xx.

Signed-off-by: York Sun <yorksun@freescale.com>
2013-11-25 11:43:46 -08:00
York Sun
5614e71b49 Driver/DDR: Moving Freescale DDR driver to a common driver
Freescale DDR driver has been used for mpc83xx, mpc85xx, mpc86xx SoCs.
The similar DDR controllers will be used for ARM-based SoCs.

Signed-off-by: York Sun <yorksun@freescale.com>
2013-11-25 11:43:43 -08:00
Tang Yuantian
f40fcfd911 mpc85xx: Fix the offset of register address error
The offset of register address within GPIO module is just
CONFIG_SYS_MPC85xx_GPIO_ADDR. So, fix it. The following platforms
are confirmed: MPC8572, P1023, P1020, P1022, P2020, P4080,
P5020, P5040, T4240, B4860.

Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com>
2013-11-25 11:40:05 -08:00
Masahiro Yamada
0a3656a42e powerpc: mpc824x: Do not create a symbolic link to bedbug_603e.c
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2013-11-17 14:11:33 -05:00
Masahiro Yamada
5cdee2d41a powerpc: mpc83xx: Do not create a symbolic link to ddr-gen2.c
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2013-11-17 14:11:33 -05:00
Masahiro Yamada
c64c5aa56a powerpc: mpc83xx: delete unused rules
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2013-11-17 14:11:33 -05:00
Masahiro Yamada
c54ecaa965 powerpc: move mpc8xxx entry under arch/powerpc/cpu/
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2013-11-17 14:11:31 -05:00
Masahiro Yamada
e5c5301f14 Makefile: make directories by Makefile.build
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2013-11-17 14:11:31 -05:00
Laurentiu TUDOR
51abee64ee powerpc/85xx: fix broken cpu "clock-frequency" property
When indexing freqProcessor[] we use the first
value in the cpu's "reg" property, which on
new e6500 cores IDs the threads.
But freqProcessor[] should be indexed with a
core index so, when fixing "the clock-frequency"
cpu node property, access the freqProcessor[]
with the core index derived from the "reg' property.
If we don't do this, last half of the "cpu" nodes
will have broken "clock-frequency" values.

Signed-off-by: Laurentiu Tudor <Laurentiu.Tudor@freescale.com>
Cc: York Sun <yorksun@freescale.com>
2013-11-13 12:41:28 -08:00
Laurentiu TUDOR
8f9fe660fc powerpc/t4240: fix per pci endpoint liodn offsets
Update the code that builds the pci endpoint liodn
offset list so that it doesn't overlap with other
liodns and doesn't generate negative offsets like:

  fsl,liodn-offset-list = <0 0xffffffcd 0xffffffcf
                             0xffffffd1 0xffffffd3
                             0xffffffd5 0xffffffd7
                             0xffffffd9 0xffffffdb>;

The update consists in adding a parameter to the
function that builds the list to specify the base
liodn.
On PCI v2.4 use the old base = 256 and, on PCI 3.0
where some of the PCIE liodns are larger than 256,
use a base = 1024. The version check is based on
the PCI controller's version register.

Signed-off-by: Laurentiu Tudor <Laurentiu.Tudor@freescale.com>
Cc: Scott Wood <scottwood@freescale.com>
Cc: York Sun <yorksun@freescale.com>
2013-11-13 12:41:28 -08:00
Laurentiu TUDOR
b4125a235e powerpc/t4240: set pcie liodn in the correct register
The liodn for the T4240's PCIE controller is no longer set
through a register in the guts register block but with one
in the PCIE register block itself.
Use the already existing SET_PCI_LIODN_BASE macro that puts
the liodn in the correct register.

Signed-off-by: Laurentiu Tudor <Laurentiu.Tudor@freescale.com>
Cc: Scott Wood <scottwood@freescale.com>
Cc: York Sun <yorksun@freescale.com>
2013-11-13 12:41:28 -08:00
ramneek mehresh
4e2e0df94d powerpc/83xx: Define USB1 and USB2 base addr for MPC834x
Define base addresse for both MPH(USB1) and DR(USB2) controllers
for MPC834x socs

Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com>
2013-11-13 12:41:28 -08:00
Priyanka Jain
2967af6816 powerpc/t1040: Update defines to support T1040SoC personalities
T1040 Soc has four personalities:
-T1040 (4 cores with L2 switch)
-T1042:Reduced personality of T1040 without L2 switch
-T1020:Reduced personality of T1040 with less cores(2 cores)
-T1022:Reduced personality of T1040 with 2 cores and without L2 switch

Update defines in arch/powerpc header files, Makefiles and in
driver/net/fm/Makefile to support all T1040 personalities

Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com>
[York Sun: fixed Makefiles]
Acked-by: York Sun <yorksun@freescale.com>
2013-11-13 12:41:08 -08:00
Wolfgang Denk
649acfe149 MPC824x: remove obsolete "PN62" board
The MPC824x processors have long reached EOL, and the PN62 board has
not seen any board-specific updates for more than a decade.  It is now
causing build issues.  Instead of wasting time on things nobody is
interested in any more, we rather drop this board.

Signed-off-by: Wolfgang Denk <wd@denx.de>
Cc: Wolfgang Grandegger <wg@grandegger.com>
cc: Tom Rini <trini@ti.com>
2013-11-11 14:46:24 -05:00
Masahiro Yamada
643aae1406 include: delete include/linux/config.h
Linux Kernel abolished include/linux/config.h long time ago.
(around version v2.6.18..v2.6.19)

We don't need to provide Linux copatibility any more.

This commit deletes include/linux/config.h
and fixes source files not to include this.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2013-11-08 15:25:13 -05:00
Masahiro Yamada
0f0f75774e cosmetic: remove empty lines at the top of file
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2013-11-08 09:41:37 -05:00
Masahiro Yamada
06c14117c4 powerpc: convert makefiles to Kbuild style
Note:
arch/powerpc/cpu/mpc8260/Makefile is originally like follows:

    ---<snip>---
    START   = start.o kgdb.o
    COBJS   = traps.o serial_smc.o serial_scc.o cpu.o cpu_init.o speed.o \
    ---<snip>---
    COBJS-$(CONFIG_ETHER_ON_SCC) = ether_scc.o
    ---<snip>---
    $(LIB): $(OBJS)
            $(call cmd_link_o_target, $(OBJS) $(obj)kgdb.o)

The link rule `$(call cmd_link_o_target, $(OBJS) $(obj)kgdb.o)'
is weird.
kbdg.o is not included in $(OBJS) but linked into $(LIB)
and $(LIB) is not dependent on kgdb.o.
(Broken dependency tracking)

So,
    START   = start.o kgdb.o
shoud have been
    START   = start.o
    SOBJS   = kgdb.o

That is why this commit adds kgdb.o to obj-y, not to extra-y.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Stefan Roese <sr@denx.de>
2013-10-31 13:26:44 -04:00
Valentin Longchamp
935b402eae fsl/mpc85xx: define common serdes_clock_to_string function
This allows to share some common code for the boards that use a corenet
base SoC.

Two different versions of the function are available in
fsl_corenet_serdes.c and fsl_corenet2_serdes.c files.

Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com>
[York Sun: fix t1040qds.c]
Acked-by: York Sun <yorksun@freescale.com>
2013-10-24 09:36:18 -07:00