Commit graph

3833 commits

Author SHA1 Message Date
Linus Walleij
d5f3d17ca6 armv8: semihosting: delete external interface
Now that loading files using semihosting can be done using
a command in standard scripts, and we have rewritten the boardfile
and added it to the Vexpress64, let's delete the external
interface to the semihosting file retrieveal and rely solely
on these commands, and staticize them inside that file so the
whole business is self-contained.

Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-03-28 12:07:46 -04:00
Linus Walleij
202a674bb8 armv8: semihosting: add a command to load semihosted images
Instead of sprinkling custom code and calls over the Vexpress64
boardfile, create a command that loads images using semihosting
just like we would load from flash memory of over the network,
using a special command:

    smhload <image> <address>

This will make it possible to remove some custom calls and
code and make the boot easier.

Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-03-28 12:07:45 -04:00
Linus Walleij
e769f68613 armv8: semihosting: do not inline trap call
The semihosting trap call does not like being inlined, probably
because that will mean register reordering screwing up the return
value in r0, so tag this function "noinline".

Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-03-28 12:07:45 -04:00
Masahiro Yamada
d6c418e4b8 ARM: bcm283x: move SoC headers to mach-bcm283x/include/mach
Move arch/arm/include/asm/arch-bcm283x/*
  -> arch/arm/mach-bcm283x/include/mach/*

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Acked-by: Stephen Warren <swarren@wwwdotorg.org>
2015-03-28 09:03:09 -04:00
Masahiro Yamada
ddf6bd4876 ARM: bcm283x: merge BCM2835/BCM2836 directories into mach-bcm283x
BCM2835 (used on Raspberry Pi) and BCM2836 (used on Raspberry Pi 2)
are similar enough.  One of the biggest differences is the ARM
processor.  It is reasonable to collect the source files into a
single place, arch/arm/mach-bcm283x/.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Acked-by: Stephen Warren <swarren@wwwdotorg.org>
2015-03-28 09:03:09 -04:00
Masahiro Yamada
326a682358 malloc_f: enable SYS_MALLOC_F by default if DM is on
This option has a bool type, not hex.
Fix it and enable it if CONFIG_DM is on because Driver Model always
requires malloc memory.  Devices are scanned twice, before/after
relocation.  CONFIG_SYS_MALLOC_F should be enabled to use malloc
memory before relocation.  As it is board-independent, handle it
globally.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Acked-by: Stephen Warren <swarren@wwwdotorg.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Acked-by: Robert Baldyga <r.baldyga@samsung.com>
2015-03-28 09:03:09 -04:00
Masahiro Yamada
91405b7fa9 malloc_f: remove redundant defalut values of CONFIG_SYS_MALLOC_F_LEN
The default value of CONFIG_SYS_MALLOC_F_LEN is defined by ./Kconfig
as 0x400.  Each defconfig or Kconfig need not repeat the same value.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Acked-by: Stephen Warren <swarren@wwwdotorg.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Acked-by: Robert Baldyga <r.baldyga@samsung.com>
2015-03-28 09:03:08 -04:00
Masahiro Yamada
0a12e6872e generic-board: move __HAVE_ARCH_GENERIC_BOARD to Kconfig
Move the option to Kconfig renaming it to CONFIG_HAVE_GENERIC_BOARD.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Alexey Brodkin <abrodkin@synopsys.com>
2015-03-28 09:03:08 -04:00
Rob Herring
7682a99826 remove unnecessary version.h includes
Various files are needlessly rebuilt every time due to the version and
build time changing. As version.h is not actually needed, remove the
include.

Signed-off-by: Rob Herring <robh@kernel.org>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Minkyu Kang <mk7.kang@samsung.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Tom Warren <twarren@nvidia.com>
Cc: Michal Simek <monstr@monstr.eu>
Cc: Macpaul Lin <macpaul@andestech.com>
Cc: Wolfgang Denk <wd@denx.de>
Cc: York Sun <yorksun@freescale.com>
Cc: Stefan Roese <sr@denx.de>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Cc: Simon Glass <sjg@chromium.org>
Cc: Philippe Reynes <tremyfr@yahoo.fr>
Cc: Eric Jarrige <eric.jarrige@armadeus.org>
Cc: "David Müller" <d.mueller@elsoft.ch>
Cc: Phil Edworthy <phil.edworthy@renesas.com>
Cc: Robert Baldyga <r.baldyga@samsung.com>
Cc: Torsten Koschorrek <koschorrek@synertronixx.de>
Cc: Anatolij Gustschin <agust@denx.de>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Reviewed-by: Łukasz Majewski <l.majewski@samsung.com>
2015-03-24 10:50:50 -04:00
Masahiro Yamada
90e357efed ARM: UniPhier: remove unnecessary ifdef conditional
The callee (arch/arm/lib/cache-cp15.c) has a #ifdef
CONFIG_SYS_DCACHE_OFF conditional.  The same conditional in the
caller (arch/arm/mach-uniphier/cache_uniphier.c) is redundant.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2015-03-24 00:16:02 +09:00
Masahiro Yamada
a509161a21 ARM: UniPhier: disable L2 cache by lowlevel_init of U-Boot proper
The L2 cache is used as a temporary SRAM on SPL.
Now the secondary CPUs store the necessary code for jumping to
Linux on their L1 I-caches.  So, the L2 cache can be disabled
much earlier, at the very entry of U-Boot proper (lowlevel_init).
This makes the boot sequence clearer.
Also, as the L1 cache has been disabled by the start.S,
enable_caches() does not need to do it again.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2015-03-24 00:15:58 +09:00
Masahiro Yamada
62118b7b01 ARM: UniPhier: optimize kicking secondary CPUs code
Currently, the secondary CPU(s) are kicked three times:
Boot ROM ---(kick)--> SPL ---(kick)--> U-boot ---(kick)--> Linux.
It makes the boot sequence very complicated.

This commit merges the first and the second kicks, so the secondary
CPU(s) can directly jump from SPL to Linux.
arch/arm/mach-uniphier/smp.S is no longer necessary.

Linux boot test passed.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2015-03-24 00:15:55 +09:00
Masahiro Yamada
4d13b1b708 ARM: UniPhier: fix typos in comments
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2015-03-24 00:15:52 +09:00
Masahiro Yamada
def3feb8cb ARM: UniPhier: add empty lowlevel_init to U-boot proper
To remove the ifdef conditional of CONFIG_SKIP_LOWLEVEL_INIT,
add late_lowlevel_init.S to U-Boot proper.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2015-03-24 00:15:48 +09:00
Masahiro Yamada
ce3a63905b ARM: UniPhier: use CONFIG_SPL_STACK to define SPL stack pointer
Ifdef conditionals for CONFIG options are not Kconfig-friendly.
Instead, define CONFIG_SPL_STACK to prepare for Kconfig moves.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2015-03-24 00:15:38 +09:00
Masahiro Yamada
499785b970 ARM: UniPhier: enable Driver Model and UART on SPL
Enable CONFIG_SPL_DM and CONFIG_SPL_SERIAL_SUPPORT, which provide
Driver Model UART support on SPL.

CONFIG_SYS_SPL_MALLOC_{START,SIZE} should be dropped because simple
malloc is preferred on SPL.  Dlmalloc requires some static variables
on .data section that is not available yet for NOR boot mode etc.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2015-03-24 00:15:35 +09:00
Masahiro Yamada
7d1a3a67bc ARM: UniPhier: move UART pin settings to SPL
The UniPhier platform is going to enable Driver Model and UART
support on SPL.  Move UART pin settings to early_pin_init(),
which is called from SPL.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2015-03-24 00:15:28 +09:00
Masahiro Yamada
94ab98bb1c ARM: UniPhier: move platform devices to SPL
Since we do not have OF_CONTROL support for SPL, platform devices
are necessary to enable Driver Model on SPL.

To prepare for that, move platdevice.o to SPL and enable it by
CONFIG_SPL_DM.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2015-03-24 00:15:24 +09:00
Masahiro Yamada
d5e7305013 ARM: UniPhier: include PH1-LD4 Makefile from PH1-sLD8
The two Makefiles arch/arm/mach-uniphier/{ph1-ld4,ph1-sld8}/Makefile
are completely the same.  We can improve the maintainability by
having one to include the other.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2015-03-24 00:15:21 +09:00
Masahiro Yamada
4ab994b16a ARM: UniPhier: remove unnecessary CONFIG_SYS_SOC
Since commit a86ac9540e (ARM: UniPhier: include <mach/*.h> instead
of <asm/arch/*.h>), UniPhier platform does not need the symbolic
link arch/arm/include/asm.  This option is not necessary either.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2015-03-24 00:15:10 +09:00
Tom Rini
e6f4042a04 Merge branch 'master' of git://git.denx.de/u-boot-atmel 2015-03-20 07:01:00 -04:00
Bo Shen
8e7a96364b ARM: atmel: sama5d4: set non-secured for peripherals
When access the programmable secure peripherals address space,
it needs set them to non-secured.

Signed-off-by: Bo Shen <voice.shen@atmel.com>
2015-03-18 23:36:10 +01:00
Bo Shen
993ea97e76 ARM: atmel: armv7: move spl lds to armv7 directory
As the u-boot-spl.lds is used only for armv7 SoCs (includes
sama5d3 and sama5d4), so move it to armv7 directory.

Signed-off-by: Bo Shen <voice.shen@atmel.com>
2015-03-18 23:36:07 +01:00
Wu, Josh
111ec4c652 ARM: at91: at91sam9rlek: add mci support
This patch enable the MCI support for at91sam9rlek board.

Signed-off-by: Josh Wu <josh.wu@atmel.com>
[rebase on ToT]
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
2015-03-18 23:36:01 +01:00
Tom Rini
a538ae997a Merge branch 'master' of git://www.denx.de/git/u-boot-imx 2015-03-18 07:07:43 -04:00
Tom Rini
a74ef40a47 Merge branch 'master' of git://git.denx.de/u-boot-uniphier 2015-03-15 14:31:39 -04:00
Masahiro Yamada
6462cdedc2 ARM: UniPhier: adjust device trees for business transfer
Panasonic's System LSI products, UniPhier SoC family, have been
transferred to Socionext Inc.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2015-03-15 13:37:00 +09:00
Nishanth Menon
cdef0b3f3a ARM: OMAP3: rx51: Enable workaround for ARM errata 454179, 430973, 621766
RX51 has a secure logic which uses different parameters compared to
traditional implementation. So, make the generic secure acr write
over-ride-able by board file and refactor rx51 code to use this.

While at it, enable the OMAP3 specific errata code for 454179, 430973,
621766.

Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2015-03-13 09:29:33 -04:00
Nishanth Menon
c6f90e1418 ARM: OMAP3: Enable workaround for ARM errata 454179, 430973, 621766
Enable the OMAP3 specific errata code for 454179, 430973, 621766
and while at it, remove legacy non-revision checked errata logic.

Signed-off-by: Nishanth Menon <nm@ti.com>
Tested-by: Matt Porter <mporter@konsulko.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2015-03-13 09:29:24 -04:00
Nishanth Menon
fc7368ec85 ARM: OMAP5 / DRA7: Setup L2 Aux Control Register with recommended configuration
Update to existing recommendation for L2ACTLR configuration to prevent
system instability and optimize performance.

These apply to both OMAP5 and DRA7.

Reported-by: Vivek Chengalvala <vchengalvala@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2015-03-13 09:29:13 -04:00
Praveen Rao
5f603761c3 ARM: DRA7 / OMAP5: Add workaround for ARM errata 798870
This patch enables the workaround for ARM errata 798870 for OMAP5 /
DRA7 which says "If back-to-back speculative cache line fills (fill
A and fill B) are issued from the L1 data cache of a CPU to the
L2 cache, the second request (fill B) is then cancelled, and the
second request would have detected a hazard against a recent write or
eviction (write B) to the same cache line as fill B then the L2 logic
might deadlock."

An l2auxctlr accessor implementation for OMAP5 and DRA7 is introduced
here as well.

Signed-off-by: Praveen Rao <prao@ti.com>
Signed-off-by: Angela Stegmaier <angelabaker@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Tested-by: Matt Porter <mporter@konsulko.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2015-03-13 09:29:01 -04:00
Nishanth Menon
49ec949091 ARM: OMAP3: Get rid of omap3_gp_romcode_call and replace with omap_smc1
omap_smc1 is now generic enough to remove duplicate
omap3_gp_romcode_call logic that omap3 introduced.

As part of this change, move to using the generic lowlevel_init.S for
omap3 as well.

Signed-off-by: Nishanth Menon <nm@ti.com>
Tested-by: Matt Porter <mporter@konsulko.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2015-03-13 09:29:00 -04:00
Nishanth Menon
987ec5851c ARM: OMAP3: Rename omap3.h to omap.h to be generic as all SoCs
This is in preperation of using generic cross OMAP code.

Signed-off-by: Nishanth Menon <nm@ti.com>
Tested-by: Matt Porter <mporter@konsulko.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2015-03-13 09:28:57 -04:00
Nishanth Menon
6d8abe6a8a ARM: OMAP: Change set_pl310_ctrl_reg to be generic
set_pl310_ctrl_reg does use the Secure Monitor Call (SMC) to setup
PL310 control register, however, that is something that is generic
enough to be used for OMAP5 generation of processors as well. The only
difference being the service being invoked for the function.

So, convert the service to a macro and use a generic name (same as
that used in Linux for some consistency). While at that, also add a
data barrier which is necessary as per recommendation.

While at this, smc #0 is maintained as handcoded assembly thanks to
various gcc version eccentricities, discussion thread:
http://marc.info/?t=142542166800001&r=1&w=2

Signed-off-by: Nishanth Menon <nm@ti.com>
Tested-by: Matt Porter <mporter@konsulko.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2015-03-13 09:28:55 -04:00
Nishanth Menon
9b4d65f918 ARM: Introduce erratum workaround for 621766
621766: Under a specific set of conditions, executing a sequence of
	NEON or vfp load instructions can cause processor deadlock
Impacts: Every Cortex-A8 processors with revision lower than r2p1
Work around: Set L1NEON to 1

Based on ARM errata Document revision 20.0 (13 Nov 2010)

Signed-off-by: Nishanth Menon <nm@ti.com>
Tested-by: Matt Porter <mporter@konsulko.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2015-03-13 09:28:53 -04:00
Nishanth Menon
5902f4ce0f ARM: Introduce erratum workaround for 430973
430973: Stale prediction on replaced inter working branch causes
	Cortex-A8 to execute in the wrong ARM/Thumb state
Impacts: Every Cortex-A8 processors with revision lower than r2p1
Work around: Set IBE to 1

Based on ARM errata Document revision 20.0 (13 Nov 2010)

Signed-off-by: Nishanth Menon <nm@ti.com>
Tested-by: Matt Porter <mporter@konsulko.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2015-03-13 09:28:52 -04:00
Nishanth Menon
b45c48a7c3 ARM: Introduce erratum workaround for 454179
454179: Stale prediction may inhibit target address misprediction on
	next predicted taken branch
Impacts: Every Cortex-A8 processors with revision lower than r2p1
Work around:  Set IBE and disable branch size mispredict to 1

Also provide a hook for SoC specific handling to take place if needed.

Based on ARM errata Document revision 20.0 (13 Nov 2010)

Signed-off-by: Nishanth Menon <nm@ti.com>
Tested-by: Matt Porter <mporter@konsulko.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2015-03-13 09:28:48 -04:00
Nishanth Menon
c616a0df29 ARM: Introduce erratum workaround for 798870
Add workaround for Cortex-A15 ARM erratum 798870 which says
"If back-to-back speculative cache line fills (fill A and fill B) are
issued from the L1 data cache of a CPU to the L2 cache, the second
request (fill B) is then cancelled, and the second request would have
detected a hazard against a recent write or eviction (write B) to the
same cache line as fill B then the L2 logic might deadlock."

Implementations for SoC families such as Exynos, OMAP5/DRA7 etc
will be widely different.

Every SoC has slightly different manner of setting up access to L2ACLR
and similar registers since the Secure Monitor handling of Secure
Monitor Call(smc) is diverse. Hence an weak function is introduced
which may be overriden to implement SoC specific accessor implementation.

Based on ARM errata Document revision 18.0 (22 Nov 2013)

Signed-off-by: Nishanth Menon <nm@ti.com>
Tested-by: Matt Porter <mporter@konsulko.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2015-03-13 09:28:29 -04:00
Dirk Behme
9d16c52f62 mx6: soc: Switch to cold reset
Disable the warm reset and enable the cold reset for a more reliable
restart ('reset'). This is taken from the Linux kernel, see imx_src_init()
in arch/arm/mach-imx/src.c.

Signed-off-by: Dirk Behme <dirk.behme@de.bosch.com>
2015-03-13 13:29:42 +01:00
Peng Fan
0c1842a01f imx:mx6 remove duplicated includes
There is no need to include asm/bootm.h twice, so remove one.

Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
2015-03-13 13:28:04 +01:00
Tom Rini
b79dadf846 Merge branch 'master' of git://git.denx.de/u-boot-tegra
Conflicts:
	README

Signed-off-by: Tom Rini <trini@konsulko.com>
2015-03-10 19:09:18 -04:00
Linus Walleij
23b5877c64 armv8/vexpress64: make multientry conditional
While the Freescale ARMv8 board LS2085A will enter U-Boot both
on a master and a secondary (slave) CPU, this is not the common
behaviour on ARMv8 platforms. The norm is that U-Boot is entered
from the master CPU only, while the other CPUs are kept in
WFI (wait for interrupt) state.

The code determining which CPU we are running on is using the
MPIDR register, but the definition of that register varies with
platform to some extent, and handling multi-cluster platforms
(such as the Juno) will become cumbersome. It is better to only
enable the multiple entry code on machines that actually need
it and disable it by default.

Make the single entry default and add a special
ARMV8_MULTIENTRY KConfig option to be used by the
platforms that need multientry and set it for the LS2085A.
Delete all use of the CPU_RELEASE_ADDR from the Vexpress64
boards as it is just totally unused and misleading, and
make it conditional in the generic start.S code.

This makes the Juno platform start U-Boot properly.

Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-03-09 11:13:29 -04:00
Tom Rini
dd09f7e73c ARM: PSCI: Rework the DT handler slightly
The way the PSCI DT update happens currently means we pull in
<asm/armv7.h> everywhere, including on ARMv8 and that in turn brings in
<asm/io.h> for some non-PSCI related things that header needs to deal
with.

To fix this, we rework the hook slightly.  A good portion of
arch/arm/cpu/armv7/virt-dt.c is common looking and I hope that when PSCI
is needed on ARMv8 we can re-use this by and large.  So rename the
current hook to psci_update_dt(), move the prototype to <asm/psci.h> and
add an #ifdef that will make re-use later easier.

Reported-by: York Sun <yorksun@freescale.com>
Cc: Marc Zyngier <marc.zyngier@arm.com>
Cc: York Sun <yorksun@freescale.com>
Cc: Ian Campbell <ijc@hellion.org.uk>
Cc: Hans de Goede <hdegoede@redhat.com>
Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
Signed-off-by: Tom Rini <trini@konsulko.com>
Acked-by: York Sun <yorksun@freescale.com>
2015-03-09 11:13:29 -04:00
Przemyslaw Marczak
114c86d826 arm: relocation: clear .bss section with arch memset if defined
For ARM architecture, enable the CONFIG_USE_ARCH_MEMSET/MEMCPY,
will highly increase the memset/memcpy performance. This is able
thanks to the ARM multiple register instructions.

Unfortunatelly the relocation is done without the cache enabled,
so it takes some time, but zeroing the BSS memory takes much more
longer, especially for the configs with big static buffers.

A quick test confirms, that the boot time improvement after using
the arch memcpy for relocation has no significant meaning.
The same test confirms that enable the memset for zeroing BSS,
reduces the boot time.

So this patch enables the arch memset for zeroing the BSS after
the relocation process. For ARM boards, this can be enabled
in board configs by defining: 'CONFIG_USE_ARCH_MEMSET'.

This was tested on Trats2.
A quick test with trace. Boot time from start to main_loop() entry:
- ~1384ms - before this change
-  ~888ms - after this change

Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Tom Rini <trini@konsulko.com>
2015-03-09 11:13:28 -04:00
Tom Rini
65994d0494 Merge git://git.denx.de/u-boot-socfpga 2015-03-05 20:50:31 -05:00
Tom Rini
1c6f6a6ef9 Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx 2015-03-05 20:50:30 -05:00
Ash Charles
b050898efa omap: gpmc: 'nandecc sw' can use HAM1 or BCH8
The 'nandecc sw' command selects a software-based error correction
algorithm.  By default, this is OMAP_ECC_HAM1_CODE_SW but some
platforms use OMAP_ECC_BCH8_CODE_HW_DETECTION_SW as their
software-based correction algorithm.  Allow a user to be specific e.g.
 # nandecc sw <hamming|bch8>
where 'hamming' is still the default.

Note: we don't just use CONFIG_NAND_OMAP_ECCSCHEME as it might be set
      to a hardware-based ECC scheme---a little strange when the user
      has requested 'sw' ECC.

Signed-off-by: Ash Charles <ashcharles@gmail.com>
2015-03-05 20:49:43 -05:00
Gilles Gameiro
a2bc4321e4 Adding Support for BAV335x boards 2015-03-05 20:13:21 -05:00
Albert ARIBAUD \(3ADEV\)
d275c40c69 omap3: add support for QUIPOS Cairo board.
This patch extends OMAP3 support for AM/DM37xx and
introduces the AM3703-based Quipos Cairo board.

Signed-off-by: Albert ARIBAUD (3ADEV) <albert.aribaud@3adev.fr>
Reviewed-by: Simon Glass <sjg@chromium.org>
2015-03-05 20:13:21 -05:00
gaurav rana
e04916a721 SECURE_BOOT : enable esbc_validate command for powerpc and arm platforms.
esbc_validate command uses various IP Blocks: Security Monitor, CAAM block
and SFP registers. Hence the respective CONFIG's are enabled.

Apart from these CONFIG_SHA_PROG_HW_ACCEL and CONFIG_RSA are also enabled.

Signed-off-by: Gaurav Rana <gaurav.rana@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-03-05 12:04:59 -08:00