Commit graph

39226 commits

Author SHA1 Message Date
Stephen Warren
20bbde0628 ARM: tegra: add PCIe controller to Tegra186 SoC DT
The Tegra186 PCIe DT content is almost identical to previous chips, except
that the:

- There are 3 ports instead of 2.
- Some physical addresses have moved.
- PHY programming is handled by firmware, so CCPLEX DTs don't need to
  reference any PHY.
- The power domain is explicitly represented in DT. This change is
  mandatory for Tegra186 since standard power domain APIs are used, and
  should be made to the DT for older SoCs, although we get away without
  doing so since U-Boot currently uses custom APIs that hard-code power
  domain IDs.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2016-08-04 13:36:59 -07:00
Stephen Warren
23ab5bda7e ARM: tegra: add BPMP I2C to Tegra186 device tree
This allows the BPMP I2C device to be instantiated, which makes it
available to other drivers and the user.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2016-08-04 13:36:59 -07:00
Stephen Warren
19014203c4 ARM: tegra: add BPMP and dependencies to Tegra186 DT
This adds the DT content that's needed to allow board DTs to enable use
of BPMP, clocks, resets, GPIOs, eMMC, and SD cards.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2016-08-04 13:36:59 -07:00
Stephen Warren
6e7a11e64e dt-bindings: add Tegra186 BPMP I2C binding
In Tegra186, the BPMP (Boot and Power Management Processor) owns certain
HW devices, such as the I2C controller for the power management I2C bus.
Software running on other CPUs must perform IPC to the BPMP in order to
execute transactions on that I2C bus. This binding describes an I2C bus
that is accessed in such a fashion.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2016-08-04 13:36:59 -07:00
Stephen Warren
390ae57c76 dt-bindings: allow child nodes inside the Tegra BPMP
The BPMP implements some services which must be represented by separate
nodes. For example, it can provide access to certain I2C controllers, and
the I2C bindings represent each I2C controller as a device tree node.
Update the binding to describe how the BPMP supports this.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2016-08-04 13:36:59 -07:00
Stephen Warren
7b9cb49405 ARM: tegra: add BPMP DT bindings
The Tegra BPMP (Boot and Power Management Processor) is a separate
auxiliary CPU embedded into Tegra to perform power management work, and
controls related features such as clocks, resets, power domains, PMIC I2C
bus, etc. These bindings dictate how to represent the BPMP in device tree.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2016-08-04 13:36:58 -07:00
Stephen Warren
729c2db7a9 ARM: tegra: adapt to latest HSP DT binding
The DT binding for the Tegra186 HSP module apparently wasn't quite final
when I posted initial U-Boot support for it. Add the final DT binding doc
and adapt all code and DT files to match it.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2016-08-04 13:36:58 -07:00
Scott Wood
e1efe43c71 powerpc/86xx: Increase boot map size to 256 MiB
This is what Linux maps on classic PPC during boot, and modern kernel
images don't fit within the current 8 MiB uncompressed limit.

Adjust image load addresses to be above this limit to avoid conflicts.

Signed-off-by: Scott Wood <oss@buserror.net>
Reviewed-by: York Sun <york.sun@nxp.com>
2016-08-03 18:02:29 -07:00
Tom Rini
ad6a303c57 Merge git://git.denx.de/u-boot-fsl-qoriq 2016-08-02 20:45:24 -04:00
Hou Zhiqiang
ab01ef5fa6 ARMv8/fsl-ppa: Consolidate PPA image stored-media flag for XIP
The PPA binary may be stored on QSPI flash instead of NOR.
So, deprecated CONFIG_SYS_LS_PPA_FW_IN_NOR in favour of
CONFIG_SYS_LS_PPA_FW_IN_XIP to prevent fragmentation of code
by addition of a new QSPI specific flag.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Signed-off-by: Abhimanyu Saini <abhimanyu.saini@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2016-08-02 09:51:29 -07:00
Hou Zhiqiang
bded21895d arm/PSCI: Add support for creating ARMv7 PSCI version 1.0 DT node
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2016-08-02 09:50:00 -07:00
Hou Zhiqiang
2c77416544 arm/PSCI: Fixed the backward compatiblity issue
Appended the compatible strings of old version PSCI to the latest
version supported. And there are some psci functions' property must
be added to DT only for psci version 0.1, including cpu_on, cpu_off,
cpu_suspend, migrate.

Note, ARMv8 Secure Firmware Framework doesn't support PSCI ver 0.1.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2016-08-02 09:47:49 -07:00
Hou Zhiqiang
388aabc85d arm/PSCI: Removed unused code
Identify the PSCI node only by its name, so removed the code finding
it by compatible string.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2016-08-02 09:47:35 -07:00
York Sun
8936691ba6 driver/ddr/fsl: Fix timing_cfg_2
Commit 5605dc6 tried to fix wr_lat bit in timing_cfg_2, but the
change was wrong. wr_lat has 5 bits with MSB at [13] and lower
4 bits at [9:12], in big-endian convention.

Signed-off-by: York Sun <york.sun@nxp.com>
Reported-by: Thomas Schaefer <Thomas.Schaefer@kontron.com>
2016-08-02 09:47:34 -07:00
York Sun
473af36a88 board/freescale: Update MAINTAINERS files
Update maintainers for secure boot targets.

Signed-off-by: York Sun <york.sun@nxp.com>
2016-08-02 09:47:34 -07:00
Wenbin Song
6ffc490541 armv8: ls1043a: enable pxe commands
Enable pxe command for ls1043ardb and ls1043aqds.

Signed-off-by: Wenbin Song <wenbin.song@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2016-08-02 09:46:07 -07:00
Prabhakar Kushwaha
37eac3f460 armv8: ls1012a: Update Refresh cycle for DDR
Refresh cycle value must be selected based on the frequency
of DDR. tREFI = 7.8 us as per JEDEC. The value for MDREF[REF_CNT]
should be based on round up (tREFI/tCK) formula. For 500MHz, mdref
value should be 0x0f3c8000.

Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2016-08-02 09:46:02 -07:00
Prabhakar Kushwaha
9c3fca2a79 armv8: ls1012a: Enable DDR row-bank-column decoding
Enable DDR row-bank-column decoding to decode DDR address as
row-bank-column instead of bank-row-column for improving
performance of serial data transfers.

Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2016-08-02 09:45:56 -07:00
Prabhakar Kushwaha
3b4dbd37dc board: ls1012aqds: Update LBMAP_MASK and RST_CTL_RESET
qixis_reset altbank usagge ~QIXIS_LBMAP_MASK in code. So define
inverse value QIXIS_LBMAP_MASK.

Also, update QIXIS_RST_CTL_RESET value to keep RST_CTL[REQ_MOD]
as 0b11 i.e. PORESET during qixis_reset

Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2016-08-02 09:45:48 -07:00
Sumit Garg
7fe1d6a410 crypto/fsl: Update blob cmd to accept 64bit addresses
Update blob cmd to accept 64bit source, key modifier and destination
addresses. Also correct output result print format for fsl specific
implementation of blob cmd.

Signed-off-by: Sumit Garg <sumit.garg@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2016-08-02 09:45:39 -07:00
Yunhui Cui
04e5c6d9cc driver: spi: fsl-qspi: remove compile Warnings
Warnins log:
drivers/spi/fsl_qspi.c: In function ‘qspi_ahb_read’:
drivers/spi/fsl_qspi.c:400:16: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast]
  memcpy(rxbuf, (u8 *)(priv->cur_amba_base + priv->sf_addr), len);

Signed-off-by: Yunhui Cui <yunhui.cui@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2016-08-02 09:45:13 -07:00
York Sun
f3dbf1f0c9 powerpc/mpc85xx: Update erratum workaround for A006379
Update erratum workaround for A006379 to set register CPCHDBCR0
with value 0x001e0000, replacing the old value 0x003c0000.

Signed-off-by: York Sun <york.sun@nxp.com>
Reported-by: Dave Liu <dave.liu@nxp.com>
2016-08-02 09:43:13 -07:00
Tom Rini
7351bf2b5b Merge branch 'master' of git://www.denx.de/git/u-boot-microblaze 2016-08-02 07:32:30 -04:00
Jaehoon Chung
dbc39699d0 MAINTAINERS, git-mailrc: Update the mmc maintainer
Update the mmc maintainer from Pantelis to me.

Acked-by: Pantelis Antoniou <pantelis.antoniou@konsulko.com>
Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
2016-08-02 07:30:56 -04:00
Michal Simek
28559d4c93 ARM64: zynqmp: Do not enable DM_MMC by default
The patch:
"dm: mmc: zynq: Convert zynq to use driver model for MMC"
(sha1: 329a449f2c)
added dependency on enabling some MMC options by default.
There are minimal ZynqMP configurations which require
only minimal configurations to be enabled to keep u-boot size
as lower as possible.

Move options to defconfig instead.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2016-08-02 07:19:09 +02:00
Soren Brinkmann
8fbf678ba0 ARM64: zynqmp: Fix stack pointer initialization
This partly reverts commit:
"ARM64: zynqmp: Add SPL support support"
(sha1: e6a9ed04e7)

Stack can rewrite ATF code.

Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2016-08-02 07:19:09 +02:00
Michal Simek
0cfd0a976f ARM64: zynqmp: Define config USB_STORAGE through defconfig
Define config USB_STORAGE through defconfig for all
Xilinx ZynqMP boards.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2016-08-02 07:19:05 +02:00
Michal Simek
3c70349f8e xilinx: Sync defconfigs with the latest Kconfig layout
Update Microblaze, Zynq and ZynqMP defconfigs to reflect
latest Kconfig changes.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2016-08-02 06:54:42 +02:00
Michal Simek
33986e2c31 ARM64: zynqmp: Wire up PSCI reset
Using PSCI to reset the system.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2016-08-02 06:54:34 +02:00
Michal Simek
a9022b017a ARM64: zynqmp: Add u-boot,dm-pre-reloc to clk nodes
Serial driver is getting clk information via DT that's why
also clk node needs to have this flag.

Different behavior was introduced by:
"dm: Use dm_scan_fdt_dev() directly where possible"
(sha1: 911954859d)
where simple-bus driver starts to call dm_scan_fdt_dev() which has
additional logic around pre_reloc_only parameter which exclude
clk nodes.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2016-08-01 08:35:02 +02:00
Simon Glass
6de80f2196 Drop references to MAKEALL in the documentation
It is confusing to mention MAKEALL when it is not the normal way of building
U-Boot anymore. Update the documentation to suit.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
2016-07-31 19:37:08 -06:00
Simon Glass
c8a3777c51 Drop the MAKEALL tool
Buildman has been around for 3 years now. It has had a lot of use and
testing. Perhaps it is time to remove MAKEALL.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
2016-07-31 19:37:08 -06:00
Simon Glass
c8d7393b73 buildman: Add a quick-start note
For those who just want to build a board, it is useful to see a quick hint
right at the start of the documentation. Add a few commands showing how to
download toolchains and build a board.

Signed-off-by: Simon Glass <sjg@chromium.org>
2016-07-31 19:37:08 -06:00
Simon Glass
c8785c5b49 buildman: Avoid overwriting existing toolchain entries
The current code for setting up the toolchain config always writes the new
paths to an item called 'toolchain'. This means that it will overwrite any
existing toolchain item with the same name. In practice, this means that:

   buildman --fetch-arch all

will fetch all toolchains, but only the path of the final one will be added
to the config. This normally works out OK, since most toolchains are the
same version (e.g. gcc 4.9) and will be found on the same path. But it is
not correct and toolchains for archs which don't use the same version will
not function as expected.

Adjust the code to use a complete glob of the toolchain path.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
2016-07-31 19:37:08 -06:00
Simon Glass
7e92e46e63 buildman: Drop the toolchain error when downloading toolchains
It doesn't make sense to complain about missing toolchains when the
--fetch-arch option is being used. The user is presumably aware that there
is a toolchain problem and is actively correcting it by running with this
option.

Refactor the code to avoid printing this confusing message.

Signed-off-by: Simon Glass <sjg@chromium.org>
2016-07-31 19:37:08 -06:00
Simon Glass
2289b2763c buildman: Fix a typo in TestSettingsHasPath()
The function comment should say 'buildman'. Fix it.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
2016-07-31 19:37:08 -06:00
Simon Glass
713bea38dd buildman: Improve the toolchain progress/error output
Use colour to make it easier to see what is going on. Also print a message
before downloading a new toolchain. Mention --fetch-arch in the message that
is shown when there are no available toolchains, since this is the quickest
way to resolve the problem.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
2016-07-31 19:37:08 -06:00
Simon Glass
80e6a48750 buildman: Allow the toolchain error to be suppressed
When there are no toolchains a warning is printed. But in some cases this is
confusing, such as when the user is fetching new toolchains.

Adjust the function to supress the warning in this case.

Signed-off-by: Simon Glass <sjg@chromium.org>
2016-07-31 19:37:08 -06:00
Simon Glass
bd6f5d98de buildman: Fix the 'help' test to use the correct path
When buildman is run via a symlink, this test fails. Fix it to work the same
way as buildman itself.

Signed-off-by: Simon Glass <sjg@chromium.org>
2016-07-31 19:37:08 -06:00
Simon Glass
8e605a5e3e buildman: Automatically create a config file if needed
If there is no ~/.buildman file, buildman currently complains and exists. To
make things a little more friendly, create an empty one automatically. This
will not allow things to be built, but --fetch-arch can be used to handle
that.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
2016-07-31 19:37:08 -06:00
Simon Glass
8ea42101d2 buildman: Tidy up the README a little
Tidy up some problems found by a recent review.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
2016-07-31 19:37:08 -06:00
Michal Simek
e2f88dfd2d libfdt: Introduce new ARCH_FIXUP_FDT option
Add new Kconfig option to disable arch_fixup_fdt() calls for cases where
U-Boot shouldn't update memory setup in DTB file.
One example of usage of this option is to boot OS with different memory
setup than U-Boot use.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Acked-by: Simon Glass <sjg@chromium.org>
2016-07-31 19:37:08 -06:00
Tom Rini
26fb8db0f4 Merge git://git.denx.de/u-boot-rockchip 2016-07-31 20:31:13 -04:00
Hans de Goede
fcada3b05e sunxi: Re-enable h3 emac support
With the recent bug fixes for the sun8i_emac driver all known issues
are resolved, so we can re-enable the driver.

While at it, also enable the emac on the Orange Pi One.

Cc: Chen-Yu Tsai <wens@csie.org>
Cc: Corentin LABBE <clabbe.montjoie@gmail.com>
Cc: Amit Singh Tomar <amittomer25@gmail.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Acked-by: Jagan Teki <jteki@openedev.com>
2016-07-31 21:45:47 +02:00
Hans de Goede
4069437dfb net: sun8i_emac: Fix DMA alignment issues with the rx / tx buffers
This fixes the following CACHE warnings when using sun8i_emac:

=> dhcp
BOOTP broadcast 1
BOOTP broadcast 2
CACHE: Misaligned operation at range [7bf594a8, 7bf59628]
BOOTP broadcast 3
CACHE: Misaligned operation at range [7bf59c90, 7bf59e10]
CACHE: Misaligned operation at range [7bf5a478, 7bf5a5f8]
DHCP client bound to address 10.42.43.80 (1009 ms)

Note this commit also changes the max rx size from 2024 to 2044,
matching what the kernel driver uses.

Cc: Chen-Yu Tsai <wens@csie.org>
Cc: Corentin LABBE <clabbe.montjoie@gmail.com>
Cc: Amit Singh Tomar <amittomer25@gmail.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
2016-07-31 21:45:46 +02:00
Hans de Goede
3f8ea3b06e sunxi: On newer SoCs use words 1-3 instead of just word 3 from the SID
It seems that bytes 13-14 of the SID / bytes 1-2 from word 3 of the SID
are always 0 on H3 making it a poor candidate to use as source for the
serialnr / mac-address, and the other non constant words (1 and 2) also
have quite a few bits which are the same for some boards,

This commits switches to using the crc32 of words 1 - 3 to get a
more unique value for the mac-address / serialnr.

Cc: Chen-Yu Tsai <wens@csie.org>
Cc: Corentin LABBE <clabbe.montjoie@gmail.com>
Cc: Amit Singh Tomar <amittomer25@gmail.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
2016-07-31 21:45:39 +02:00
Hans de Goede
97322c3e07 sunxi: Ensure that the NIC specific bytes of the mac are not all 0
On 2 of my H3 boards bytes 13-15 of the SID are all 0 leading to
the NIC specific bytes of the mac all being 0, which leads to the
boards not getting an ipv6 address from the dhcp server.

This commits adds a check to ensure this does not happen.

Cc: Chen-Yu Tsai <wens@csie.org>
Cc: Corentin LABBE <clabbe.montjoie@gmail.com>
Cc: Amit Singh Tomar <amittomer25@gmail.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
2016-07-31 21:45:34 +02:00
Chen-Yu Tsai
3e5e274aed sunxi: Hummingbird_A31_defconfig: Drop MACPWR option
MACPWR was used to bring the Ethernet PHY out of reset. The designware
driver now supports the phy reset gpio binding, so this is no longer
needed. In fact in requesting the same GPIO, it makes the designware
driver fail to probe.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
2016-07-31 21:45:12 +02:00
Chen-Yu Tsai
4694dc56e9 sunxi: gpio: Add .xlate function for gpio phandle resolution
sunxi uses a 2 cell phandle for gpio bindings. Also there are no
seperate nodes for each pin bank.

Add a custom .xlate function to map gpio phandles to the correct
pin bank device. This fixes gpio_request_by_name usage.

Fixes: 7aa9748584 ("dm: sunxi: Modify the GPIO driver to support driver
		      model")
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
2016-07-31 21:45:12 +02:00
jk.kernel@gmail.com
dd63fbc70a rockchip: add support for rk3288 PopMetal board
PopMetal is a rockchip rk3288 based board made by ChipSpark, which has
many interface such as HDMI, VGA, USB, micro-SD card, WiFi, Audio and
Gigabit Ethernet.

Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
2016-07-31 07:24:20 -06:00