Moved CONFIG_SPL_TEXT_BASE to common/spl/Kconfig and migrate existing
values.
Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
[trini: Re-run migration]
Signed-off-by: Tom Rini <trini@konsulko.com>
Booting this board failed as the initial console isn't found since
commit c402e81702 ("dts: arm: socfpga: merge gen5 devicetrees from linux")
The uart0 devicetree entry was missing "clock-frequency = <100000000>:"
since that commit
Fixes: c402e81702 ("dts: arm: socfpga: merge gen5 devicetrees from linux")
Reported-by: rafael mello <rafaelmello_3@hotmail.com>
Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
The usage of socfpga_sdram_apply_static_cfg() seems rather dubious and
is confirmed to lead to a rare system hang when enabling bridges. This
patch removes the socfpga_sdram_apply_static_cfg() altogether, because
it's use seems unjustified and problematic.
The socfpga_sdram_apply_static_cfg() triggers write to SDRAM staticcfg
register to set the applycfg bit, which according to old vendor U-Boot
sources can only be written when there is no traffic between the SDRAM
controller and the rest of the system. Empirical measurements confirm
this, setting the applycfg bit when there is traffic between the SDRAM
controller and CPU leads to the SDRAM controller accesses being blocked
shortly after.
Altera originally solved this by moving the entire code which sets the
staticcfg register to OCRAM [1]. The commit message claims that the
applycfg bit needs to be set after write to fpgaportrst register. This
is however inverted by Altera shortly after in [2], where the order
becomes the exact opposite of what commit message [1] claims to be the
required order. The explanation points to a possible problem in AMP
use-case, where the FPGA might be sending transactions through the F2S
bridge.
However, the AMP is only the tip of the iceberg here. Any of the other
L2, L3 or L4 masters can trigger transactions to the SDRAM. It becomes
rather non-trivial to guarantee there are no transactions to the SDRAM
controller.
The SoCFPGA SDRAM driver always writes the applycfg bit in SPL. Thus,
writing the applycfg again in bridge enable code seems redundant and
can presumably be dropped.
[1] 75905816ec
[2] 8ba6986b04
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>
Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Cc: Tien Fong Chee <tien.fong.chee@intel.com>
The driver currently calculates the end address of cache flush operation
for the DMA descriptors by adding cacheline size to the start address of
the last DMA descriptor. This is not safe, as the cacheline size may be,
in some unlikely cases, smaller than the DMA descriptor size. Replace the
addition with roundup() applied on the end address of the last DMA
descriptor to round it up to the nearest cacheline size multiple.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Jaehoon Chung <jh80.chung@samsung.com>
Cc: Simon Glass <sjg@chromium.org>
The bounce_buffer_start() can return -ENOMEM in case memory allocation
failed. However, in that case, the bounce buffer address is the same as
the possibly unaligned input address, and the cache maintenance operations
were not applied to this address. This could cause subtle problems. Add
handling for the bounce_buffer_start() return value to prevent such a
problem from happening.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Jaehoon Chung <jh80.chung@samsung.com>
Cc: Simon Glass <sjg@chromium.org>
The current 4-minute data transfer timeout is misleading and broken.
Instead of such a long wait, calculate the timeout duration based on
the length of the data transfer. The current formula is the transfer
length in bits, divided by a multiplication of bus frequency in Hz,
bus width, DDR mode and converted the mSec. The value is bounded from
the bottom to 1000 mSec.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Jaehoon Chung <jh80.chung@samsung.com>
Cc: Simon Glass <sjg@chromium.org>
Add optional "mask" argument to the SoCFPGA bridge command, to select
which bridges should be enabled/disabled. This allows the user to avoid
enabling bridges which are not connected into the FPGA fabric. Default
behavior is to enable/disable all bridges.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>
Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Cc: Tien Fong Chee <tien.fong.chee@intel.com>
Instead of just putting the bridges into reset, fully remove the bridges
from the L3 main bridge space when disabling them by clearing bits in
NIC-301 remap register. Moreover, only touch the 3 LSbits in brgmodrst
register as the rest of the bits are undefined.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>
Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Cc: Tien Fong Chee <tien.fong.chee@intel.com>
Disable bridges between L3 Main switch and FPGA unless booting
from FPGA and keep them disabled to prevent glitches and possible
hangs of the L3 Main switch.
The current version of the code could have enabled the bridges
between the L3 Main switch and FPGA for a short period of time
in board_init_f() in case the FPGA was programmed and then again
disable them at the end of board_init_f(). Replace this with a
code which only sets up the handoff registers and let the user
enable the bridges later on.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>
Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Cc: Tien Fong Chee <tien.fong.chee@intel.com>
Factor out the code for programming preloader handoff register values,
the ISWGRP Handoff 0 and 1. These registers later control which bridges
are enabled by the "bridge" command on Gen5 devices.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>
Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Cc: Tien Fong Chee <tien.fong.chee@intel.com>
Per Pierre this change shouldn't have been applied as it was superseded
by "fs: btrfs: fix btrfs_search_tree invalid results" which is also
applied now as 1627e5e598.
This reverts commit 633967f981.
Signed-off-by: Tom Rini <trini@konsulko.com>
AVB 2.0 spec. revision 1.1 introduces support for named persistent values
that must be tamper evident and allows AVB to store arbitrary key-value
pairs [1].
Introduce implementation of two additional AVB operations
read_persistent_value()/write_persistent_value() for retrieving/storing
named persistent values.
Correspondent pull request in the OP-TEE OS project repo [2].
[1]: https://android.googlesource.com/platform/external/avb/+/android-9.0.0_r22
[2]: https://github.com/OP-TEE/optee_os/pull/2699
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Sam Protsenko <semen.protsenko@linaro.org>
Signed-off-by: Igor Opaniuk <igor.opaniuk@gmail.com>
Add the device trees for
* vexpress_ca5x2_defconfig
* vexpress_ca9x4_defconfig
* vexpress_ca15_tc2_defconfig
as available in Linux 5.1 rc5.
We are using the vexpress_ca15_tc2_defconfig and vexpress_ca9x4_defconfig
for Travis testing via QEMU.
The UEFI base Embedded Base Boot Requirements Specification (EBBR) requires
that an embedded board either provides a device tree or an ACPI table.
All block devices are meant to be moved to the driver model. On ARM this
requires a device tree.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
The sysreset of 'POWER' type is a PMIC reset defined as
'remove and restore power'.
So normally only COLD/WARN is supported by sysreset_syscon.
This modification allows to use the function sysreset_walk(SYSRESET_POWER)
when it is supported by PMIC driver (see example in stpmic1).
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
As far back as 2011, "_armboot_start" was being described as "no
longer defined":
commit 297f18ac0f
Author: Greg Ungerer <greg.ungerer@opengear.com>
Date: Fri Sep 9 22:23:34 2011 +1000
CM4000: fix broken flash base for OpenGear boards
Use _bss_start_ofs as the size of the boot loader code+data that we want
to protect in the flash. This replaces use of the no longer defined
_armboot_start.
The generated flash.log file that mach-imx uses for MKIMAGEOUTPUT is not
covered by any other ignore pattern. Ignore all *.log files.
Signed-off-by: Baruch Siach <baruch@tkos.co.il>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
The da850evm include environment/ti/mmc.h and places
DEFAULT_MMC_TI_ARGS, defined int that file, in
CONFIG_EXTRA_ENV_SETTINGS. This has been broken for some time
since neither CMD_PART nor CMD_UUID are available, so manually
changing the environmental variables was always required before
booting from MMC. With this patch, these scripts should work
again, and by default they point to mmc 0, partition 2, and
the dtb file exists in a /boot directory on partition 2.
Signed-off-by: Adam Ford <aford173@gmail.com>
A previous patch converted a bunch of settings for CONFIG_SF_DEFAULT
but it broke the SPI Flash which now prevents booting. This patch
now correctly sets CONFIG_SF_DEFAULT_SPEED=30000000 to match what it
was before the conversion.
Fixes: 14453fbfad ("Convert CONFIG_SF_DEFAULT_* to Kconfig")
Signed-off-by: Adam Ford <aford173@gmail.com>
The match controller register is not cleared during
initialization. However, some bits of this register may reset the TC if
tnMRx match it.
As we can't make any assumption about how U-Boot is launched by the first
stage bootloader (such as S1L) clearing this register ensure that the
timers work as expected.
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
Since the introduction of the driver, some memory in IRAM is reserved for
the TX buffers.
However there are not used but instead of it, it is the buffer provided
by the net stack which is used. As stated in the comment of the driver,
not using the IRAM buffer could cause cache issue and lower the
throughput.
For the second argument it is less the case for transmitting buffers
because the throughput gain in IRAM is mitigated by the time to copy the
data from RAM to IRAM, but the first argument is still valid and indeed
this patch fixes issue seen with Ethernet on some boards
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
The purpose of "mtd: nand: raw: allow to disable unneeded ECC layouts"
was to allow disabling the default ECC layouts if a driver is known to
provide its own ECC layout. However, this commit did the opposite and
disabled the default layout when it was _not_ selected.
It breaks all the NAND drivers not providing their own ECC layout this
patch fix this situation.
It was tested with the lpc32xx_nand_slc driver.
Fixes: a38c3af868 ("mtd: nand: raw: allow to disable unneeded ECC layouts")
Reviewed-by: Miquel Raynal <miquel.raynal@bootlin.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
Tested-by: Eugen Hristev <eugen.hristev@microchip.com>
generate define for an alias only if the struct is not
created already.
This prevents compilerwarning:
PLAT spl/dts/dt-platdata.o
spl/dts/dt-platdata.c:11:46: error: missing braces around initializer [-Werror=missing-braces]
static const struct dtd_simple_bus dtv_ahb = {
^
spl/dts/dt-platdata.c:20:46: error: missing braces around initializer [-Werror=missing-braces]
static const struct dtd_simple_bus dtv_apb = {
^
cc1: all warnings being treated as errors
on the at91 based taurus board. Reason is in at91sam9260.dtsi
is defined:
ahb {
compatible = "simple-bus";
ranges;
and later:
pinctrl: pinctrl@fffff400 {
compatible = "atmel,at91rm9200-pinctrl", "simple-bus";
ranges = <0xfffff400 0xfffff400 0x600>;
without this patch dtoc generates:
struct dtd_atmel_at91rm9200_pinctrl {
fdt32_t atmel_mux_mask[6];
fdt32_t ranges[3];
fdt32_t reg[6];
};
struct dtd_simple_bus {
bool ranges;
};
"#define dtd_simple_bus dtd_atmel_at91rm9200_pinctrl"
and the line with "define dtd_simple_bus..." introduces
the warning. This define is not needed.
Signed-off-by: Heiko Schocher <hs@denx.de>
btrfs_search_tree should return the first item in the tree that is
greater or equal to the searched item.
The search algorithm did not properly handle the edge case where the
searched item is higher than the last item of the node but lower than
the first item of the next node. Instead of properly returning the first
item of the next node, it was returning an invalid path pointer
(pointing to a non-existent item after the last item of the node + 1).
This fixes two issues in the btrfs driver:
- Looking for a ROOT_ITEM could fail if it was the first item of its
leaf node.
- Iterating through DIR_INDEX entries (for readdir) could fail if the
first DIR_INDEX entry was the first item of a leaf node.
Signed-off-by: Pierre Bourdon <delroth@gmail.com>
Cc: Marek Behun <marek.behun@nic.cz>
ROOT_ITEMs in btrfs are referenced without knowing their actual "offset"
value. To perform these searches using only two items from the key, the
btrfs driver uses a special "btrfs_search_tree_key_type" function.
The algorithm used by that function to transform a 3-tuple search into a
2-tuple search was subtly broken, leading to items not being found if
they were the first in their tree node.
This commit fixes btrfs_search_tree_key_type to properly behave in these
situations.
Signed-off-by: Pierre Bourdon <delroth@gmail.com>
Cc: Marek Behun <marek.behun@nic.cz>
Add new defconfig files for the AM65x High Security EVM.
This defconfigs are the same as for the non-secure part, except for:
CONFIG_TI_SECURE_DEVICE option set to 'y'
CONFIG_FIT_IMAGE_POST_PROCESS option set to 'y'
CONFIG_SPL_FIT_IMAGE_POST_PROCESS option set to 'y'
Signed-off-by: Andrew F. Davis <afd@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Andreas Dannenberg <dannenberg@ti.com>
K3 HS devices require signed binaries for boot, use the SECDEV tools
to sign the boot artifacts during build.
Signed-off-by: Andrew F. Davis <afd@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Andreas Dannenberg <dannenberg@ti.com>
K3 devices have High Security (HS) variants along with the non-HS already
supported. Like the previous generation devices (OMAP/Keystone2) K3
supports boot chain-of-trust by authenticating and optionally decrypting
images as they are unpacked from FIT images. Add support for this here.
Signed-off-by: Andrew F. Davis <afd@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Andreas Dannenberg <dannenberg@ti.com>
SYSFW version 2019.01 introduces a slightly modified version of this API,
add support for it here.
Signed-off-by: Andrew F. Davis <afd@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Andreas Dannenberg <dannenberg@ti.com>
TI-SCI message protocol provides support for controlling the firewall
configurations available in SoC.
Introduce support for the set of TI-SCI message protocol APIs that
provide us with this capability of controlling firewalls.
Signed-off-by: Andrew F. Davis <afd@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Andreas Dannenberg <dannenberg@ti.com>
On HS devices the 512b region of reset isolated memory called
MCU_PSRAM0 is firewalled by default. Until SYSFW is loaded we
cannot use this memory. It is only used to store a single value
left at the end of SRAM by ROM that will be needed later. Save
that value to a global variable stored in the .data section.
This section is used as .bss will be cleared between saving
this value and using it.
Signed-off-by: Andrew F. Davis <afd@ti.com>
Reviewed-by: Andreas Dannenberg <dannenberg@ti.com>
Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
The objective is to provide a simple way to retrieve a BMP file,
and display it as splashscreen, from extlinux.conf file input.
For this, we take example on https://www.syslinux.org/wiki/
index.php?title=Menu#The_advanced_menu_system
and more particularly on MENU BACKGROUND chapter.
For this, add "menu background" support in pxe command.
As example, extlinux.conf content will look like:
# Generic Distro Configuration file generated by OpenEmbedded
menu title Select the boot mode
TIMEOUT 20
menu background ../splash.bmp
DEFAULT stm32mp157c-ev1-sdcard
LABEL stm32mp157c-ev1-sdcard
KERNEL /uImage
FDT /stm32mp157c-ev1.dtb
APPEND root=/dev/mmcblk0p6 rootwait rw earlyprintk console=ttySTM0,115200
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Fixes building mkimage on systems where OpenSSL header files do not
live in the standard include path.
Signed-off-by: Pierre Bourdon <delroth@gmail.com>
The handling of regarding bootmode and early setup has been moved to
central location 'common/br_resetc.c', so use this on brxre1 board.
Signed-off-by: Hannes Schmelzer <hannes.schmelzer@br-automation.com>
On many B&R boards we have a reset-controller, responsible for very
early board-bringup (voltages, clocks, ...) and bootmode selection.
To be ready for adding more B&R boards to source tree while avoiding
duplicate code, we add the resetcontroller implementation to the common
part of B&R boards.
Signed-off-by: Hannes Schmelzer <hannes.schmelzer@br-automation.com>
Many B&R boards are equipped with an I2C-EEPROM where various
information can be stored.
Today there is only a single byte for 'board_id' used.
We write this 'board_id' into environment for later use during boot.
If the value != 0xFF, meaning the byte is programmed, we modify the
"brdefaultip" environment variable for setting an IP-Address based on
board_id.
Signed-off-by: Hannes Schmelzer <hannes.schmelzer@br-automation.com>
Today the BuR common stuff is only used on AM33XX boards. In future we
plan to have many other platforms than AM33XX so we have to move arch-
specific #include(s) to responsible #ifdef sections. By the way we drop
unneeded #include(s).
Signed-off-by: Hannes Schmelzer <hannes.schmelzer@br-automation.com>
- Add DM based generic watchdog start and reset implementation
and remove all ad-hoc implementations (Stefan)
- Move mv_sdhci to DM (Pierre)
- Misc turris_omnia updates (Pierre)
- Change openrd targets to correctly build again (size changes
and fixes to the dts targets) and bring it back into Travis
builds (Stefan)
- Add Kirkwood db-88f6281-bp board (Chris)
With the latest size increase of the openrd boards, they all compile
clean again. Let's mark them as maintained again and add the Travis
job.
Please note that I can only compile-test these targets as I don't
have access to one of those boards.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Albert ARIBAUD <albert-u-boot@aribaud.net>
Cc: Vagrant Cascadian <vagrant@debian.org>
Cc: Chris Packham <judge.packham@gmail.com>
Cc: Tom Rini <trini@konsulko.com>
With the new generic function, the scattered other functions are now
removed to be replaced by the generic one. The new version also enables
the configuration of the watchdog timeout via the DT "timeout-sec"
property (if enabled via CONFIG_OF_CONTROL).
The watchdog servicing is enabled via CONFIG_WATCHDOG.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Heiko Schocher <hs@denx.de>
Cc: Eugen Hristev <eugen.hristev@microchip.com>
