Instead of passing this parameter into __dw_i2c_set_bus_speed(), pass in
the driver's private data, from which the function can obtain that
information. This allows the function to have access to the full state of
the driver.
Signed-off-by: Sicomp_param1mon Glass <sjg@chromium.org>
Reviewed-by: Heiko Schocher <hs@denx.de>
Signed-off-by: Simon Glass <sjg@chromium.org>
The i2c controller defines a few timing properties. Read these in and
store them for use by the driver.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Heiko Schocher <hs@denx.de>
At present the driver uses an approximation for the bus clock, e.g. 166MHz
instead of 166 2/3 MHz.
This can result in small errors in the resulting I2C speed, perhaps 0.5%
or so.
Adjust the existing code to start from the accurate figure, even if later
rounding reduces this accuracy.
Update the bus speed code to work in KHz instead of MHz, which removes
most of the error.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Heiko Schocher <hs@denx.de>
Group these #defines into an enum to make it easier to understand the
relationship between them.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Jun Chen <ptchentw@gmail.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
Some SoCs support a higher speed than what is currently called 'max' in
this driver. Rename it to 'high' speed, which is the official name of the
3.4MHz speed.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Jun Chen <ptchentw@gmail.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
We use struct clk here so really should include this header file to avoid
build errors. Also switch the order of clk.h in the C file to match the
required code style.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
Reviewed-by: Jun Chen <ptchentw@gmail.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
If a different input clock is required then the correct way to do this is
with a clock driver. Don't allow boards to override IC_CLK.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Heiko Schocher <hs@denx.de>
Some versions of this peripherals provide more control of the bus
behaviour. Add definitions for these registers.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
Reviewed-by: Jun Chen <ptchentw@gmail.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
The srdata field is unused since commit 71204e95ce ("i2c: mxc:
refactor i2c driver and support dm").
Cc: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Baruch Siach <baruch@tkos.co.il>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Since frac_pll_init() is only used in this file, change it to 'static'.
This fixes the following sparse warning:
arch/arm/mach-imx/imx8m/clock_imx8mq.c:662:5: warning: no previous
prototype for ‘frac_pll_init’ [-Wmissing-prototypes]
Signed-off-by: Pedro Jardim <jardim.c.pedro@gmail.com>
Function sscg_pll_init() is not used anywhere, so it can simply be deleted.
This was found because of the following sparse
warning:
arch/arm/mach-imx/imx8m/clock_imx8mq.c:702:5: warning: no previous prototype for ‘sscg_pll_init’ [-Wmissing-prototypes]
int sscg_pll_init(u32 pll)
^~~~~~~~~~~~~
Signed-off-by: Pedro Jardim <jardim.c.pedro@gmail.com>
Since do_imx8m_showclocks() is only used inside this file, make it 'static'.
This fixes the following sparse warning:
arch/arm/mach-imx/imx8m/clock_imx8mq.c:836:5: warning: no previous prototype
for ‘do_imx8m_showclocks’ [-Wmissing-prototypes]
int do_imx8m_showclocks(cmd_tbl_t *cmdtp, int flag, int argc,
^~~~~~~~~~~~~~~~~~~
Signed-off-by: Pedro Jardim <jardim.c.pedro@gmail.com>
Function init_usb_clk() is not used anywhere, so it can simply be deleted.
This was detected by the following sparse warning:
arch/arm/mach-imx/imx8m/clock_imx8mq.c:377:6: warning: no previous prototype
for ‘init_usb_clk’ [-Wmissing-prototypes]
void init_usb_clk(void)
^~~~~~~~~~~~
Signed-off-by: Pedro Jardim <jardim.c.pedro@gmail.com>
Guard 'parent_rate==0' to prevent 'divide by zero' issue in
clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL.
Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
Guard 'mfd==0' to prevent 'divide by zero' issue in
clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd
should never be 0 at all.
Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
Guard 'parent_rate==0' to prevent 'divide by zero' issue in
clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL.
Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
m68k needs block cache list initialized after relocation.
Other architectures must not be involved.
Fixing regression related to:
commit 1526bcce0f
("common: add blkcache init")
Signed-off-by: Angelo Durgehello <angelo.dureghello@timesys.com>
This function parameter usage of load_addr was incorrectly caught in
the clarifying renames of commit bb872dd930, which results in boot
failures on Marvell A38x.
Signed-off-by: Joel Johnson <mrjoel@lixil.net>
Patch-to: Simon Glass <sjg@chromium.org>
Orange Pi Win has gigabit ethernet port, but default U-Boot
configuration for that board enabled ethernet driver but
didn't enable realtek phy.
Fix that.
Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Since commit 067e0b9684 ("sunxi: Allow booting from 128KB SD/eMMC offset")
we support having the SPL loaded from either the traditional 8KB SD
card/eMMC offset, or from the alternative location at 128KB. However the
sector to find the U-Boot image was still hard-coded at compile time,
and had to be adjusted for one of the two choices.
Since we can actually override the function to return the sector offset,
we can just check the boot source byte there to select the proper offset
based on from where the SPL was loaded.
This allows the very same binary image to be loaded from either 128KB or
8KB, with the U-Boot proper image always being located just behind the SPL.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Acked-by: Jagan Teki <jagan@amarulasolutions.com>
The Boot ROM write some boot source ID (SD card, eMMC, SPI, ...) into
a certain location in SRAM, so the SPL can easily determine where to
load U-Boot proper from.
Factor out reading this value, as it will come in handy again shortly.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Acked-by: Jagan Teki <jagan@amarulasolutions.com>
clk_get_by_name() requires clk_get_by_id() that is not available if
CONFIG_OF_PLATDATA is defined, so move clk_get_by_name() into #else
condition of #if CONFIG_IS_ENABLED(OF_PLATDATA).
Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
mtk_clk_find_parent_rate is calling clk_get_rate to know the rate
of a parent clock. clk_get_rate returns a ulong, while
mtk_clk_find_parent_rate returns an int. This implicit cast creates
an issue for clock rates big enough to need the full 32 bits to
store its data. When that happen the clk rate will become incorrect
because of the implicit cast between ulong -> int -> ulong.
This commit change the return type of mtk_clk_find_parent_rate to
ulong.
Signed-off-by: Fabien Parent <fparent@baylibre.com>
This patch adds a prototype for the weak function
board_mtdparts_default().
It solves one warning when compiling with W=1 on stm32mp1 board:
board/st/stm32mp1/stm32mp1.c:
warning: no previous prototype for 'board_mtdparts_default'
[-Wmissing-prototypes]
void board_mtdparts_default(const char **mtdids,
const char **mtdparts)
^~~~~~~~~~~~~~~~~~~~~~
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
The blkcache_read() routine returns 1 (true) to indicate that a block was
found in the cache and returned, or 0 if not.
Signed-off-by: Eric Nelson <eric@nelint.com>
There is a typo in meerkat96 MAINTAINERS email address. Fix it.
Reported-by: Carl Gelfand <carl@novtech.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
On m68k, block_cache list is relocated, but next and prev list
pointers are not adjusted to the relocated struct list_head address,
so the first iteration over the block_cache list hangs.
This patch initializes the block_cache list after relocation.
Signed-off-by: Angelo Durgehello <angelo.dureghello@timesys.com>
Reviewed-by: Eric Nelson <eric@nelint.com>
Now that arch specific dma mapping APIs take care of cache
flush/invalidate, drop local cache flush operation.
While at that fix dma_unmap_single() call to match new prototype
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Drop local dma_map_single() and dma_unmap_single() and use arch specific
common implementation
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Acked-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Drop local dma_map_single() and dma_unmap_single() and use arch specific
common implementation
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Acked-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Subsystems such as USB expect dma_map_single() and dma_unmap_single() to
do dcache flush/invalidate operations as required. For example, see
see drivers/usb/gadget/udc/udc-core.c::usb_gadget_map_request().
Currently drivers do this locally, (see drivers/usb/dwc3/ep0.c,
drivers/mtd/nand/raw/denali.c etc..)
Update arch specific dma_map_single() and dma_unmap_single() APIs to do
cache flush/invalidate operations, so that drivers need not implement
them locally.
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Reviewed-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Rick Chen <rick@andestech.com>
This patch includes the following:
1. Add fastboot command to erase the whole EMMC_USER
2. Add fastboot command to flash image at EMMC_BOOT1
3. Add fastboot command to erase the whole EMMC_BOOT1
4. Enale CONFIG_FASTBOOT_MMC_BOOT1_SUPPORT for mt8518
Signed-off-by: mingming lee <mingming.lee@mediatek.com>
Function mod_exp_sw() is only used via the operators of the uclass.
It is not defined in any include.
Make mod_exp_sw() static.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
drivers/rng/sandbox_rng.c requires rand() to be defined but configuration
option CONFIG_CONFIG_LIB_RAND selected in drivers/rng/Kconfig does not
exist.
test/lib/test_aes.c requires rand() to be defined.
Fix the selection criteria for choice "Pseudo-random library support type".
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
CONFIG_SPL_RSA is meant to control if lib/rsa/* is used for SPL. Adjust
lib/Makefile to consider this setting.
This was correctly setup with commit 51c14cd128 ("verified-boot: Minimal
support for booting U-Boot proper from SPL") and got lost with commit
089df18bfe ("lib: move hash CONFIG options to Kconfig").
Fixes: 089df18bfe ("lib: move hash CONFIG options to Kconfig")
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
The Libre Computer ALL-H5-CC board is an upgraded version of the
ALL-H3-CC. Changes include:
- Gigabit Ethernet via external RTL8211E Ethernet PHY
- 16 MiB SPI NOR flash memory
- PoE tap header
- Line out jack removed
Only H5 variant test samples were made available, and the vendor is not
certain whether other SoC variants would be made or not. Furthermore the
board is a minor upgrade compared to the ALL-H3-CC. Thus the device tree
simply includes the one for the ALL-H3-CC, and adds the changes on top.
The device tree was synced over from the Linux kernel, along with other
H3/H5 changes, in a previous patch. Thus only the defconfig and an entry
to the MAINTAINERS file is added.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
[jagan: drop CONFIG_SYS_SPI_U_BOOT_OFFS]
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
The Libre Computer ALL-H3-IT board is a small single board computer that
is roughly the same size as the Raspberry Pi Zero, or around 20% smaller
than a credit card.
The board features:
- H2, H3, or H5 SoC from Allwinner
- 2 DDR3 DRAM chips
- Realtek RTL8821CU based WiFi module
- 128 Mbit SPI-NOR flash
- micro-SD card slot
- micro HDMI video output
- FPC connector for camera sensor module
- generic Raspberri-Pi style 40 pin GPIO header
- additional pin headers for extra USB host ports, ananlog audio and
IR receiver
Only H5 variant test samples were made available, but the vendor does
have plans to include at least an H3 variant. Thus the device tree is
split much like the ALL-H3-CC, with a common dtsi file for the board
design, and separate dts files including the common board file and the
SoC dtsi file. The other variants will be added as they are made
available.
The device tree was synced over from the Linux kernel, along with other
H3/H5 changes, in a previous patch. Thus only the defconfig and an entry
to the MAINTAINERS file is added.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
[jagan: drop CONFIG_SYS_SPI_U_BOOT_OFFS]
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
