Commit graph

458 commits

Author SHA1 Message Date
Shaohui Xie
ae6b458306 driver/net/fm/memac_phy: set NEG bit for external MDIOs
NEG bit default is '1' for external MDIOs as per FMAN-v3 RM, but on some
platforms, e.g. T2080QDS, this bit is '0', which leads to MDIO failure
on XAUI PHY, so set this bit definitely to align with the RM.

Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-11-14 11:12:13 -08:00
Shaohui Xie
ff5fb2a36d Fman/mEMAC: mEMAC fix for 10G MAC and PHY
1. use Payload length check disable when enable MAC;
2. add XGMII support for setting MAC interface mode;
3. only enable auto negotiation for Non-XGMII mode;
4. return 0xffff if clause 22 is used to read 10G phy_id;

Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
Acked-By: Joe Hershberger <joe.hershberger@ni.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-11-14 11:12:13 -08:00
Dirk Eibach
b97cd6814e ppc4xx: Handle i2c stuck on combined xfer
ppc4xx i2c master gets stuck on errors while repeated start is
active. Can be easily reproduced by "i2c md" on an unpopulated
i2c address. There is not stop condition given, scl remains
pulled low.
The only way out seems to be doing a stop manually and then a
soft reset.

Signed-off-by: Dirk Eibach <dirk.eibach@gdsys.cc>
Reviewed-by: Stefan Roese <sr@denx.de>
2014-11-10 06:44:30 +01:00
Marek Vasut
5038d7f189 ppc: Zap Hymod board
Remove this board as this is the only one last user of eeprom_probe(),
which is pretty non-standard stuff.

This patch also removes all the PHP, SQL and CSS stuff from U-Boot,
which probably makes U-Boot a bit less IoT ;-)

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Tom Rini <trini@ti.com>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Cc: Heiko Schocher <hs@denx.de>
2014-10-27 14:35:55 +01:00
Anatolij Gustschin
c6832a9635 powerpc: mpc512x: fix boot breakage
Commit d6b11fd1 (powerpc: remove MBX and MBX860T boards support)
removed mbxbar field in "struct sysconf512x" by mistake and broke
booting on mpc5121 boards. Fix it.

Signed-off-by: Anatolij Gustschin <agust@denx.de>
2014-10-27 14:35:53 +01:00
Ruchika Gupta
7cad2e38d6 powerpc/mpc85xx: SECURE BOOT - Bypass PAMU in case of secure boot
By default, PAMU's (IOMMU) are enabled in case of secure boot.
Disable/bypass them once the control reaches the bootloader.

For non-secure boot, PAMU's are already bypassed in the default
SoC configuration.

Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-10-16 14:17:42 -07:00
Ruchika Gupta
b9eebfade9 fsl_sec: Add hardware accelerated SHA256 and SHA1
SHA-256 and SHA-1 accelerated using SEC hardware in Freescale SoC's
The driver for SEC (CAAM) IP is based on linux drivers/crypto/caam.
The platforms needto add the MACRO CONFIG_FSL_CAAM inorder to
enable initialization of this hardware IP.

Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-10-16 14:17:07 -07:00
Ruchika Gupta
028dbb8db1 fsl_sec : Change accessor function to take care of endianness
SEC registers can be of type Little Endian or big Endian depending upon
Freescale SoC. Here SoC defines the register type of SEC IP.

So update acessor functions with common SEC acessor functions to take care
both type of endianness.

Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-10-16 14:16:50 -07:00
Ruchika Gupta
48ef0d2a10 fsl_sec : Move SEC CCSR definition to common include
Freescale SEC controller has been used for mpc8xxx. It will be used
for ARM-based SoC as well. This patch moves the CCSR defintion of
SEC to common include

Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-10-16 14:16:25 -07:00
Masahiro Yamada
9ed3246e19 powerpc: ppc4xx: remove board support for bluestone
This board has been orphaned for more than 6 months.

It is the last board defining CONFIG_APM821XX.
The code inside #ifdef CONFIG_APM821XX should be removed too.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2014-10-10 09:44:43 -04:00
Claudiu Manoil
93f26f130e net: Merge asm/fsl_enet.h into fsl_mdio.h
fsl_enet.h defines the mapping of the usual MII management
registers, which are included in the MDIO register block
common to Freescale ethernet controllers. So it shouldn't
depend on the CPU architecture but it should be actually
part of the arch independent fsl_mdio.h.

To remove the arch dependency, merge the content of
asm/fsl_enet.h into fsl_mdio.h.
Some files (like fm_eth.h) were simply including fsl_enet.h
only for phy.h. These were updated to include phy.h instead.

Signed-off-by: Claudiu Manoil <claudiu.manoil@freescale.com>
2014-09-08 10:30:33 -07:00
Boschung, Rainer
60b295672d powerpc: macros for e500mc timer regs added
For e500mc cores the watchdog timer period has to be set by means of a
6bit value, that defines the bit of the timebase counter used to signal
a watchdog timer exception on its 0 to 1 transition.
The macro used to set the watchdog period TCR_WP, was redefined for e500mc
to support 6 WP setting.

The parameter (x) given to the macro specifies the prescaling factor of
the time base clock (fTB):

watchdog_period = 1/fTB * 2^x

Signed-off-by: Rainer Boschung <rainer.boschung@keymile.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-08-01 14:18:07 -07:00
Tang Yuantian
7cb7272365 mpc85xx/t104x: Enable L2 and CPC cache when resume
When resume from deep sleep, uboot needs to enable L2 and CPC
cache, or they would be keeping unusable in kernel because
kernel didn't enble or initialized them.
This patch didn't change the existing L2 cache enabling code,
just put them in a function.

Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-07-22 16:25:55 -07:00
Shaohui Xie
e55782eccc powerpc/t4240qds: fix offset of serdes when checking reference clock
T4240 has 4 serdes, each serdes has 4k memory space, two PLLs.
We use PLL1CR0 to check the serdes reference clock.

Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-07-22 16:25:55 -07:00
York Sun
8340e7ac86 driver/ddr: Fix DDR4 driver for ARM
Previously the driver was only tested on Power SoCs. Different barrier
instructions are needed for ARM SoCs.

Signed-off-by: York Sun <yorksun@freescale.com>
2014-07-22 16:25:54 -07:00
Sandeep Singh
d43a386a91 powerpc/mpc85xx: Removed support for G4060
G4060 has no PA cores, hence removing its support.

Signed-off-by: Sandeep Singh <Sandeep@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-07-22 16:25:54 -07:00
Zhao Qiang
38d67a4e55 qe: move immap_qe.h from arch directory into common directory
ls1021 is arm-core and supports qe too.
Move immap_qe.h into common directory for both arm and powerpc.

Signed-off-by: Zhao Qiang <B45475@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-07-22 16:25:54 -07:00
Sandeep Singh
377ffcfabf powerpc/mpc85xx: Add workaround to enable TDM on T1040
This is a workaround for 32 bit hardware limitation of TDM.
T1040 has 36 bit physical addressing, TDM DMAC register
are 32 bit wide but need to store address of CCSR space
which lies beyond 32 bit address range. This workaround
creats a LAW to enable access of TDM DMA to CCSR by
mapping CCSR to overlap with DDR.
A hole of 16M is created in memory using device tree. This
workaround law is set only if "tdm" is defined in hwconfig.
Also disable POST tests and add LIODN for TDM

Signed-off-by: Sandeep Singh <Sandeep@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-06-05 13:45:07 -07:00
Shaveta Leekha
b6808cd82d powerpc/serdes: Add the workaround for erratum A-007186
SerDes PLL is calibrated at reset. When the junction temperature
delta from the time the PLL is calibrated exceeds +56C/-66C,
jitter may increase and can cause PLL to unlock.

This workaround overwrite the SerDes registers with new values,
to calibrate SerDes registers.
These values are known to work fine for all temperature ranges.

This workaround is valid for B4, T4 and T2 platforms, so
added in their config.

Signed-off-by: Shaveta Leekha <shaveta@freescale.com>
Signed-off-by: Poonam Aggrwal <Poonam.Aggrwal@freescale.com>
[York Sun: replaced typedef ccsr_sfp_regs_t with struct ccsr_sfp_regs]
Reviewed-by: York Sun <yorksun@freescale.com>
2014-06-05 13:45:07 -07:00
York Sun
9855b3beca powerpc/mpc85xx: Add workaround for DDR erratum A004508
When the DDR controller is initialized below a junction temperature of
0°C and then operated above a junction temperature of 65°C, the DDR
controller may cause receive data errors, resulting ECC errors and/or
corrupted data. This erratum applies to the following SoCs and their
variants: MPC8536, MPC8569, MPC8572, P1010, P1020, P1021, P1022, P1023,
P2020.

Signed-off-by: York Sun <yorksun@freescale.com>
2014-06-05 13:45:07 -07:00
Masahiro Yamada
3fe1a8545b powerpc: hiddendragon: remove orphan board
This board has been orphan for a while.
(Emails to its maintainer have been bouncing.)

Because MPC82xx family is old enough, nobody would pick up
the maintainership on it.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Wolfgang Denx <wd@denx.de>
2014-05-30 14:03:24 -04:00
ramneek mehresh
80ba6a6f2a mpc85xx/p1020:Define number of USB controllers used on P1020RDB-PD platform
P1020 SoC which has two USB controllers, but only first one is used
on this platform.

Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-05-16 16:24:27 -05:00
Shaveta Leekha
9c3fdd883a powerpc/mpc85xx: Added B4460 support
B4460 differs from B4860 only in number of CPU cores,
hence used existing support for B4860.
B4460 has 2 PPC cores whereas B4860 has 4 PPC cores.

Signed-off-by: Shaveta Leekha <shaveta@freescale.com>
Signed-off-by: Sandeep Singh <Sandeep@freescale.com>
Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-05-16 16:24:26 -05:00
Chunhe Lan
f1a96ec1a9 fsl/pci: Add workaround for erratum A-005434
By default, all PEX inbound windows PEX_PEXIWARn[TRGT] are
mapped to 0xF, which is local memory. But for BSC9132, 0xF
is CCSR, 0x0 is local memory.

Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com>
Signed-off-by: Chunhe Lan <Chunhe.Lan@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-05-16 16:24:26 -05:00
Shengzhou Liu
5122dfae5d powerpc/85xx: add T4080 SoC support
The T4080 SoC is a low-power version of the T4160.
T4080 combines 4 dual-threaded Power Architecture e6500
cores with single cluster and two memory complexes.

Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
2014-05-13 08:26:54 -07:00
Shengzhou Liu
c665c473b6 powerpc/t208x: enable errata A006261, A006593, A006379
Enable errata A006261, A006593, A006379 for T208x.
Additionally enable CONFIG_CMD_ERRATA for T2080RDB.

Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
2014-05-13 08:26:54 -07:00
Aneesh Bansal
e47c2a6851 powerpc/mpc85xx: SECURE BOOT- Add secure boot target for T2080RDB
Secure Boot Target is added for T2080RDB

Changes:
For Secure boot, CPC is configured as SRAM and used as house
keeping area which needs to be disabled.
So CONFIG_SYS_CPC_REINIT_F is defined for CONFIG_T2080RDB.

Signed-off-by: Aneesh Bansal <aneesh.bansal@freescale.com>
2014-05-13 08:26:54 -07:00
Aneesh Bansal
4067815998 powerpc/mpc85xx: SECURE BOOT- secure boot target for t1040rdb
T1040RDB.h file is removed and a unified file T104xRDB.h is created.
Hence macro CONFIG_T1040 is renamed to CONFIG_T104x.

Signed-off-by: Gaurav Kumar Rana <gaurav.rana@freescale.com>
Signed-off-by: Aneesh Bansal <aneesh.bansal@freescale.com>
2014-05-13 08:24:32 -07:00
Masahiro Yamada
8e2615752e bd_info: remove bi_barudrate member from struct bd_info
gd->bd->bi_baudrate is a copy of gd->baudrate.

Since baudrate is a common feature for all architectures,
keep gd->baudrate only.

It is true that bi_baudrate was passed to the kernel in that structure
but it was a long time ago.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Tom Rini <trini@ti.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Heiko Schocher <hs@denx.de>
Acked-by: Michal Simek <monstr@monstr.eu> (For microblaze)
2014-05-12 15:19:45 -04:00
vijay rai
0c12a1592c powerpc/85xx: Enhance get_sys_info() to check clocking mode
T1040 and it's variants provide "Single Oscillator Source" Reference Clock Mode.

In this mode, single onboard oscillator(DIFF_SYSCLK) can provide the reference clock
(100MHz) to the following PLLs:
• Platform PLL
• Core PLLs
• USB PLL
• DDR PLL, etc

The cfg_eng_use0 of porsr1 register identifies whether the SYSCLK (single-ended) or
DIFF_SYSCLK (differential) is selected as the clock input to the chip.

get_sys_info has been enhanced to add the diff_sysclk so that the
various drivers can be made aware of ths diff sysclk configuration and
act accordingly.

Other changes:
-single_src to ddr_refclk_sel, as it is use for checking ddr reference clock
-Removed the print of single_src from get_sys_info as this will be
-printed whenever somebody calls get_sys_info which is not appropriate.
-Add print of single_src in checkcpu as it is called only once during initialization

Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com>
Signed-off-by: Vijay Rai <vijay.rai@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-04-22 17:58:52 -07:00
Tang Yuantian
5aef4c86f3 mpc85xx: Add support for the supplement configuration unit register
The supplement configuration unit (SCFG) provides chip-specific
configuration and status registers for the device. It is the chip
defined module for extending the device configuration unit (DCFG)
module. It provides a set of CCSR registers in addition to those
available in the device configuration unit.
The base address for this unit is 0x0F_C000.

Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-04-22 17:58:49 -07:00
York Sun
c3678b0937 powerpc/mpc85xx: Add workaround for erratum A007212
Erratum A007212 for DDR is about a runaway condition for DDR PLL
oscilliator. Please refer to erratum document for detail.
For this workaround to work, DDR PLL needs to be disabled in RCW.
However, u-boot needs to know the expected PLL ratio. We put the
ratio in a reserved field RCW[18:23]. U-boot will skip this workaround
if DDR PLL ratio is set, or the reserved field is not set.

Workaround for erratum A007212 applies to selected versions of
B4/T4 SoCs. It is safe to apply the workaround to all versions. It
is helpful for upgrading SoC without changing u-boot. In case DDR
PLL is disabled by RCW (part of the erratum workaround), we need this
u-boot workround to bring up DDR clock.

Signed-off-by: York Sun <yorksun@freescale.com>
2014-04-22 17:58:48 -07:00
Nikhil Badola
11856919f2 fsl/usb: Workaround for USB erratum-A007075
Put a delay of 5 millisecond after reset so that ULPI phy
gets enough time to come out of reset. Erratum A007075 applies
to following SOCs and their variants, if any
        P1010 rev 1.0
        B4860 rev 1.0, 2.0
        P4080 rev 2.0, 3.0

Signed-off-by: Nikhil Badola <nikhil.badola@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-04-22 17:58:48 -07:00
York Sun
34e026f9b1 driver/ddr/fsl: Add DDR4 support to Freescale DDR driver
Mostly reusing DDR3 driver, this patch adds DDR4 SPD handling, register
calculation and programming.

Signed-off-by: York Sun <yorksun@freescale.com>
2014-04-22 17:58:48 -07:00
Zhao Qiang
2a44efeb21 QE/U-QE: Add U-QE support
Modify code to adapt to both u-qe and qe.

U_QE is a kind of cutted QE.
the differences between U_QE and QE
	1. UCC: U_QE supports 2 UCCs while QE supports up to 8 UCCs.
	2. IMMR: have different immr base addr.
	3. iopin: U_QE doesn't need to config iopin.

Signed-off-by: Zhao Qiang <B45475@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-04-22 17:58:47 -07:00
Aneesh Bansal
2d8db6d315 powerpc/mpc85xx: SECURE BOOT- Add secure boot target for T1040QDS and T1040RDB
Secure Boot Target is added for T1040QDS and T1040RDB
Changes:
For Secure boot, CPC is configured as SRAM and used as house
keeping area which needs to be disabled.
So CONFIG_SYS_CPC_REINIT_F is defined for CONFIG_T1040QDS and
CONFIG_T1040RDB

Signed-off-by: Gaurav Rana <gaurav.rana@freescale.com>
Signed-off-by: Aneesh Bansal <aneesh.bansal@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-04-22 17:58:47 -07:00
Aneesh Bansal
ca4819df83 powerpc/mpc85xx: SECURE BOOT- Add secure boot target for T2080QDS
Secure Boot Target is added for T2080QDS
Changes:
For Secure boot, CPC is configured as SRAM and used as house
keeping area which needs to be disabled.
So CONFIG_SYS_CPC_REINIT_F is defined for CONFIG_T2080QDS.

Signed-off-by: Aneesh Bansal <aneesh.bansal@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-04-22 17:58:46 -07:00
Aneesh Bansal
796a781001 powerpc/mpc85xx: SECURE BOOT- Add secure boot target for T4240QDS and T4160QDS
Secure Boot Target is added for T4240QDS and T4160QDS
Changes:
For Secure boot, CPC is configured as SRAM and used as house
keeping area which needs to be disabled.
So CONFIG_SYS_CPC_REINIT_F is defined for CONFIG_T4240QDS.

Signed-off-by: Aneesh Bansal <aneesh.bansal@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-04-22 17:58:46 -07:00
Aneesh Bansal
fb4a2409b4 powerpc/mpc85xx: SECURE BOOT- Add secure boot target for B4860QDS
Changes:
1. L2 cache is being invalidated by Boot ROM code for e6500 core.
   So removing the invalidation from start.S
2. Clear the LAW and corresponding configuration for CPC. Boot ROM
   code uses it as hosekeeping area.
3. For Secure boot, CPC is configured as SRAM and used as house
   keeping area. This configuration is to be disabled once in uboot.
   Earlier this disabling of CPC as SRAM was happening in cpu_init_r.
   As a result cache invalidation function was getting skipped in
   case CPC is configured as SRAM.This was causing random crashes.

Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com>
Signed-off-by: Aneesh Bansal <aneesh.bansal@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-04-22 17:58:46 -07:00
Aneesh Bansal
f978f7c203 powerpc/mpc85xx: SECURE BOOT- Add secure boot target for BSC9132QDS
Add NOR, SPI and SD secure boot targets for BSC9132QDS.

Changes:
- Debug TLB entry is not required for Secure Boot Target.

Signed-off-by: Aneesh Bansal <aneesh.bansal@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-04-22 17:58:46 -07:00
Alexander Graf
fa08d39517 PPC 85xx: Add qemu-ppce500 machine
For KVM we have a special PV machine type called "ppce500". This machine
is inspired by the MPC8544DS board, but implements a lot less features
than that one.

It also provides more PCI slots and is supposed to be enumerated by
device tree only.

This patch adds support for the generic ppce500 machine and tries to
rely solely on device tree for device enumeration.

Signed-off-by: Alexander Graf <agraf@suse.de>
Acked-by: Scott Wood <scottwood@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-04-22 17:58:45 -07:00
Alexander Graf
f29f804a93 PPC: 85xx: Generalize DDR TLB mapping function
The DDR mapping function really is just a generic virtual -> physical
mapping function. Generalize it so it can support any virtual starting
offset and IO maps just the same.

Signed-off-by: Alexander Graf <agraf@suse.de>
Acked-by: Scott Wood <scottwood@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-04-22 17:58:45 -07:00
Masahiro Yamada
d6b11fd1f0 powerpc: remove MBX and MBX860T boards support
Enough time has passed since these boards were moved to Orphan. Remove.

 - Remove board/mbx8xx/*
 - Remove include/configs/{MBX.h,MBX860T.h}
 - Clean-up if defined(CONFIG_MBX)
 - Move the entries from boards.cfg to doc/README.scrapyard

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2014-04-18 10:42:29 -04:00
Masahiro Yamada
a146e8b189 powerpc: remove NX823 board support
Enough time has passed since this board was moved to Orphan. Remove.

 - Remove board/nx823/*
 - Remove include/configs/NX823.h
 - Clean-up ifdef(CONFIG_NX823)
 - Move the entry from boards.cfg to doc/README.scrapyard

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2014-04-18 10:42:29 -04:00
Haijun.Zhang
1336e2d343 mmc:eSDHC: Workaround for data timeout issue on Txxx SoC
1. The Data timeout counter value in eSDHC_SYSCTL register is
not working as it should be, so add quirks to enable this
workaround to fix it to the max value 0xE.

2. Add CONFIG_SYS_FSL_ERRATUM_ESDHC111 to enable its workaround.

* Update of patch for change mmc interface by
	Pantelis Antoniou <panto@antoniou-consulting.com>

Signed-off-by: Haijun Zhang <Haijun.Zhang@freescale.com>
Acked-by: Pantelis Antoniou <panto@antoniou-consulting.com>
2014-04-02 13:25:01 +03:00
Tom Rini
247161b816 Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx 2014-03-07 20:54:22 -05:00
Priyanka Jain
bf4699db85 powerpc/mpc85xx: Add SCFG_PIXCLKCR register support for T1040
T1040 SoC has SCFG (Supplement Configuration) Block which provides
chip specific configuration and status support. The base address of
SCFG block in T1040 is 0xfc000.
SCFG contains SCFG_PIXCLKCR (DIU pixel clock control register)
at offset 0x28.

Add definition of
-SCFG block
-SCFG_PIXCLKCR register
-Bits definition of SCFG_PIXCLK register

Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-03-07 14:53:29 -08:00
Suresh Gupta
9c641a872a powerpc/usb: Workaround for erratum-A006261
USB spec says that the minimum disconnect threshold should be
	over 525 mV. However, internal USB PHY threshold value is below
	this specified value. Due to this some devices disconnect at
	run-time. Hence, phy settings are tweaked to increased disconnect
	threshold to be above 525mV by using this workaround.

Signed-off-by: Suresh Gupta <suresh.gupta@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-03-07 14:52:16 -08:00
Shaveta Leekha
7af9a07403 powerpc/b4860: Add workaround for errata A006384 and A006475
SerDes PLLs may not lock reliably at 5 G VCO configuration(A006384)
and at cold temperatures(A006475), workaround recalibrate the
PLLs with some SerDes configuration

Both these errata are only applicable for b4 rev1.
So, make workaround for these errata conditional,
depending upon soc version.

Signed-off-by: Shaveta Leekha <shaveta@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-03-07 14:52:01 -08:00
Shaveta Leekha
6df82e3c0f B4860/B4420: Add PLL_NUM define for B4420/B4860 to use SerDes2 Refclks re-configuration
B4860 has two PLL per SerDes whereas B4420 has one PLL per SerDes,
add their defines in arch/powerpc/include/asm/config_mpc85xx.h

Signed-off-by: Shaveta Leekha <shaveta@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-03-07 14:50:10 -08:00