Commit graph

61 commits

Author SHA1 Message Date
Kumar Gala
a036b04436 MPC8610HPCD: Report board id, board version and fpga version.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2008-06-19 08:32:18 -05:00
Becky Bruce
9973e3c614 Change initdram() return type to phys_size_t
This patch changes the return type of initdram() from long int to phys_size_t.
This is required for a couple of reasons: long int limits the amount of dram
to 2GB, and u-boot in general is moving over to phys_size_t to represent the
size of physical memory.  phys_size_t is defined as an unsigned long on almost
all current platforms.

This patch *only* changes the return type of the initdram function (in
include/common.h, as well as in each board's implementation of initdram).  It
does not actually modify the code inside the function on any of the platforms;
platforms which wish to support more than 2GB of DRAM will need to modify
their initdram() function code.

Build tested with MAKEALL for ppc, arm, mips, mips-el. Booted on powerpc
MPC8641HPCN.

Signed-off-by: Becky Bruce <becky.bruce@freescale.com>
2008-06-12 08:50:18 +02:00
Jon Loeliger
2c289e320d mpc86xx: Removed unused and unconfigured memory test code.
Besides, other common code exists.

Signed-off-by: Jon Loeliger <jdl@freescale.com>
2008-05-19 09:47:25 -05:00
Kumar Gala
45239cf415 85xx/86xx: Rename ext_refrec to timing_cfg_3 to match docs
All the 85xx and 86xx UM describe the register as timing_cfg_3
not as ext_refrec.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2008-04-29 11:44:29 -05:00
Jon Loeliger
a30a549a35 Remove erroneous or extra spd.h #includers.
Many of the spd.h #includers don't need it,
and wanted to have spd_sdram() declared instead.
Since they didn't get that, some also had open
coded extern declarations of it instead or as well.
Fix it all up by using spd_sdram.h where needed.

Signed-off-by: Jon Loeliger <jdl@freescale.com>
2008-03-05 00:17:43 +01:00
Jon Loeliger
a551cee99a 86xx: Fix GUR PCI config registers properly.
Back in commit 975a083a5e where
I tried to "8610HPCD: Fix typos in two PCI setup registers", I
botched it due to not realizing that 8610 and 8641 had different
Global Utility Register defintions, one of which was like 85xx,
and the other wasn't.  Correct this problem by introducing two
symbols, one for each 86xx SoC, but neither of which is named
anything like 85xx.

My bad.  Lovely Wednesday with git bisect.  You know.

Signed-off-by: Jon Loeliger <jdl@freescale.com>
2008-02-20 14:45:09 -06:00
Jon Loeliger
975a083a5e 8610HPCD: Fix typos in two PCI setup registers.
The two symbols MPC86xx_PORDEVSR_IO_SEL and MPC86xx_PORBMSR_HA
were erroneously present as 85xx names and values, leftover from
the clone wars.  Fix this by removing the 85xx cruft from the
86xx codebase.

Signed-off-by: Jon Loeliger <jdl@freescale.com>
2008-02-19 12:31:08 -06:00
Jon Loeliger
1df170f8b2 Convert MPC8610HPCD to use libfdt.
Assumes the presence of the aliases node in the DTS to
locate the pci and serial nodes for fixups.

Use consistent fdtaddr and fdtfile in environment variables.

Signed-off-by: Jon Loeliger <jdl@freescale.com>
2008-01-09 10:47:31 -06:00
Jon Loeliger
c9974ab0a4 8610: Fix lingering compile warnings.
Turn off DEBUG.

Signed-off-by: Jon Loeliger <jdl@freescale.com>
2008-01-09 10:47:30 -06:00
York Sun
a877880c69 8610: Add 8610 DIU display driver
1280x1024 and 1024x768 @ 32 bpp are supported now.
DVI, Single-link LVDS, Double-link LVDS are all supported.

Environmental variable "monitor" is used to specify monitor port.

A new command "diufb" is introduced to reinitialize monitor
and display a BMP file in the memory. So far, 1-bit, 4-bit,
8-bit and 24-bit BMP formats are supported.

    diufb init
        - initialize the diu driver
    Enable the port specified in the environmental variable "monitor"

    diufb addr
        - display bmp file in memory.
    The bmp image should be no bigger than the resolution, 1280x1024
    for DVI and double-link LVDS, 1024x768 for single-link LVDS.

Note, this driver allocate memory but doesn't free it after use
It is written on purpose -- to avoid a failure of reallocation
due to memory fragement.

ECC of DDR is disabled for DIU performance. L2 data cache is also disabled.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Jon loeliger <jdl@freescale.com>
2007-11-07 14:09:09 -06:00
Jon Loeliger
3dd2db53ce Initial mpc8610hpcd board files.
Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com>
Signed-off-by: Mahesh Jade <mahesh.jade@freescale.com>
Signed-off-by: Jason Jin <Jason.jin@freescale.com>
Signed-off-by: Jon Loeliger <jdl@freescale.com>
2007-10-17 15:01:33 -05:00