Commit graph

2338 commits

Author SHA1 Message Date
kevin.morfitt@fearnside-systems.co.uk
cd85662b34 CONFIG_SYS_HZ fix for ARM902T S3C24X0 Boards
This sets CONFIG_SYS_HZ to 1000 for all boards that use the s3c2400 and
s3c2410 cpu's which fixes various problems such as the timeouts in tftp being
too short.

Tested on an Embest SBC2440-II Board with local u-boot patches as I don't
have any s3c2400 or s3c2410 boards but need this patch applying before I can
submit patches for the SBC2440-II Board. Also, ran MAKEALL for all ARM9 targets
and no new warnings or errors were found.

It was originally submitted on 21/06/2009 but didn't get into the 2009.08
release, and Jean-Pierre made one comment on the original patch (see
http://lists.denx.de/pipermail/u-boot/2009-July/055470.html). I've made two
changes to the original patch:
- it's been re-based to the current release
- I've re-named get_timer_raw() to get_ticks() in response to Jean-Pierre's comment

This affects the sbc2410, smdk2400, smdk2410 and trab boards. I've copied it
directly to the maintainers of all except the sbc2410 which doesn't have an
entry in MAINTAINERS.

Signed-off-by: Kevin Morfitt <kmorfitt@aselaptop-1.localdomain>
Tested-by: Wolfgang Denk <wd@denx.de>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2009-10-13 21:13:55 -05:00
Minkyu Kang
399e5ae0d0 s5pc1xx: support Samsung s5pc1xx SoC
This patch adds support for the Samsung s5pc100 and s5pc110
SoCs. The s5pc1xx SoC is an ARM Cortex A8 processor.

Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Signed-off-by: HeungJun, Kim <riverful.kim@samsung.com>
2009-10-13 21:13:55 -05:00
Simon Kagstrom
9df20ce211 arm: Correct build with CONFIG_SYS_HUSH_PARSER set
FLAG_PARSE_SEMICOLON is not defined without hush.h, so include that.

Signed-off-by: Simon Kagstrom <simon.kagstrom@netinsight.net>
Signed-off-by: Prafulla Wadaskar <prafulla@marvell.com>
2009-10-13 06:17:38 -05:00
Tom Rix
23b80982a0 Add support for Eukrea CPU9260/CPU9G20 SBC
these boards are built around Atmel's AT91SAM9260/9G20 and have
up to 64MB of NOR flash, up to 128MB of SDRAM, up to 2GB of NAND
and include a 10/100 Ethernet PHY in RMII mode.

Signed-off-by: Eric Benard <eric@eukrea.com>
Signed-off-by: Tom Rix <Tom.Rix@windriver.com>
2009-10-13 06:17:35 -05:00
Tom Rix
d8380c9d35 Add support for Eukrea CPUAT91 SBC
CPUAT91 is built around Atmel's AT91RM9200 and has up to 16MB of NOR
flash, up to 128MB of SDRAM, and includes a Micrel KS8721 PHY in RMII
mode.

Signed-off-by: Eric Benard <eric@eukrea.com>
Signed-off-by: Tom Rix <Tom.Rix@windriver.com>
2009-10-13 06:17:35 -05:00
Sandeep Paulraj
7908c97a10 TI DaVinci: DM646x: Initial Support for DM646x SOC
DM646x is an SOC from TI which has both an ARM and a DSP.
There are multiple variants of the SOC mainly dealing with different
core speeds.
This patch adds the initial framework for the DM646x SOC.

Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
2009-10-13 06:17:34 -05:00
Tom Rix
7a2aa8b681 OMAP3 Move cache routine to cache.S
v7_flush_dcache_all, because it depends on omap ROM code is not
generic.  Rename the function to 'invalidate_dcache' and move it
to the omap cpu directory.

Collect the other omap cache routines l2_cache_enable and
l2_cache_disable with invalide_dcache into cache.S.  This
means removing the old cache.c file that contained l2_cache_enable
and l2_cache_disable.

The conversion from cache.c to cache.S was done most through
disassembling the uboot binary.  The only significant change was
to change the comparision for the return of get_cpu_rev from

   cmp	r0, #0
   beq	earlier_than_label

Which was lost information to

   cmp	r0, #CPU_3XX_ES20
   blt	earlier_than_label

The paths through the enable routine were verified by
adding an infinite loop and seeing the hang.  Then
removing the infinite loop and seeing it continue.

The disable routine is similar enough that it was not
tested with this method.

Run tested by cold booting from nand on beagle and zoom1.
Compile tested on MAKEALL arm.

Signed-off-by: Tom Rix <Tom.Rix@windriver.com>
2009-10-13 06:17:33 -05:00
Wolfgang Denk
cd77dd109c Merge branch 'reloc' 2009-10-09 00:03:18 +02:00
Joakim Tjernlund
afc3ba0fc4 relocation: Do not relocate NULL pointers.
NULL is an absolute value and should not be relocated.
After this correction code like:
 void weak_fun(void) __attribute__((weak));
 printf("weak_fun:%p\n", weak_fun);
will still print null after relocation.

Signed-off-by: Joakim Tjernlund <Joakim.Tjernlund@transmode.se>
2009-10-08 09:33:36 +02:00
Peter Tyser
3beb40c247 85xx: Ensure BSS segment isn't linked at address 0
When U-Boot is relocated from flash to RAM pointers are modified
accordingly.  However, pointers initialzed with NULL values should not
be modified so that they maintain their intended NULL value.  If the
BSS segment is linked at address 0 its address will not be
updated as necessary during relocation.

This is a temporary workaround.  The end goal is to add support to
U-Boot to dynamically locate the BSS at an arbitrary address at
runtime.  When the ability to fixup the BSS inteligently is
added, this workaround can be removed and the 85xx link script
can put the BSS at a fixed address at link time.

Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
2009-10-08 00:33:47 +02:00
Wolfgang Denk
da01f53404 mpc512x: fix fixed_sdram() init code.
Commit 054197ba and later fixes used an array to initialize some of
the MDDRC parameters; however, the use of an array turned out to be a
bad idea as it was not possible to correlate structure entries to
array indices in readable and reliable way. Now we use a struct
instead, which makes this self-explanatory.

Signed-off-by: Wolfgang Denk <wd@denx.de>
2009-10-08 00:23:12 +02:00
Niklaus Giger
78d2a64137 ppc4xx: Rework cmd reginfo
The command "reginfo" got an overhaul for the ppc4xx. It dumps all the
relevant HW configuration registers (address, symbolic name, content).
This allows to easily detect errors in *.h files and changes in the HW
configuration.

Signed-off-by: Niklaus Giger <niklaus.giger@member.fsf.org>
Signed-off-by: Stefan Roese <sr@denx.de>
2009-10-07 09:15:26 +02:00
Niklaus Giger
ddc922ff2c ppc_4xx: Apply new HW register names
Modify all existing *.c files to use the new register names
as seen in the AMCC manuals.

Signed-off-by: Niklaus Giger <niklaus.giger@member.fsf.org>
Signed-off-by: Stefan Roese <sr@denx.de>
2009-10-07 09:15:20 +02:00
Stefan Roese
56f14818f6 ppc4xx: Add PPC405EX(r) Rev D support
Unfortunately some Rev D PPC405EX/405EXr PVR's are identical with older
405EX(r) parts. Here a list:

0x12911475 - 405EX Rev D with Security *and* 405EX Rev A/B witout Sec
0x12911473 - 405EX Rev D without Security *and* 405EXr Rev A/B with Sec

Since there are only a few older parts in the field, this patch now
changes the PVR's above to represent the new Rev D versions.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Phong Vo" <pvo@amcc.com>
2009-10-07 09:14:27 +02:00
Stefan Roese
06dfaeef52 ppc4xx: Fix msg "initialization as root-complex failed" upon PCIe scan
This message is printed upon PCIe bus scan, not only upon error, but also
if no PCIe device is detected at all. Since this is not an error, let's
remove this message in this case. We already have the message
"link is not up." if there is no PCIe device present.

Signed-off-by: Stefan Roese <sr@denx.de>
Acked-by: Wolfgang Denk <wd@denx.de>
2009-10-07 09:13:46 +02:00
Mike Nuss
54f5f056aa PPC4xx: Denali core: Fix incorrect DDR row bits
The SPD detection code for the Denali memory controller used on some
ppc4xx
processors incorrectly encodes DDR0_42. With certain memory
configurations,
this can cause the bootwrapper to incorrectly calculate the installed
memory
size, because the number of row bits is wrong. This patch fixes that
encoding.

Signed-off-by: Mike Nuss <mike@terascala.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2009-10-07 09:10:11 +02:00
Peter Tyser
858290178f ppc: Enable full relocation to RAM
The following changes allow U-Boot to fully relocate from flash to
RAM:
 - Remove linker scripts' .fixup sections from the .text section
 - Add -mrelocatable to PLATFORM_RELFLAGS for all boards
 - Define CONFIG_RELOC_FIXUP_WORKS for all boards

Previously, U-Boot would partially relocate, but statically initialized
pointers needed to be manually relocated.

Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
2009-10-03 10:15:45 +02:00
Stefan Roese
fb95169e39 ppc4xx: Merge PPC4xx DDR and DDR2 ECC handling
This patch merges the ECC handling (ECC parity byte writing) into one
file (ecc.c) for all PPC4xx SDRAM controllers except for PPC440EPx/GRx.
This exception is because only those PPC's use the completely different
Denali SDRAM controller core.

Previously we had two routines to generate/write the ECC parity bytes.
With this patch we now only have one core function left.

Tested on Kilauea (no ECC) and Katmai (with and without ECC).

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Felix Radensky <felix@embedded-sol.com>
Cc: Grant Erickson <gerickson@nuovations.com>
Cc: Pieter Voorthuijsen <pv@prodrive.nl>
2009-10-02 13:53:37 +02:00
Felix Radensky
d24bd2517a ppc4xx: Reorganize DDR2 ECC handling
Reorganize DDR2 ECC handling to use common code for
SPD DIMMs and soldered SDRAM. Also, use common code
to display SDRAM info (ECC, CAS latency) for SPD and
soldered SDRAM variants.

Signed-off-by: Felix Radensky <felix@embedded-sol.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2009-10-02 13:53:28 +02:00
Wolfgang Denk
9ae7ae6b4d Merge branch 'master' of git://git.denx.de/u-boot-ppc4xx 2009-09-30 23:26:59 +02:00
Stefan Roese
b306db2f1b ppc4xx: Remove mtsdram0() marcos and use common mtsdram() instead
Additionally some whitespace coding style fixes.

Signed-off-by: Stefan Roese <sr@denx.de>
2009-09-28 10:46:05 +02:00
Stefan Roese
95b602bab5 ppc4xx: Convert PPC4xx SDRAM defines from lower case to upper case
The latest PPC4xx register cleanup patch missed some SDRAM defines.
This patch now changes lower case UIC defines to upper case. Also
some names are changed to match the naming in the IBM/AMCC users
manuals (e.g. mem_mcopt1 -> SDRAM0_CFG).

Signed-off-by: Stefan Roese <sr@denx.de>
2009-09-28 10:45:54 +02:00
Stefan Roese
952e7760bf ppc4xx: Convert PPC4xx UIC defines from lower case to upper case
The latest PPC4xx register cleanup patch missed the UIC defines.
This patch now changes lower case UIC defines to upper case.

Signed-off-by: Stefan Roese <sr@denx.de>
2009-09-28 10:45:42 +02:00
Kim Phillips
c7190f028f mpc83xx: retain POR values of non-configured ACR, SPCR, SCCR, and LCRR bitfields
some LCRR bits are not documented throughout the 83xx family RMs.
New board porters copying similar board configurations might omit
setting e.g., DBYP since it was not documented in their SoC's RM.

Prevent them bricking their board by retaining power on reset values
in bit fields that the board porter doesn't explicitly configure
via CONFIG_SYS_<registername>_<bitfield> assignments in the board
config file.

also move LCRR assignment to cpu_init_r[am] to help ensure no
transactions are being executed via the local bus while CLKDIV is being
modified.

also start to use i/o accessors.

Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2009-09-26 21:19:38 -05:00
Heiko Schocher
3887c3fbdb mucmc52, uc101: delete ata@3a00 node, if no CF card is detected
U-Boot can detect if an IDE device is present or not.
If not, and this new config option is activated, U-Boot
removes the ATA node from the DTS before booting Linux,
so the Linux IDE driver does not probe the device and
crash. This is needed for buggy hardware (uc101) where
no pull down resistor is connected to the signal IDE5V_DD7.

Signed-off-by: Heiko Schocher <hs@denx.de>
2009-09-25 01:22:13 +02:00
Martha M Stan
054197ba8e mpc512x: Streamlined fixed_sdram() init sequence.
Signed-off-by: Martha M Stan <mmarx@silicontkx.com>

Minor cleanup:

Re-ordered default_mddrc_config[] to have matching indices.

This allows to use the same index "N" for source and target fields;
before, we had code like this

	out_be32(&im->mddrc.ddr_time_config2, mddrc_config[3]);

which always looked like a copy & paste error because 2 != 3.

Also, use NULL when meaning a null pointer.

Signed-off-by: Wolfgang Denk <wd@denx.de>
2009-09-25 00:45:30 +02:00
Kumar Gala
39aaca1f66 ppc/p4080: Determine various chip frequencies on CoreNet platforms
The means to determine the core, bus, and DDR frequencies are completely
new on CoreNet style platforms.  Additionally on p4080 we can have
different frequencies for FMAN and PME IP blocks.  We need to keep track
of the FMAN & PME frequencies since they are used for time stamping
capabilities inside each block.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-09-24 12:05:29 -05:00
Kumar Gala
3c2a67eec8 ppc/p4080: Handle timebase enabling and frequency reporting
On CoreNet style platforms the timebase frequency is the bus frequency
defined by 16 (on PQ3 it is divide by 8).  Also on the CoreNet platforms
the core not longer controls the enabling of the timebase.  We now need
to enable the boot core's timebase via CCSR register writes.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-09-24 12:05:29 -05:00
Kumar Gala
7e4259bba4 ppc/p4080: Add various p4080 related defines (and p4040)
There are various locations that we have chip specific info:

* Makefile for which ddr code to build
* Added p4080 & p4040 to cpu_type_list and SVR list
* Added number of LAWs for p4080
* Set CONFIG_MAX_CPUS to 8 for p4080

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-09-24 12:05:28 -05:00
Kumar Gala
39a7e7fd53 ppc/p4080: CoreNet platfrom style secondary core release
The CoreNet platform style of bringing secondary cores out of reset is
a bit different that the PQ3 style.  Mostly the registers that we use
to setup boot translation, enable time bases, and boot release the cores
have moved around.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-09-24 12:05:28 -05:00
Kumar Gala
a880cf3e0e ppc/p4080: CoreNet platfrom style CCSRBAR setting
On CoreNet based platforms the CCSRBAR address is split between an high &
low register and we no longer shift the address.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Signed-off-by: Scott Wood <scottwood@freescale.com>
2009-09-24 12:05:28 -05:00
Kumar Gala
25bacf7a2b ppc/85xx: Fix enabling of L2 cache
We need to flash invalidate the locks in addition to the cache
before we enable.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-09-24 12:05:27 -05:00
Vivek Mahajan
cb0ff65c61 85xx-fdt: Fixed l2-ctlr's compatible prop for QorIQ
The code assumed names where just numbers and always prefixed 'mpc'.
However newer QorIQ don't follow the mpc naming scheme.

Signed-off-by: Vivek Mahajan <vivek.mahajan@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-09-24 12:05:27 -05:00
Mingkai Hu
234a89d911 ppc/85xx: add cpu init config file for boot from NAND
When boot from NAND, the NAND flash must be connected to br/or0.
Also init RAM(L2 SRAM or DDR SDRAM) for load the second image to
it.

Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-09-24 12:05:26 -05:00
Mingkai Hu
098bcbae31 ppc/85xx: add ld script file for boot from NAND
The first stage 4K image uses a seperate ld script file to
generate 4K image. This patch moves it to the cpu/mpc85xx/*
to make it avaliable for 85xx platform.

Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-09-24 12:05:25 -05:00
Rupjyoti Sarmah
fcdb36b85a ppc4xx: Fix PCIE PLL lock on 440SPe Yucca board
u-boot reports a PCIE PLL lock error at boot time on Yucca board, and
left PCIe nonfunctional. This is fixed by making u-boot function
ppc4xx_init_pcie() to wait 300 uS after negating reset before the
first check of the PLL lock.

Signed-off-by: Rupjyoti Sarmah <rsarmah@amcc.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2009-09-23 15:46:08 +02:00
Stefan Roese
e67af44d01 ppc4xx: Consolidate get_OPB_freq()
All 4xx variants had their own, mostly identical get_OPB_freq()
function. Some variants even only had the OPB frequency calculated
in this routine and not supplied the sys_info.freqOPB variable
correctly (e.g. 405EZ). This resulted in incorrect OPB values passed
via the FDT to Linux.

This patch now removes all those copies and only uses one function
for all 4xx variants (except for IOP480 which doesn't have an OPB).

Signed-off-by: Stefan Roese <sr@denx.de>
2009-09-17 14:08:32 +02:00
Stefan Roese
95a4a593b5 ppc4xx: Fix 405EZ uart base baud calculation
With this fix, Linux correctly configures the baudrate when booting
with FDT passed from U-Boot to Linux.

Signed-off-by: Stefan Roese <sr@denx.de>
2009-09-17 14:05:52 +02:00
Kumar Gala
15fba3279b ppc/85xx: Disable all async interrupt sources when we boot
We should make sure to clear MSR[ME, CE, DE] when we boot an OS image
since we have changed the exception vectors and the OSes vectors might
not be setup we should avoid async interrupts at all costs.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-09-15 21:30:09 -05:00
Kumar Gala
9f00409a9d ppc/85xx: Split out cpu_init_early into its own file for NAND_SPL
By pulling out cpu_init_early we can build just it and not all of
cpu_init for NAND_SPL.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-09-15 21:30:09 -05:00
Kumar Gala
0456dbf347 ppc/85xx: Change cpu_init_early_f so we can use with NAND SPL
Use write_tlb and don't use memset so we can use the same code for
cpu_init_early_f between NAND SPL and not.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-09-15 21:30:09 -05:00
Mingkai Hu
7da53351d8 ppc/85xx: add boot from NAND/eSDHC/eSPI support
The MPC8536E is capable of booting form NAND/eSDHC/eSPI, this patch
implements these three bootup methods in a unified way - all of these
use the general cpu/mpc85xx/start.S, and load the main image to L2SRAM
which lets us use the SPD to initialize the SDRAM.

For all three bootup methods, the bootup process can be divided into two
stages: the first stage will initialize the corresponding controller,
configure the L2SRAM, then copy the second stage image to L2SRAM and
jump to it. The second stage image is just like the general U-Boot image
to configure all the hardware and boot up to U-Boot command line.

When boot from NAND, the eLBC controller will first load the first stage
image to internal 4K RAM buffer because it's also stored on the NAND
flash. The first stage image, also call 4K NAND loader, will initialize
the L2SRAM, load the second stage image to L2SRAM and jump to it. The 4K
NAND loader's code comes from the corresponding nand_spl directory, along
with the code twisted by CONFIG_NAND_SPL.

When boot from eSDHC/eSPI, there's no such a first stage image because
the CPU ROM code does the same work. It will initialize the L2SRAM
according to the config addr/word pairs on the fixed address and
initialize the eSDHC/eSPI controller, then load the second stage image
to L2SRAM and jump to it.

The macro CONFIG_SYS_RAMBOOT is used to control the code to produce the
second stage image for all different bootup methods. It's set in the
board config file when one of the bootup methods above is selected.

Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-09-15 21:30:09 -05:00
Kumar Gala
b2eec281a8 ppc/85xx: Move code around to prep for NAND_SPL
If we move some of the functions in tlb.c around we need less
ifdefs.  The first stage loader just needs invalidate_tlb and
init_tlbs.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-09-15 21:30:09 -05:00
Kumar Gala
206af3527c ppc/85xx: Repack tlb_table to save space
We can pack the initial tlb_table in MAS register format and use
write_tlb to set things up.  This savings can be helpful for NAND
style first stage boot loaders.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-09-15 21:30:09 -05:00
Kumar Gala
d30f904353 ppc/85xx: Introduce low level write_tlb function
Factor out the code we use to actually write a tlb entry.

set_tlb is a logical view of the TLB while write_tlb is a low level
matching the MAS registers.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-09-15 21:30:08 -05:00
Kumar Gala
6d8565a1ed ppc/8xxx: Misc DDR related fixes
* Fix setting of ESDMODE (MR1) register - the bit shifting was wrong
* Fix the format string to match size in a debug print

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-09-15 21:30:08 -05:00
Scott Wood
3e3c9c157b ppc/85xx: Remove some bogus code from external interrupt handler.
Skipping the interrupted instruction will accomplish nothing other
than turning a spurious interrupt into a crash.

External interrupts are not machine checks, so don't count them as such.

Signed-off-by: Scott Wood <scottwood@freescale.com>
2009-09-15 21:30:08 -05:00
Scott Wood
dcc87dd58d ppc/85xx: Ensure that MAS8 is zero when writing TLB entries.
Its reset value is random, and we sometimes read uninitialized TLB
arrays.  Make sure that we don't retain MAS8 from reading such an entry
if the VF bit in MAS8 is set, attempts to use the mapping will trap.

Signed-off-by: Scott Wood <scottwood@freescale.com>
2009-09-15 21:30:08 -05:00
Scott Wood
1b72dbecca ppc/85xx: Don't enable interrupts before we're ready
We cannot handle any exceptions while running in AS1, as the exceptions
will transition back to AS0 without a valid mapping.

Signed-off-by: Scott Wood <scottwood@freescale.com>
2009-09-15 21:30:07 -05:00
Stefan Roese
d1c3b27525 ppc4xx: Big cleanup of PPC4xx defines
This patch cleans up multiple issues of the 4xx register (mostly
DCR, SDR, CPR, etc) definitions:

- Change lower case defines to upper case (plb4_acr -> PLB4_ACR)
- Change the defines to better match the names from the
  user's manuals (e.g. cprpllc -> CPR0_PLLC)
- Removal of some unused defines

Please test this patch intensive on your PPC4xx platform. Even though
I tried not to break anything and tested successfully on multiple
4xx AMCC platforms, testing on custom platforms is recommended.

Signed-off-by: Stefan Roese <sr@denx.de>
2009-09-11 10:35:58 +02:00