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https://github.com/AsahiLinux/u-boot
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ppc4xx: Merge PPC4xx DDR and DDR2 ECC handling
This patch merges the ECC handling (ECC parity byte writing) into one file (ecc.c) for all PPC4xx SDRAM controllers except for PPC440EPx/GRx. This exception is because only those PPC's use the completely different Denali SDRAM controller core. Previously we had two routines to generate/write the ECC parity bytes. With this patch we now only have one core function left. Tested on Kilauea (no ECC) and Katmai (with and without ECC). Signed-off-by: Stefan Roese <sr@denx.de> Cc: Felix Radensky <felix@embedded-sol.com> Cc: Grant Erickson <gerickson@nuovations.com> Cc: Pieter Voorthuijsen <pv@prodrive.nl>
This commit is contained in:
parent
d24bd2517a
commit
fb95169e39
6 changed files with 179 additions and 263 deletions
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@ -9,7 +9,7 @@
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* Copyright (c) 2008 Nuovation System Designs, LLC
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* Grant Erickson <gerickson@nuovations.com>
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* (C) Copyright 2007-2008
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* (C) Copyright 2007-2009
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* Stefan Roese, DENX Software Engineering, sr@denx.de.
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*
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* COPYRIGHT AMCC CORPORATION 2004
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@ -48,6 +48,8 @@
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#include <asm/mmu.h>
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#include <asm/cache.h>
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#include "ecc.h"
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#if defined(CONFIG_SDRAM_PPC4xx_IBM_DDR2)
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#define PPC4xx_IBM_DDR2_DUMP_REGISTER(mnemonic) \
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@ -93,24 +95,11 @@ void dcbz_area(u32 start_address, u32 num_bytes);
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#define MULDIV64(m1, m2, d) (u32)(((u64)(m1) * (u64)(m2)) / (u64)(d))
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static unsigned long is_ecc_enabled(void);
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/*-----------------------------------------------------------------------------+
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* wait_ddr_idle
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*-----------------------------------------------------------------------------*/
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static void wait_ddr_idle(void)
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{
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u32 val;
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do {
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mfsdram(SDRAM_MCSTAT, val);
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} while ((val & SDRAM_MCSTAT_IDLE_MASK) == SDRAM_MCSTAT_IDLE_NOT);
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}
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#if !defined(CONFIG_NAND_SPL)
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/*-----------------------------------------------------------------------------+
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* sdram_memsize
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*-----------------------------------------------------------------------------*/
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static phys_size_t sdram_memsize(void)
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phys_size_t sdram_memsize(void)
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{
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phys_size_t mem_size;
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unsigned long mcopt2;
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@ -183,6 +172,18 @@ static phys_size_t sdram_memsize(void)
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return mem_size << 20;
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}
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/*-----------------------------------------------------------------------------+
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* is_ecc_enabled
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*-----------------------------------------------------------------------------*/
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static unsigned long is_ecc_enabled(void)
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{
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unsigned long val;
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mfsdram(SDRAM_MCOPT1, val);
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return SDRAM_MCOPT1_MCHK_CHK_DECODE(val);
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}
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/*-----------------------------------------------------------------------------+
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* board_add_ram_info
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*-----------------------------------------------------------------------------*/
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@ -198,12 +199,11 @@ void board_add_ram_info(int use_default)
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get_sys_info(&board_cfg);
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#if defined(CONFIG_440)
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#if defined(CONFIG_405EX)
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val = board_cfg.freqPLB;
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#else
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mfsdr(SDR0_DDR0, val);
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val = MULDIV64((board_cfg.freqPLB), SDR0_DDR0_DDRM_DECODE(val), 1);
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#else
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mfsdr(SDR0_SDSTP0, val);
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val = MULDIV64((board_cfg.freqPLB), SDR0_SDSTP0_PLB2xDV0_DECODE(val), 1);
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#endif
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printf(" enabled, %d MHz", (val * 2) / 1000000);
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@ -211,112 +211,7 @@ void board_add_ram_info(int use_default)
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val = (val & SDRAM_MMODE_DCL_MASK) >> 4;
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printf(", CL%d)", val);
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}
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#ifdef CONFIG_DDR_ECC
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/*-----------------------------------------------------------------------------+
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* program_ecc_addr.
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*-----------------------------------------------------------------------------*/
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static void program_ecc_addr(unsigned long start_address,
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unsigned long num_bytes,
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unsigned long tlb_word2_i_value)
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{
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unsigned long current_address;
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unsigned long end_address;
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unsigned long address_increment;
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unsigned long mcopt1;
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char str[] = "ECC generation -";
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char slash[] = "\\|/-\\|/-";
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int loop = 0;
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int loopi = 0;
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current_address = start_address;
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mfsdram(SDRAM_MCOPT1, mcopt1);
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if ((mcopt1 & SDRAM_MCOPT1_MCHK_MASK) != SDRAM_MCOPT1_MCHK_NON) {
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mtsdram(SDRAM_MCOPT1,
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(mcopt1 & ~SDRAM_MCOPT1_MCHK_MASK) | SDRAM_MCOPT1_MCHK_GEN);
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sync();
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eieio();
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wait_ddr_idle();
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puts(str);
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#ifdef CONFIG_440
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if (tlb_word2_i_value == TLB_WORD2_I_ENABLE) {
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#endif
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/* ECC bit set method for non-cached memory */
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if ((mcopt1 & SDRAM_MCOPT1_DMWD_MASK) == SDRAM_MCOPT1_DMWD_32)
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address_increment = 4;
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else
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address_increment = 8;
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end_address = current_address + num_bytes;
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while (current_address < end_address) {
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*((unsigned long *)current_address) = 0x00000000;
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current_address += address_increment;
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if ((loop++ % (2 << 20)) == 0) {
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putc('\b');
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putc(slash[loopi++ % 8]);
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}
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}
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#ifdef CONFIG_440
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} else {
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/* ECC bit set method for cached memory */
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dcbz_area(start_address, num_bytes);
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/* Write modified dcache lines back to memory */
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clean_dcache_range(start_address, start_address + num_bytes);
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}
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#endif /* CONFIG_440 */
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blank_string(strlen(str));
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sync();
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eieio();
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wait_ddr_idle();
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/* clear ECC error repoting registers */
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mtsdram(SDRAM_ECCCR, 0xffffffff);
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mtdcr(0x4c, 0xffffffff);
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mtsdram(SDRAM_MCOPT1,
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(mcopt1 & ~SDRAM_MCOPT1_MCHK_MASK) | SDRAM_MCOPT1_MCHK_CHK_REP);
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sync();
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eieio();
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wait_ddr_idle();
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}
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}
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/*-----------------------------------------------------------------------------+
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* do_program_ecc.
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*-----------------------------------------------------------------------------*/
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static void do_program_ecc(unsigned long tlb_word2_i_value)
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{
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unsigned long mcopt1;
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unsigned long mcopt2;
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unsigned long mcstat;
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phys_size_t memsize = sdram_memsize();
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if (memsize > CONFIG_MAX_MEM_MAPPED) {
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printf("\nWarning: Can't enable ECC on systems with more than 2GB of SDRAM!\n");
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return;
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}
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mfsdram(SDRAM_MCOPT1, mcopt1);
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mfsdram(SDRAM_MCOPT2, mcopt2);
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if ((mcopt1 & SDRAM_MCOPT1_MCHK_MASK) != SDRAM_MCOPT1_MCHK_NON) {
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/* DDR controller must be enabled and not in self-refresh. */
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mfsdram(SDRAM_MCSTAT, mcstat);
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if (((mcopt2 & SDRAM_MCOPT2_DCEN_MASK) == SDRAM_MCOPT2_DCEN_ENABLE)
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&& ((mcopt2 & SDRAM_MCOPT2_SREN_MASK) == SDRAM_MCOPT2_SREN_EXIT)
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&& ((mcstat & (SDRAM_MCSTAT_MIC_MASK | SDRAM_MCSTAT_SRMS_MASK))
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== (SDRAM_MCSTAT_MIC_COMP | SDRAM_MCSTAT_SRMS_NOT_SF))) {
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program_ecc_addr(0, memsize, tlb_word2_i_value);
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}
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}
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}
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#endif /* CONFIG_DDR_ECC */
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#endif /* !CONFIG_NAND_SPL */
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#if defined(CONFIG_SPD_EEPROM)
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@ -439,7 +334,6 @@ typedef enum ddr_cas_id {
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/*-----------------------------------------------------------------------------+
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* Prototypes
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*-----------------------------------------------------------------------------*/
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static phys_size_t sdram_memsize(void);
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static void get_spd_info(unsigned long *dimm_populated,
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unsigned char *iic0_dimm_addr,
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unsigned long num_dimm_banks);
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@ -2405,25 +2299,6 @@ static void program_memory_queue(unsigned long *dimm_populated,
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#endif
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}
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/*-----------------------------------------------------------------------------+
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* is_ecc_enabled.
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*-----------------------------------------------------------------------------*/
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static unsigned long is_ecc_enabled(void)
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{
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unsigned long dimm_num;
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unsigned long ecc;
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unsigned long val;
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ecc = 0;
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/* loop through all the DIMM slots on the board */
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for (dimm_num = 0; dimm_num < MAXDIMMS; dimm_num++) {
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mfsdram(SDRAM_MCOPT1, val);
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ecc = max(ecc, SDRAM_MCOPT1_MCHK_CHK_DECODE(val));
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}
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return ecc;
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}
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#ifdef CONFIG_DDR_ECC
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/*-----------------------------------------------------------------------------+
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* program_ecc.
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@ -2989,21 +2864,6 @@ static void test(void)
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#else /* CONFIG_SPD_EEPROM */
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/*-----------------------------------------------------------------------------+
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* is_ecc_enabled
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*-----------------------------------------------------------------------------*/
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static unsigned long is_ecc_enabled(void)
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{
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unsigned long ecc;
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unsigned long val;
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ecc = 0;
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mfsdram(SDRAM_MCOPT1, val);
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ecc = max(ecc, SDRAM_MCOPT1_MCHK_CHK_DECODE(val));
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return ecc;
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}
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/*-----------------------------------------------------------------------------
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* Function: initdram
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* Description: Configures the PPC4xx IBM DDR1/DDR2 SDRAM memory controller.
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@ -3225,18 +3085,6 @@ void mtdcr_any(u32 dcr, u32 val)
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}
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}
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#endif /* defined(CONFIG_440) */
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void blank_string(int size)
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{
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int i;
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for (i = 0; i < size; i++)
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putc('\b');
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for (i = 0; i < size; i++)
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putc(' ');
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for (i = 0; i < size; i++)
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putc('\b');
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}
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#endif /* !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL) */
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inline void ppc4xx_ibm_ddr2_register_dump(void)
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#include <asm/io.h>
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#include <asm/processor.h>
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#include "ecc.h"
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#if defined(CONFIG_PPC4xx_DDR_AUTOCALIBRATION)
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/*
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static inline void ecc_clear_status_reg(void)
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{
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mtsdram(SDRAM_ECCCR, 0xffffffff);
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mtsdram(SDRAM_ECCES, 0xffffffff);
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#if defined(SDRAM_R0BAS)
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mtdcr(SDRAM_ERRSTATLL, 0xffffffff);
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#endif
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* ecc error, then don't count
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* this as a passing value
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*/
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mfsdram(SDRAM_ECCCR, ecc_status);
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mfsdram(SDRAM_ECCES, ecc_status);
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if (ecc_status != 0x00000000) {
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/* clear on error */
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ecc_clear_status_reg();
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179
cpu/ppc4xx/ecc.c
179
cpu/ppc4xx/ecc.c
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@ -2,7 +2,7 @@
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* Copyright (c) 2008 Nuovation System Designs, LLC
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* Grant Erickson <gerickson@nuovations.com>
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*
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* (C) Copyright 2005-2007
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* (C) Copyright 2005-2009
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* Stefan Roese, DENX Software Engineering, sr@denx.de.
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*
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* (C) Copyright 2002
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@ -42,81 +42,144 @@
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#include <ppc_defs.h>
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#include <asm/processor.h>
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#include <asm/io.h>
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#include <asm/mmu.h>
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#include <asm/cache.h>
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#include "ecc.h"
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#if defined(CONFIG_SDRAM_PPC4xx_IBM_DDR) || \
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defined(CONFIG_SDRAM_PPC4xx_IBM_DDR2)
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#if defined(CONFIG_DDR_ECC) || defined(CONFIG_SDRAM_ECC)
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#if defined(CONFIG_405EX)
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/*
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* void ecc_init()
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*
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* Description:
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* This routine initializes a range of DRAM ECC memory with known
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* data and enables ECC checking.
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*
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* TO DO:
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* - Improve performance by utilizing cache.
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* - Further generalize to make usable by other 4xx variants (e.g.
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* 440EPx, et al).
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*
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* Input(s):
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* start - A pointer to the start of memory covered by ECC requiring
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* initialization.
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* size - The size, in bytes, of the memory covered by ECC requiring
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* initialization.
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*
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* Output(s):
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* start - A pointer to the start of memory covered by ECC with
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* CONFIG_SYS_ECC_PATTERN written to all locations and ECC data
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* primed.
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*
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* Returns:
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* N/A
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* Currently only 405EX uses 16bit data bus width as an alternative
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* option to 32bit data width (SDRAM0_MCOPT1_WDTH)
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*/
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#define SDRAM_DATA_ALT_WIDTH 2
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#else
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#define SDRAM_DATA_ALT_WIDTH 8
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#endif
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static void wait_ddr_idle(void)
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{
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u32 val;
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do {
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mfsdram(SDRAM_MCSTAT, val);
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} while ((val & SDRAM_MCSTAT_IDLE_MASK) == SDRAM_MCSTAT_IDLE_NOT);
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}
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static void program_ecc_addr(unsigned long start_address,
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unsigned long num_bytes,
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unsigned long tlb_word2_i_value)
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{
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unsigned long current_address;
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unsigned long end_address;
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unsigned long address_increment;
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unsigned long mcopt1;
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char str[] = "ECC generation -";
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char slash[] = "\\|/-\\|/-";
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int loop = 0;
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int loopi = 0;
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current_address = start_address;
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mfsdram(SDRAM_MCOPT1, mcopt1);
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if ((mcopt1 & SDRAM_MCOPT1_MCHK_MASK) != SDRAM_MCOPT1_MCHK_NON) {
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mtsdram(SDRAM_MCOPT1,
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(mcopt1 & ~SDRAM_MCOPT1_MCHK_MASK) | SDRAM_MCOPT1_MCHK_GEN);
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sync();
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eieio();
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wait_ddr_idle();
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puts(str);
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#ifdef CONFIG_440
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if (tlb_word2_i_value == TLB_WORD2_I_ENABLE) {
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#endif
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/* ECC bit set method for non-cached memory */
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if ((mcopt1 & SDRAM_MCOPT1_DMWD_MASK) == SDRAM_MCOPT1_DMWD_32)
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address_increment = 4;
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else
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address_increment = SDRAM_DATA_ALT_WIDTH;
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end_address = current_address + num_bytes;
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while (current_address < end_address) {
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*((unsigned long *)current_address) = 0;
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current_address += address_increment;
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if ((loop++ % (2 << 20)) == 0) {
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putc('\b');
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putc(slash[loopi++ % 8]);
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}
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}
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#ifdef CONFIG_440
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} else {
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/* ECC bit set method for cached memory */
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dcbz_area(start_address, num_bytes);
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/* Write modified dcache lines back to memory */
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clean_dcache_range(start_address, start_address + num_bytes);
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}
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#endif /* CONFIG_440 */
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blank_string(strlen(str));
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sync();
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eieio();
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wait_ddr_idle();
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/* clear ECC error repoting registers */
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mtsdram(SDRAM_ECCES, 0xffffffff);
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mtdcr(0x4c, 0xffffffff);
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mtsdram(SDRAM_MCOPT1,
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(mcopt1 & ~SDRAM_MCOPT1_MCHK_MASK) | SDRAM_MCOPT1_MCHK_CHK_REP);
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sync();
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eieio();
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wait_ddr_idle();
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}
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}
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#if defined(CONFIG_SDRAM_PPC4xx_IBM_DDR)
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void ecc_init(unsigned long * const start, unsigned long size)
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{
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const unsigned long pattern = CONFIG_SYS_ECC_PATTERN;
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unsigned long * const end = (unsigned long * const)((long)start + size);
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unsigned long * current = start;
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unsigned long mcopt1;
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long increment;
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if (start >= end)
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return;
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mfsdram(SDRAM_ECC_CFG, mcopt1);
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/* Enable ECC generation without checking or reporting */
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mtsdram(SDRAM_ECC_CFG, ((mcopt1 & ~SDRAM_ECC_CFG_MCHK_MASK) |
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SDRAM_ECC_CFG_MCHK_GEN));
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increment = sizeof(u32);
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#if defined(CONFIG_440)
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/*
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||||
* Look at the geometry of SDRAM (data width) to determine whether we
|
||||
* can skip words when writing.
|
||||
* Init ECC with cache disabled (on PPC's with IBM DDR
|
||||
* controller (non DDR2), not tested with cache enabled yet
|
||||
*/
|
||||
program_ecc_addr((u32)start, size, TLB_WORD2_I_ENABLE);
|
||||
}
|
||||
#endif
|
||||
|
||||
if ((mcopt1 & SDRAM_ECC_CFG_DMWD_MASK) != SDRAM_ECC_CFG_DMWD_32)
|
||||
increment = sizeof(u64);
|
||||
#endif /* defined(CONFIG_440) */
|
||||
#if defined(CONFIG_SDRAM_PPC4xx_IBM_DDR2)
|
||||
void do_program_ecc(unsigned long tlb_word2_i_value)
|
||||
{
|
||||
unsigned long mcopt1;
|
||||
unsigned long mcopt2;
|
||||
unsigned long mcstat;
|
||||
phys_size_t memsize = sdram_memsize();
|
||||
|
||||
while (current < end) {
|
||||
*current = pattern;
|
||||
current = (unsigned long *)((long)current + increment);
|
||||
if (memsize > CONFIG_MAX_MEM_MAPPED) {
|
||||
printf("\nWarning: Can't enable ECC on systems with more than 2GB of SDRAM!\n");
|
||||
return;
|
||||
}
|
||||
|
||||
/* Wait until the writes are finished. */
|
||||
mfsdram(SDRAM_MCOPT1, mcopt1);
|
||||
mfsdram(SDRAM_MCOPT2, mcopt2);
|
||||
|
||||
sync();
|
||||
if ((mcopt1 & SDRAM_MCOPT1_MCHK_MASK) != SDRAM_MCOPT1_MCHK_NON) {
|
||||
/* DDR controller must be enabled and not in self-refresh. */
|
||||
mfsdram(SDRAM_MCSTAT, mcstat);
|
||||
if (((mcopt2 & SDRAM_MCOPT2_DCEN_MASK) == SDRAM_MCOPT2_DCEN_ENABLE)
|
||||
&& ((mcopt2 & SDRAM_MCOPT2_SREN_MASK) == SDRAM_MCOPT2_SREN_EXIT)
|
||||
&& ((mcstat & (SDRAM_MCSTAT_MIC_MASK | SDRAM_MCSTAT_SRMS_MASK))
|
||||
== (SDRAM_MCSTAT_MIC_COMP | SDRAM_MCSTAT_SRMS_NOT_SF))) {
|
||||
|
||||
/* Enable ECC generation with checking and no reporting */
|
||||
|
||||
mtsdram(SDRAM_ECC_CFG, ((mcopt1 & ~SDRAM_ECC_CFG_MCHK_MASK) |
|
||||
SDRAM_ECC_CFG_MCHK_CHK));
|
||||
program_ecc_addr(0, memsize, tlb_word2_i_value);
|
||||
}
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* defined(CONFIG_DDR_ECC) || defined(CONFIG_SDRAM_ECC) */
|
||||
#endif /* defined(CONFIG_SDRAM_PPC4xx_IBM_DDR)... */
|
||||
|
|
|
@ -2,7 +2,7 @@
|
|||
* Copyright (c) 2008 Nuovation System Designs, LLC
|
||||
* Grant Erickson <gerickson@nuovations.com>
|
||||
*
|
||||
* Copyright (c) 2007 DENX Software Engineering, GmbH
|
||||
* Copyright (c) 2007-2009 DENX Software Engineering, GmbH
|
||||
* Stefan Roese <sr@denx.de>
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
|
@ -25,18 +25,13 @@
|
|||
*
|
||||
* Description:
|
||||
* This file implements ECC initialization for PowerPC processors
|
||||
* using the SDRAM DDR2 controller, including the 405EX(r),
|
||||
* 440SP(E), 460EX and 460GT.
|
||||
* using the IBM SDRAM DDR1 & DDR2 controller.
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef _ECC_H_
|
||||
#define _ECC_H_
|
||||
|
||||
#if !defined(CONFIG_SYS_ECC_PATTERN)
|
||||
#define CONFIG_SYS_ECC_PATTERN 0x00000000
|
||||
#endif /* !defined(CONFIG_SYS_ECC_PATTERN) */
|
||||
|
||||
/*
|
||||
* Since the IBM DDR controller used on 440GP/GX/EP/GR is not register
|
||||
* compatible to the IBM DDR/2 controller used on 405EX/440SP/SPe/460EX/GT
|
||||
|
@ -46,24 +41,35 @@
|
|||
|
||||
/* For 440GP/GX/EP/GR */
|
||||
#if defined(CONFIG_SDRAM_PPC4xx_IBM_DDR)
|
||||
#define SDRAM_ECC_CFG SDRAM_CFG0
|
||||
#define SDRAM_ECC_CFG_MCHK_MASK SDRAM_CFG0_MCHK_MASK
|
||||
#define SDRAM_ECC_CFG_MCHK_GEN SDRAM_CFG0_MCHK_GEN
|
||||
#define SDRAM_ECC_CFG_MCHK_CHK SDRAM_CFG0_MCHK_CHK
|
||||
#define SDRAM_ECC_CFG_DMWD_MASK SDRAM_CFG0_DMWD_MASK
|
||||
#define SDRAM_ECC_CFG_DMWD_32 SDRAM_CFG0_DMWD_32
|
||||
#define SDRAM_MCOPT1 SDRAM_CFG0
|
||||
#define SDRAM_MCOPT1_MCHK_MASK SDRAM_CFG0_MCHK_MASK
|
||||
#define SDRAM_MCOPT1_MCHK_NON SDRAM_CFG0_MCHK_NON
|
||||
#define SDRAM_MCOPT1_MCHK_GEN SDRAM_CFG0_MCHK_GEN
|
||||
#define SDRAM_MCOPT1_MCHK_CHK SDRAM_CFG0_MCHK_CHK
|
||||
#define SDRAM_MCOPT1_MCHK_CHK_REP SDRAM_CFG0_MCHK_CHK
|
||||
#define SDRAM_MCOPT1_DMWD_MASK SDRAM_CFG0_DMWD_MASK
|
||||
#define SDRAM_MCOPT1_DMWD_32 SDRAM_CFG0_DMWD_32
|
||||
|
||||
#define SDRAM_MCSTAT SDRAM0_MCSTS
|
||||
#define SDRAM_MCSTAT_IDLE_MASK SDRAM_MCSTS_CIS
|
||||
#define SDRAM_MCSTAT_IDLE_NOT SDRAM_MCSTS_IDLE_NOT
|
||||
|
||||
#define SDRAM_ECCES SDRAM0_ECCESR
|
||||
#endif
|
||||
|
||||
/* For 405EX/440SP/SPe/460EX/GT */
|
||||
#if defined(CONFIG_SDRAM_PPC4xx_IBM_DDR2)
|
||||
#define SDRAM_ECC_CFG SDRAM_MCOPT1
|
||||
#define SDRAM_ECC_CFG_MCHK_MASK SDRAM_MCOPT1_MCHK_MASK
|
||||
#define SDRAM_ECC_CFG_MCHK_GEN SDRAM_MCOPT1_MCHK_GEN
|
||||
#define SDRAM_ECC_CFG_MCHK_CHK SDRAM_MCOPT1_MCHK_CHK
|
||||
#define SDRAM_ECC_CFG_DMWD_MASK SDRAM_MCOPT1_DMWD_MASK
|
||||
#define SDRAM_ECC_CFG_DMWD_32 SDRAM_MCOPT1_DMWD_32
|
||||
#endif
|
||||
void ecc_init(unsigned long * const start, unsigned long size);
|
||||
void do_program_ecc(unsigned long tlb_word2_i_value);
|
||||
|
||||
extern void ecc_init(unsigned long * const start, unsigned long size);
|
||||
static void inline blank_string(int size)
|
||||
{
|
||||
int i;
|
||||
|
||||
for (i = 0; i < size; i++)
|
||||
putc('\b');
|
||||
for (i = 0; i < size; i++)
|
||||
putc(' ');
|
||||
for (i = 0; i < size; i++)
|
||||
putc('\b');
|
||||
}
|
||||
|
||||
#endif /* _ECC_H_ */
|
||||
|
|
|
@ -117,6 +117,7 @@
|
|||
#define SDRAM_MCSTS_MRSC 0x80000000
|
||||
#define SDRAM_MCSTS_SRMS 0x40000000
|
||||
#define SDRAM_MCSTS_CIS 0x20000000
|
||||
#define SDRAM_MCSTS_IDLE_NOT 0x00000000 /* Mem contr not idle */
|
||||
|
||||
/*
|
||||
* SDRAM Refresh Timer Register
|
||||
|
@ -416,8 +417,7 @@
|
|||
#define SDRAM_SDTR3 0x87 /* DDR SDRAM timing 3 */
|
||||
#define SDRAM_MMODE 0x88 /* memory mode */
|
||||
#define SDRAM_MEMODE 0x89 /* memory extended mode */
|
||||
#define SDRAM_ECCCR 0x98 /* ECC error status */
|
||||
#define SDRAM_ECCES SDRAM_ECCCR
|
||||
#define SDRAM_ECCES 0x98 /* ECC error status */
|
||||
#define SDRAM_CID 0xA4 /* core ID */
|
||||
#ifndef CONFIG_405EX
|
||||
#define SDRAM_RID 0xA8 /* revision ID */
|
||||
|
@ -1397,7 +1397,6 @@
|
|||
/*
|
||||
* Prototypes
|
||||
*/
|
||||
void inline blank_string(int size);
|
||||
inline void ppc4xx_ibm_ddr2_register_dump(void);
|
||||
u32 mfdcr_any(u32);
|
||||
void mtdcr_any(u32, u32);
|
||||
|
@ -1405,6 +1404,8 @@ u32 ddr_wrdtr(u32);
|
|||
u32 ddr_clktr(u32);
|
||||
void spd_ddr_init_hang(void);
|
||||
u32 DQS_autocalibration(void);
|
||||
phys_size_t sdram_memsize(void);
|
||||
void dcbz_area(u32 start_address, u32 num_bytes);
|
||||
#endif /* __ASSEMBLY__ */
|
||||
|
||||
#endif /* _PPC4xx_SDRAM_H_ */
|
||||
|
|
|
@ -768,10 +768,6 @@
|
|||
|
||||
#define SDR0_SDCS_SDD (0x80000000 >> 31)
|
||||
|
||||
/* SDR0_SDSTP0 Serial Device Strap Register0 */
|
||||
#define SDR0_SDSTP0 0x0020
|
||||
#define SDR0_SDSTP0_PLB2xDV0_DECODE(n) ((((unsigned long)(n)) & 0x07))
|
||||
|
||||
/* CUST0 Customer Configuration Register0 */
|
||||
#define SDR0_CUST0 0x4000
|
||||
#define SDR0_CUST0_MUX_E_N_G_MASK 0xC0000000 /* Mux_Emac_NDFC_GPIO */
|
||||
|
|
Loading…
Add table
Reference in a new issue