Also move lib_$ARCH/config.mk to arch/$ARCH/config.mk
This change is intended to clean up the top-level directory structure
and more closely mimic Linux's directory organization.
Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
Previously, a specific file or directory could be compiled with custom
CFLAGS by adding a Makefile variable such as:
CFLAGS_dlmalloc.o = <custom flags for common/dlmalloc.c>
or
CFLAGS_lib = <custom flags for lib directory>
This method breaks down once multiple files or directories share the
same path. Eg FLAGS_fileA = <custom flags> would incorrectly result in
both dir1/fileA.c and dir2/fileA.c being compiled with <custom flags>.
This change allows finer grained control which we need once we move
lib_$ARCH to arch/$ARCH/lib/ and lib_generic/ to lib/. Without this
change all lib/ directories would share the same custom CFLAGS.
Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
The CPUDIR variable points to the location of a target's CPU directory.
Currently, it is set to cpu/$CPU. However, using $CPUDIR will allow for
more flexibility in the future. It lays the groundwork for reorganizing
U-Boot's directory structure to support a layout such as:
arch/$ARCH/cpu/$CPU/* (architecture with multiple CPU types)
arch/$ARCH/cpu/* (architecture with one CPU type)
Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
* add WATCHDOG_RESET to !tstc() loops
* prevents watchdog timeout, while waiting for input,
if CONFIG_BOOT_RETRY_TIME or CONFIG_SHOW_ACTIVITY defined
Signed-off-by: Jens Scharsig <js_at_ng@scharsoft.de>
Version 4.2.4 of gcc produces the following warnings without this change:
mkimage.c: In function ‘main’:
mkimage.c:204: warning: dereferencing type-punned pointer will break strict-aliasing rules
mkimage.c:222: warning: dereferencing type-punned pointer will break strict-aliasing rules
Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
gcc 3.4.6 previously reported the following error on many MIPS boards
which utilize UBI:
cmd_ubi.c:193: warning: 'vol' might be used uninitialized in this function
The current code is structured such that 'vol' will never be used when
it is NULL anyway, but gcc isn't smart enough to figure this out.
Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
Signed-off-by: Stefan Roese <sr@denx.de>
While debugging one ill behaving USB device I found two bugs in USB
storage probe.
usb_stor_get_info() returns -1 (error), 0 (skip) or 1 (ok). First part
of this patch fixes error case.
Second part fixes usb_inquiry()'s retry counter handling. Original code
had retry = -1 on error case, not retry = 0 as checked in the next line.
Signed-off-by: Kim B. Heino <Kim.Heino@bluegiga.com>
Here's another USB storage patch. Currently U-Boot handles storage
devices #0 - #4 as valid devices, even if there is none connected. This
patch fixes usb_stor_get_dev() to check detected device count instead
of MAX-define.
This is very important for ill behaving devices. usb_dev_desc[] can be
partially initialized if device probe fails.
After fixing get_dev() it was easy to fix "usb part" etc commands.
Previously it outputed "Unknown partition table" five times, now it's
"no USB devices available".
Signed-off-by: Kim B. Heino <Kim.Heino@bluegiga.com>
Add NEC EHCI controller to the list of the supported devices.
Signed-off-by: Sergei Shtylyov <sshtylyov@mvista.com>
drivers/usb/host/ehci-pci.c | 1 +
1 file changed, 1 insertion(+)
Commit b416191a14 (Fix EHCI port reset.) didn't
move the code that checked for successful clearing of the port reset bit from
ehci_submit_root(), relying on wait_ms() call instead. The mentioned code also
erroneously reported port reset state when the reset was already completed.
Signed-off-by: Sergei Shtylyov <sshtylyov@mvista.com>
USB devices on the 2nd port are not detected and I get the following message:
The request port(1) is not configured
That's with default CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS value of 2. 'req->index'
is 1-based, so the comparison in ehci_submit_root() can't be correct.
Signed-off-by: Sergei Shtylyov <sshtylyov@mvista.com>
On little endian machines, EHCI root hub's USB revision is reported as 0.2 --
cpu_to_le16() was missed in the initializer for the 'bcdUSB' descriptor field.
The same should be done for the 'bcdDevice' field.
Signed-off-by: Sergei Shtylyov <sshtylyov@mvista.com>
Fixes this warning:
ati_radeon_fb.c: In function 'radeon_probe':
ati_radeon_fb.c:598: warning: format '%x' expects type 'unsigned int',
but argument 2 has type 'void *'
Signed-off-by: Anatolij Gustschin <agust@denx.de>
Use pci_bus_to_virt() to convert the bus address from the BARs to
virtual address' to eliminate the direct mapping requirement.
Rename variables to better match usage (_phys -> _bus or no-suffix)
This fixes the mpc8572ds CONFIG_PHYS_64BIT mode failure:
"videoboot: Video ROM failed to map!"
Tested on mpc8572ds with and without CONFIG_PHYS_64BIT.
Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com>
Console was being switched to video even if emulator fails and
causing this hang:
Scanning PCI bus 04
04 00 1095 3132 0104 00
PCIE3 on bus 03 - 04
Video: ATI Radeon video card (1002, 5b60) found @(2:0:0)
videoboot: Booting PCI video card bus 2, function 0, device 0
videoboot: Video ROM failed to map!
640x480x8 31kHz 59Hz
radeonfb: FIFO Timeout !
Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com>
Tested-by: Anatolij Gustschin <agust@denx.de>
This patch adds reset_timer() before the flash status check
waiting loop.
Since the timer is basically running asynchronous to the cfi
code, it is possible to call get_timer(0), then only a few
_SYSCLK_ cycles later an interrupt is generated. This causes
timeout even though much less time has elapsed. So the timer
period registers should be reset before get_timer(0) is
called.
There is similar usage in nand_base.c.
Signed-off-by: Thomas Chou <thomas@wytron.com.tw>
Signed-off-by: Stefan Roese <sr@denx.de>
The MPC8536DS_NAND SPL build was failing due to code size increase
introduced by commit:
commit 33f57bd553
Author: Kumar Gala <galak@kernel.crashing.org>
Date: Fri Mar 26 15:14:43 2010 -0500
85xx: Fix enabling of L1 cache parity on secondary cores
We built in some NS16550 functions that we dont need and can get
rid of them via CONFIG_NS16550_MIN_FUNCTIONS.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
The Freescale P2020DS board uses a new type of PIXIS FPGA, called the ngPIXIS.
The ngPIXIS has one distinct new feature: the values of the on-board switches
can be selectively overridden with shadow registers. This feature is used to
boot from a different NOR flash bank, instead of having a register dedicated
for this purpose. Because the ngPIXIS is so different from the previous PIXIS,
a new file is introduced: ngpixis.c.
Also update the P2020DS checkboard() function to use the new macros defined
in the header file.
Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Refactor and document the Freescale PIXIS code, used on most 85xx and 86xx
boards. This makes the code easier to read and more flexible.
Delete pixis.h, because none of the exported functions were actually being
used by any other file. Make all of the functions in pixis.c 'static'.
Remove "#include pixis.h" from every file that has it.
Remove some unnecessary #includes.
Make 'pixis_base' into a macro, so that we don't need to define it in every
function.
Add "while(1);" loops at the end of functions that reset the board, so that
execution doesn't continue while the reset is in progress.
Replace in_8/out_8 calls with clrbits_8, setbits_8, or clrsetbits_8, where
appropriate.
Replace ulong/uint with their spelled-out equivalents. Remove unnecessary
typecasts, changing the types of some variables if necessary.
Add CONFIG_SYS_PIXIS_VCFGEN0_ENABLE and CONFIG_SYS_PIXIS_VBOOT_ENABLE to make
it easier for specific boards to support variations in the PIXIS registers
sets. No current boards appears to need this feature.
Fix the definition of CONFIG_SYS_PIXIS_VBOOT_MASK for the MPC8610 HPCD.
Apparently, "pixis_reset altbank" has never worked on this board.
Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
The HID1[MBDD] bit is new on rev5.0 or greater cores and will optimize
the performance of mbar/eieio instructions.
Signed-off-by: Sandeep Gopalpet <sandeep.kumar@freescale.com>
There are various locations that we have chip specific info:
* Makefile for which ddr code to build
* Added P1012/P1013/P1021/P1022 to cpu_type_list and SVR list
* Added number of LAWs for P1012/P1013/P1021/P1022
* Set CONFIG_MAX_CPUS to 2 for P1021/P1022
* PCI port config
Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
Signed-off-by: Srikanth Srinivasan <srikanth.srinivasan@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
If the PCI controller wasn't configured or enabled delete from the
device tree (include its alias).
For the case that we didn't even configure u-boot with knowledge of
the controller we can use the fact that the pci_controller pointer
is NULL to delete the node in the device tree. We determine that
a controller was not setup (because of HW config) based on the fact
that cfg_addr wasn't setup.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Now that the linker script is preprocessed with -ansi, there is no need to
manually undef the bfin define.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
If someone uses the FDPIC toolchain to compile U-Boot, make sure the
linker knows to use the normal ABI target rather than the FDPIC one.
This wasn't needed with older toolchains, but when we fixed the linker
such that the default target changed based on tuple, this broke.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Switch to the SMC911X driver by default now, and fix LDR env settings.
Signed-off-by: Harald Krapfenbauer <Harald.Krapfenbauer@bluetechnix.at>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
The strictest alignment on Blackfin systems is 32bits (since that is the
largest load instruction), so don't force 256byte alignment here.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
The reloc_off member no longer exists, so drop it. Also change this
function so that it is always compiled and prevents latent issues like
this in the future.
Reported-by: Peter Meerwald <pmeerw@pmeerw.net>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Add a helper function that given an alias will delete both the node
the alias points to and the alias itself
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Acked-by: Gerald Van Baren <vanbaren@cideas.com>
For 64B cacheline SoC, set the fixed 8-beat burst len,
for 32B cacheline SoC, set the On-The-Fly as default.
Signed-off-by: Dave Liu <daveliu@freescale.com>
Read-to-read/Write-to-write turnaround for same chip select
of DDR3 memory, BL/2+2 cycles is enough for them at BC4 and
OTF case, BL/2 cycles is enough for fixed BL8.
Cutting down the turnaround from BL/2+4 to BL/2+2 or BL/2
will improve the memory performance.
Signed-off-by: Dave Liu <daveliu@freescale.com>
