mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-10 15:14:43 +00:00
Blackfin: sync ptrace headers with linux
Scrub a lot of dead cruft in the process. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
This commit is contained in:
Mike Frysinger
parent
6a0be8f8fe
commit
dd97022cbe
2 changed files with 129 additions and 236 deletions
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@ -1,31 +1,11 @@
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/*
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* U-boot - ptrace.h
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* Copyright 2004-2008 Analog Devices Inc.
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*
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* Copyright (c) 2005-2007 Analog Devices Inc.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
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* MA 02110-1301 USA
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* Licensed under the GPL-2 or later.
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*/
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#ifndef _BLACKFIN_PTRACE_H
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#define _BLACKFIN_PTRACE_H
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#define NEW_PT_REGS
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#ifndef _BFIN_PTRACE_H
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#define _BFIN_PTRACE_H
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/*
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* GCC defines register number like this:
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@ -35,128 +15,30 @@
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* 16 - 31 dsp registers I/B/L0 -- I/B/L3 & M0--M3
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* 32 - 33 A registers A0 & A1
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* 34 - status register
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* -----------------------------
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*
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* We follows above, except:
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* 32-33 --- Low 32-bit of A0&1
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* 34-35 --- High 8-bit of A0&1
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*/
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#if defined(NEW_PT_REGS)
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#define PT_IPEND 0
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#define PT_SYSCFG (PT_IPEND+4)
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#define PT_SEQSTAT (PT_SYSCFG+4)
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#define PT_RETE (PT_SEQSTAT+4)
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#define PT_RETN (PT_RETE+4)
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#define PT_RETX (PT_RETN+4)
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#define PT_RETI (PT_RETX+4)
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#define PT_PC PT_RETI
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#define PT_RETS (PT_RETI+4)
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#define PT_RESERVED (PT_RETS+4)
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#define PT_ASTAT (PT_RESERVED+4)
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#define PT_LB1 (PT_ASTAT+4)
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#define PT_LB0 (PT_LB1+4)
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#define PT_LT1 (PT_LB0+4)
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#define PT_LT0 (PT_LT1+4)
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#define PT_LC1 (PT_LT0+4)
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#define PT_LC0 (PT_LC1+4)
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#define PT_A1W (PT_LC0+4)
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#define PT_A1X (PT_A1W+4)
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#define PT_A0W (PT_A1X+4)
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#define PT_A0X (PT_A0W+4)
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#define PT_B3 (PT_A0X+4)
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#define PT_B2 (PT_B3+4)
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#define PT_B1 (PT_B2+4)
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#define PT_B0 (PT_B1+4)
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#define PT_L3 (PT_B0+4)
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#define PT_L2 (PT_L3+4)
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#define PT_L1 (PT_L2+4)
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#define PT_L0 (PT_L1+4)
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#define PT_M3 (PT_L0+4)
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#define PT_M2 (PT_M3+4)
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#define PT_M1 (PT_M2+4)
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#define PT_M0 (PT_M1+4)
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#define PT_I3 (PT_M0+4)
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#define PT_I2 (PT_I3+4)
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#define PT_I1 (PT_I2+4)
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#define PT_I0 (PT_I1+4)
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#define PT_USP (PT_I0+4)
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#define PT_FP (PT_USP+4)
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#define PT_P5 (PT_FP+4)
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#define PT_P4 (PT_P5+4)
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#define PT_P3 (PT_P4+4)
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#define PT_P2 (PT_P3+4)
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#define PT_P1 (PT_P2+4)
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#define PT_P0 (PT_P1+4)
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#define PT_R7 (PT_P0+4)
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#define PT_R6 (PT_R7+4)
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#define PT_R5 (PT_R6+4)
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#define PT_R4 (PT_R5+4)
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#define PT_R3 (PT_R4+4)
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#define PT_R2 (PT_R3+4)
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#define PT_R1 (PT_R2+4)
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#define PT_R0 (PT_R1+4)
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#define PT_ORIG_R0 (PT_R0+4)
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#define PT_SR PT_SEQSTAT
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#else
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/*
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* Here utilize blackfin : dpregs = [pregs + imm16s4]
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* [pregs + imm16s4] = dpregs
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* to access defferent saved reg in stack
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*/
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#define PT_R3 0
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#define PT_R4 4
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#define PT_R2 8
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#define PT_R1 12
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#define PT_P5 16
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#define PT_P4 20
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#define PT_P3 24
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#define PT_P2 28
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#define PT_P1 32
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#define PT_P0 36
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#define PT_R7 40
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#define PT_R6 44
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#define PT_R5 48
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#define PT_PC 52
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#define PT_SEQSTAT 56 /* so-called SR reg */
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#define PT_SR PT_SEQSTAT
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#define PT_ASTAT 60
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#define PT_RETS 64
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#define PT_A1w 68
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#define PT_A0w 72
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#define PT_A1x 76
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#define PT_A0x 80
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#define PT_ORIG_R0 84
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#define PT_R0 88
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#define PT_USP 92
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#define PT_FP 96
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#define PT_SP 100
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/* Added by HuTao, May26 2003 3:18PM */
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#define PT_IPEND 100
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/* Add SYSCFG register for single stepping support */
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#define PT_SYSCFG 104
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#endif
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#ifndef __ASSEMBLY__
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#if defined(NEW_PT_REGS)
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struct task_struct;
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/* this struct defines the way the registers are stored on the
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* stack during a system call.
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*/
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stack during a system call. */
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struct pt_regs {
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long orig_pc;
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long ipend;
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long syscfg;
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long seqstat;
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long rete;
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long retn;
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long retx;
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long pc;
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long pc; /* PC == RETI */
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long rets;
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long reserved;
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long reserved; /* Used as scratch during system calls */
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long astat;
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long lb1;
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long lb0;
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@ -201,69 +83,116 @@ struct pt_regs {
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long r1;
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long r0;
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long orig_r0;
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};
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#else
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/* now we don't know what regs the system call will use */
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struct pt_regs {
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long r3;
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long r4;
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long r2;
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long r1;
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long p5;
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long p4;
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long p3;
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long p2;
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long p1;
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long p0;
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long r7;
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long r6;
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long r5;
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unsigned long pc;
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unsigned long seqstat;
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unsigned long astat;
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unsigned long rets;
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long a1w;
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long a0w;
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long a1x;
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long a0x;
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long orig_r0;
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long r0;
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long usp;
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long fp;
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/*
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* Added for supervisor/user mode switch.
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*
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* HuTao May26 03 3:23PM
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*/
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long ipend;
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long orig_p0;
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long syscfg;
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};
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#endif
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/* Arbitrarily choose the same ptrace numbers as used by the Sparc code. */
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#define PTRACE_GETREGS 12
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#define PTRACE_SETREGS 13 /* ptrace signal */
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#define PTRACE_GETREGS 12
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#define PTRACE_SETREGS 13 /* ptrace signal */
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#define PTRACE_GETFDPIC 31 /* get the ELF fdpic loadmap address */
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#define PTRACE_GETFDPIC_EXEC 0 /* [addr] request the executable loadmap */
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#define PTRACE_GETFDPIC_INTERP 1 /* [addr] request the interpreter loadmap */
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#define PS_S (0x0002)
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#ifdef __KERNEL__
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#ifndef PS_S
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#define PS_S (0x0c00)
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/* Bit 11:10 of SEQSTAT defines user/supervisor/debug mode
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* 00: user
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* 01: supervisor
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* 1x: debug
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*/
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#define PS_M (0x1000) /* I am not sure why this is required here Akbar */
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#endif
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#define user_mode(regs) (!((regs)->seqstat & PS_S))
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#define instruction_pointer(regs) ((regs)->pc)
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/* user_mode returns true if only one bit is set in IPEND, other than the
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master interrupt enable. */
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#define user_mode(regs) (!(((regs)->ipend & ~0x10) & (((regs)->ipend & ~0x10) - 1)))
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#define instruction_pointer(regs) ((regs)->pc)
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#define user_stack_pointer(regs) ((regs)->usp)
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#define profile_pc(regs) instruction_pointer(regs)
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extern void show_regs(struct pt_regs *);
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#endif
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#endif
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#endif
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#define arch_has_single_step() (1)
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extern void user_enable_single_step(struct task_struct *);
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/* see arch/blackfin/kernel/ptrace.c about this redirect */
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#define user_disable_single_step(child) ptrace_disable(child)
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/*
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* Get the address of the live pt_regs for the specified task.
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* These are saved onto the top kernel stack when the process
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* is not running.
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*
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* Note: if a user thread is execve'd from kernel space, the
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* kernel stack will not be empty on entry to the kernel, so
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* ptracing these tasks will fail.
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*/
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#define task_pt_regs(task) \
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(struct pt_regs *) \
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((unsigned long)task_stack_page(task) + \
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(THREAD_SIZE - sizeof(struct pt_regs)))
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#endif /* __KERNEL__ */
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#endif /* __ASSEMBLY__ */
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/*
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* Offsets used by 'ptrace' system call interface.
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*/
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#define PT_R0 204
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#define PT_R1 200
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#define PT_R2 196
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#define PT_R3 192
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#define PT_R4 188
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#define PT_R5 184
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#define PT_R6 180
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#define PT_R7 176
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#define PT_P0 172
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#define PT_P1 168
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#define PT_P2 164
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#define PT_P3 160
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#define PT_P4 156
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#define PT_P5 152
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#define PT_FP 148
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#define PT_USP 144
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#define PT_I0 140
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#define PT_I1 136
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#define PT_I2 132
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#define PT_I3 128
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#define PT_M0 124
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#define PT_M1 120
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#define PT_M2 116
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#define PT_M3 112
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#define PT_L0 108
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#define PT_L1 104
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#define PT_L2 100
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#define PT_L3 96
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#define PT_B0 92
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#define PT_B1 88
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#define PT_B2 84
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#define PT_B3 80
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#define PT_A0X 76
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#define PT_A0W 72
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#define PT_A1X 68
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#define PT_A1W 64
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#define PT_LC0 60
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#define PT_LC1 56
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#define PT_LT0 52
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#define PT_LT1 48
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#define PT_LB0 44
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#define PT_LB1 40
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#define PT_ASTAT 36
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#define PT_RESERVED 32
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#define PT_RETS 28
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#define PT_PC 24
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#define PT_RETX 20
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#define PT_RETN 16
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#define PT_RETE 12
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#define PT_SEQSTAT 8
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#define PT_IPEND 4
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#define PT_ORIG_R0 208
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#define PT_ORIG_P0 212
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#define PT_SYSCFG 216
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#define PT_TEXT_ADDR 220
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#define PT_TEXT_END_ADDR 224
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#define PT_DATA_ADDR 228
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#define PT_FDPIC_EXEC 232
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#define PT_FDPIC_INTERP 236
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#endif /* _BFIN_PTRACE_H */
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@ -1,42 +1,14 @@
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/*
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* U-boot - traps.h
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* Copyright 2004-2009 Analog Devices Inc.
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* 2001 Lineo, Inc
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* Tony Kou
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* 1993 Hamish Macdonald
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*
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* Copyright (c) 2005-2007 Analog Devices Inc.
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*
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* This file is based on
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* linux/include/asm/traps.h
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* Copyright (C) 1993 Hamish Macdonald
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* Lineo, Inc Jul 2001 Tony Kou
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
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* MA 02110-1301 USA
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* Licensed under the GPL-2
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*/
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/*
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*/
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#ifndef _BLACKFIN_TRAPS_H
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#define _BLACKFIN_TRAPS_H
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#ifndef __ASSEMBLY__
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typedef void (*e_vector) (void);
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extern e_vector vectors[];
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#endif
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#ifndef _BFIN_TRAPS_H
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#define _BFIN_TRAPS_H
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#define VEC_SYS (0)
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#define VEC_EXCPT01 (1)
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@ -64,23 +36,15 @@ extern e_vector vectors[];
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#define VEC_CPLB_M (38)
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#define VEC_CPLB_MHIT (39)
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#define VEC_WATCH (40)
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#define VEC_ISTRU_VL (41)
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#define VEC_ISTRU_VL (41) /*ADSP-BF535 only (MH) */
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#define VEC_MISALI_I (42)
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#define VEC_CPLB_I_VL (43)
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#define VEC_CPLB_I_M (44)
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#define VEC_CPLB_I_MHIT (45)
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#define VEC_ILL_RES (46) /* including unvalid supervisor mode insn */
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/* The hardware reserves (63) for future use - we use it to tell our
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* normal exception handling code we have a hardware error
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*/
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#define VEC_HWERR (63)
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#define VECOFF(vec) ((vec)<<2)
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#ifndef __ASSEMBLY__
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/* Status register bits */
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#define PS_T (0x8000)
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#define PS_S (0x0c00) /* Supervisor mode = 0b01 */
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#define PS_D (0x0c00) /* Debug mode = 0b1x */
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#define PS_M (0x1000)
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#define PS_C (0x0001)
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#endif
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#endif
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#endif /* _BFIN_TRAPS_H */
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