Commit graph

88193 commits

Author SHA1 Message Date
Marek Vasut
c9678850bd ARM: dts: stm32: Switch DWMAC RMII clock to MCO2 on DHCOM
The DHCOM SoM has two options for supplying ETHRX clock to the DWMAC
block and PHY. Either (1) ETHCK_K generates 50 MHz clock on ETH_CLK
pad for the PHY and the same 50 MHz clock are fed back to ETHRX via
internal eth_clk_fb clock connection OR (2) ETH_CLK is not used at
all, MCO2 generates 50 MHz clock on MCO2 output pad for the PHY and
the same MCO2 clock are fed back into ETHRX via ETH_RX_CLK input pad
using external pad-to-pad connection.

Option (1) has two downsides. ETHCK_K is supplied directly from either
PLL3_Q or PLL4_P, hence the PLL output is limited to exactly 50 MHz and
since the same PLL output is also used to supply SDMMC blocks, the
performance of SD and eMMC access is affected. The second downside is
that using this option, the EMI of the SoM is higher.

Option (2) solves both of those problems, so implement it here. In this
case, the PLL4_P is no longer limited and can be operated faster, at
100 MHz, which improves SDMMC performance (read performance is improved
from ~41 MiB/s to ~57 MiB/s with dd if=/dev/mmcblk1 of=/dev/null bs=64M
count=1). The EMI interference also decreases.

Ported from Linux kernel commit
73ab99aad50cd ("ARM: dts: stm32: Switch DWMAC RMII clock to MCO2 on DHCOM")

Signed-off-by: Marek Vasut <marex@denx.de>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2023-08-16 15:37:14 +02:00
Patrick Delaunay
284b08fb51 board: stm32mp1: add splash screen with stmicroelectronics logo
Display the STMicroelectronics logo with features VIDEO_LOGO and
SPLASH_SCREEN on STMicroelectronics boards.

With CONFIG_SYS_VENDOR = "st", the logo st.bmp is selected, loaded at the
address indicated by splashimage and centered with "splashpos=m,m".

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2023-08-16 15:35:55 +02:00
Patrick Delaunay
61ad1a527a ARM: dts: stm32mp: alignment with v6.4
Device tree alignment with Linux kernel v6.4.

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2023-08-16 15:30:49 +02:00
Marek Vasut
b58ab56d14 ARM: stm32: Inhibit PDDS because CSTBYDIS is set
The PWR_MPUCR CSTBYDIS bit is set, therefore the CA cores can never
enter CStandby state and would always end up in CStop state. Clear
the PDDS bit, which indicates the CA cores can enter CStandby state
as it makes little sense to keep it set with CSTBYDIS also set.

This does however fix a problem too. When both PWR_MPUCR and PWR_MCUCR
PDDS bits are set, then the chip enters CStandby state even though the
PWR_MCUCR CSTBYDIS is set. Clearing the PWR_MPUCR PDDS prevents that
from happening.

Signed-off-by: Marek Vasut <marex@denx.de>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2023-08-16 15:29:47 +02:00
Dario Binacchi
fc7bd99f6d ARM: dts: stm32: fix display pinmux for stm32f746-disco
As reported by the datasheet (DocID027590 Rev 4) for PG12:
- AF9  -> LCD_B4
- AF14 -> LCD_B1

So replace AF14 with AF9 for PG12 in the dts.

Fixes: fe63d3cfb7 ("ARM: dts: stm32: Sync DT with v4.20 kernel for stm32f7")
Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2023-08-16 15:27:45 +02:00
Patrick Delaunay
141e232dbd clk: stm32mp1: remove error for disabled clock in stm32mp1_clk_get_parent
To disabled a clock in clock tree initialization for a mux of STM32MP15,
the selected clock source index is set with the latest possible index for
the number of bit used. Today this valid configuration cause a error
in U-Boot messages, for example with CLK_ETH_DISABLED, when this clock
is not needed for the used ETH PHY without crystal:

   no parents defined for clk id 123

This patch change the level of this message to avoid this trace for
valid clock tree.

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2023-08-16 15:23:09 +02:00
Marek Vasut
b3d97f8ce3 ARM: stm32: Power cycle Buck3 in reset on DHSOM
In case the DHSOM is in suspend state and either reset button is pushed
or IWDG2 triggers a watchdog reset, then DRAM initialization could fail
as follows:

  "
  RAM: DDR3L 32bits 2x4Gb 533MHz
  DDR invalid size : 0x4, expected 0x40000000
  DRAM init failed: -22
  ### ERROR ### Please RESET the board ###
  "

Avoid this failure by not keeping any Buck regulators enabled during reset,
let the SoC and DRAMs power cycle fully. Since the change which keeps Buck3
VDD enabled during reset is ST specific, move this addition to ST specific
SPL board initialization so that it wouldn't affect the DHSOM .

Signed-off-by: Marek Vasut <marex@denx.de>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2023-08-16 15:19:57 +02:00
Tom Rini
9b54b0e37b Pull request for efi-2023-10-rc3
Documentation:
 
 * Correct description of board_get_usable_ram_top
 * Add partition API to HTML documentation
 * Describe  lmb_is_reserved
 * doc/sphinx/requirements.txt: Bump certifi up
 
 UEFI:
 
 * Fix  efi_add_known_memory
 * Make distro_efi_boot() static
 
 Other:
 
 * Correct return type board_get_usable_ram_top
 -----BEGIN PGP SIGNATURE-----
 
 iQIzBAABCAAdFiEEbcT5xx8ppvoGt20zxIHbvCwFGsQFAmTbqCcACgkQxIHbvCwF
 GsSLBw/9FysiJXRu2xzT/jX8a6vzpx4Z3xf+6CVF8Ndn771Ii1AI492e3hkJnbPq
 ifS9DOUFVh9vjRgeJqXVAjplZuHPxTqXH5PScQF6axuupzqgkOhCHeV3Hyu2FLAX
 MevX44V9pVFIZRrzaSVAGJTtshLnHua3YoAF12lPjwjA/G11+SP761coINueqjL9
 +98cpVDWzv4z0mJUsg9Tn0+cNsBAbObk365JboSGaZ9hc4fU5cgM2/iGrEjdcO8+
 bOKMiW/iUDLhBe3u0zRRqD4zK4HRNP491goXHWxer0+uQVDuzKyhgg2Vqa+9J1pv
 Ej40BxVhU8LUdmd0E6DLWrtYW/YTvXtznhM32JEzRjoJfI4KFlO7tIweJVKFfhmu
 Vo2pK790irQfLopmyJZjNMau+bThZ+xMeZkJfajEQAls88t/d6x5yJNMjX547rda
 YW0cV1XkoQ42WXTJZpZCLgH5H47bLG+1Bg9hKT/fRZLCG0PROXrA5Nr0i3Qtbq7b
 e0ELBXQdz3kdb8s4ISk2lustM4JI5dJT2jwqLYNSI5k25Bx/9dedubIOfJb/FPcH
 Frr3s/ThA8ww6eSyudL61riU2kSqFbggHZTNVHIdh5RVS9LVWjGtKOYlD6xAtIvE
 uX0n9XabNT4HwxdlLyelz1vWSMo15N5zoHP0q/DqXK5fe+WmwOs=
 =UkDs
 -----END PGP SIGNATURE-----

Merge tag 'efi-2023-10-rc3' of https://source.denx.de/u-boot/custodians/u-boot-efi

Pull request for efi-2023-10-rc3

Documentation:

* Correct description of board_get_usable_ram_top
* Add partition API to HTML documentation
* Describe  lmb_is_reserved
* doc/sphinx/requirements.txt: Bump certifi up

UEFI:

* Fix  efi_add_known_memory
* Make distro_efi_boot() static

Other:

* Correct return type board_get_usable_ram_top
2023-08-15 13:08:17 -04:00
Heinrich Schuchardt
d768dd8855 common: return type board_get_usable_ram_top
board_get_usable_ram_top() returns a physical address that is stored in
gd->ram_top. The return type of the function should be phys_addr_t like the
current type of gd->ram_top.

Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
2023-08-15 18:21:17 +02:00
Heinrich Schuchardt
b571b3acda efi_loader: fix efi_add_known_memory()
In efi_add_known_memory() we currently call board_get_usable_ram_top() with
an incorrect value 0 of parameter total_size. This leads to an incorrect
value for ram_top depending on the code in board_get_usable_ram_top().

Use the value of gd->ram_top instead which is set before relocation by
calling board_get_usable_ram_top().

Fixes: 7b78d6438a ("efi_loader: Reserve unaccessible memory")
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
2023-08-15 18:21:17 +02:00
Bin Meng
6072703dc9 bootmeth: efi: Make distro_efi_boot() static
As it is only called in bootmeth_efi.c

Signed-off-by: Bin Meng <bmeng@tinylab.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
2023-08-15 18:21:17 +02:00
Heinrich Schuchardt
5aae021c30 doc: add partition API to HTML documentation
* Convert comments in part.h to Sphinx style.
* Create documentation page for the partition API.
* Add the partition API page to the API index page.

Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2023-08-15 18:21:17 +02:00
Heinrich Schuchardt
289bd72ea4 doc: description of board_get_usable_ram_top()
Improve the description of function board_get_usable_ram_top().

Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2023-08-15 18:21:17 +02:00
Heinrich Schuchardt
78246baa8d lmb: description lmb_is_reserved, lmb_is_reserved_flags
* provide a description for function lmb_is_reserved()
* improve the description of funciton lmb_is_reserved_flags()

Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
2023-08-15 18:21:17 +02:00
Tom Rini
f26c54ddde doc/sphinx/requirements.txt: Bump certifi up
Upgrade certifi to the latest version, to remove e-Tugra from the root
store.

Link: https://groups.google.com/a/mozilla.org/g/dev-security-policy/c/C-HrP1SEq1A?pli=1
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
2023-08-15 18:21:17 +02:00
Tom Rini
f0efecd27d Merge tag 'ubi-updates-for-v2023.10-rc3' of https://source.denx.de/u-boot/custodians/u-boot-ubi
ubi changes for v2023.10-rc3

Fix:
- Fix 'ubi list' command arguments parsing
  from Dmitry
2023-08-15 10:44:32 -04:00
Tom Rini
ae9de10d5f Merge tag 'i2c-updates-for-v2023.10-rc3' of https://source.denx.de/u-boot/custodians/u-boot-i2c
i2c updates for v2023.10-rc3

Bugfixes:
- mvtwsi driver fix stuck "bus error" state
  from Sam
2023-08-15 10:44:20 -04:00
Dmitry Dunaev
34031e9cce cmd: ubi: Fix 'ubi list' command arguments parsing
This fixes allowed argc variable value for arguments parsing

Fixes: 6de1daf64b ("cmd: ubi: Add 'ubi list' command")
Signed-off-by: Dmitry Dunaev <dunaev@tecon.ru>
2023-08-15 07:32:13 +02:00
Sam Edwards
250454c59b i2c: mvtwsi: reset controller if stuck in "bus error" state
The MVTWSI controller can act either as a master or slave device. When
acting as a master, the FSM is driven by the CPU. As a slave, the FSM is
driven by the bus directly. In what is (apparently) a safety mechanism,
if the bus transitions our FSM in any improper way, the FSM goes to a
"bus error" state (0x00). I could find no documented or experimental way
to get the FSM out of this state, except for a controller reset.

Since U-Boot only uses the MVTWSI controller as a bus master, this
feature only gets in the way: we do not care what happened on the bus
previously as long as the bus is ready for a new transaction. So, when
trying to start a new transaction, check for this state and reset the
controller if necessary.

Note that this should not be confused with the "deblocking" technique
(used by the `i2c reset` command), which involves pulsing SCL repeatedly
if SDA is found to be held low, in an attempt to force the bus back to
an idle state. This patch only resets the controller in case something
else had previously upset it, and (in principle) results in no
externally-observable change in behavior.

Signed-off-by: Sam Edwards <CFSworks@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Reviewed-by: Heiko Schocher <hs@denx.de>
2023-08-15 06:52:04 +02:00
Tom Rini
832148f675 Merge tag 'u-boot-rockchip-20230814' of https://source.denx.de/u-boot/custodians/u-boot-rockchip
- Add board: rk3568 EmbedFire Lubancat 2
- Fixes for rk3568 clock and pinctrl;
- Fixes for rk3308 clock and uart;
- rk3328 rock64 updates;
- Video fix on veyron board;
2023-08-14 09:11:09 -04:00
Tom Rini
70c45244d9 - fix NULL dereference in vidconsole_measure()
- fix simplefb format for raspberrypi-4b
  - fix typo in Kconfig
 -----BEGIN PGP SIGNATURE-----
 
 iGwEABECACwWIQSC4hxrSoIUVfFO0kRM6ATMmsalXAUCZNnCUQ4cYWd1c3RAZGVu
 eC5kZQAKCRBM6ATMmsalXNeWAJ9UAkaoM0B7iTAieOTSFhQNYVXlRQCeNTEISsLe
 lfCsmvp0A6Fa+8dq9s0=
 =Xt1C
 -----END PGP SIGNATURE-----

Merge tag 'video-20230814' of https://source.denx.de/u-boot/custodians/u-boot-video

 - fix NULL dereference in vidconsole_measure()
 - fix simplefb format for raspberrypi-4b
 - fix typo in Kconfig
2023-08-14 09:09:23 -04:00
Jonas Karlman
d7009faa09 pinctrl: rockchip: Fix drive and input schmitt on RK3568
On RK3568 most pins have a configurable drive strength of level 0-5 and
some pins level 0-11. When rk3568_set_drive is called with a strength
value above 7 the drv value written to reg may overflow into the write
enable bits, resulting in a bad configuration.

This cause e.g. ethernet PHY on Radxa CM3-IO board not to work after
drive is configured according to the device tree.

  Could not get PHY for ethernet@fe010000: addr 0

Level 6-11 can be configured using a second reg for some pins, however
the drv value is reused resulting in lower 6 bits being written to reg.

Input schmitt is configured in 2-bit fields on RK3568 compared to
earlier generation and 2'b10 should be used to enable input schmitt.

Change to use regmap_update_bits with a rmask to fix the overflow issue
and closer match the linux driver. Bit shift the drv value used for the
second reg to configure drive strength level 6-11. Also write correct
values for input schmitt setting.

Fixes: 1977d746aa ("rockchip: rk3568: add rk3568 pinctrl driver")
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-08-14 11:07:27 +08:00
Meng Li
04cc66c047 rpi: set the correct parameter for simple framebuffer node
When raspberrpi-4b platform  boots up, there are 2 sets of same bootup
log displayed on HDMI monitor screen, it looks like the screen is split
into 2 parts. The root cause is that video format of u-boot is different
from kernel. The fixing "a8r8g8b8" video format is used in u-boot, but
"r5g6b5" video format from framebuffer node is used in kernel image. In
order to avoid weird display status on screen, it needs to set the correct
parameter for simple framebuffer node even if it has existed.

Signed-off-by: Meng Li <Meng.Li@windriver.com>
2023-08-13 23:57:46 +02:00
Jason Wessel
28cd244e84 bcm2835: Add simiple-framebuffer for use with fkms
When the fkms dtb overlay is used only the simple-framebuffer is
presented as a usable video display. So, add "simple-framebuffer"
compatible to enable video driver bcm2835.

Signed-off-by: Jason Wessel <jason.wessel@windriver.com>
Signed-off-by: Meng Li <Meng.Li@windriver.com>
2023-08-13 23:55:57 +02:00
Bin Meng
aba6776a71 video: kconfig: Fix a typo in SPL_VIDEO_REMOVE
Add one space between 'before' and 'loading'.

Signed-off-by: Bin Meng <bmeng@tinylab.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
2023-08-13 23:09:23 +02:00
Bin Meng
01c76f1a64 video: vidconsole: Fix null dereference of ops->measure
At present vidconsole_measure() tests ops->select_font before calling
ops->measure, which would result in a null dereference when the console
driver provides no ops for measure.

Fixes: b828ed7d79 ("console: Allow measuring the bounding box of text")
Signed-off-by: Bin Meng <bmeng@tinylab.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
2023-08-13 23:08:15 +02:00
FUKAUMI Naoki
a73a28b329 rockchip: MAINTAINERS: fix board name for Radxa ROCK 4C+
align with other ROCK series.

Fixes: 2b506407c8 ("rockchip: Add MAINTAINERS entry for Radxa Rock 4C+")
Signed-off-by: FUKAUMI Naoki <naoki@radxa.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-08-12 10:39:51 +08:00
Massimo Pegorer
c71321c7c6 dts: rockchip: rk3308: Avoid warning for serial probe on prereloc
Make device tree complete and consistent for pre relocation phase. Some
nodes are missing, causing warnings to be issued on serial port probing
during pre relocation phase (uclass_get_device_by_phandle_id fails when
called by pinctrl_select_state_full: none of these failures is fatal
nor causing issues). Add to *-u-boot.dtsi all required nodes with the
'bootph-some-ram' attribute.

Signed-off-by: Massimo Pegorer <massimo.pegorer+oss@gmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-08-12 10:37:57 +08:00
Massimo Pegorer
0cd87aac5c clk: rockchip: rk3308: Support reading UART rate and clock registers
Add support to read RK3308 registers used to configure UART clocks, and
thus to get UART rate and baudrate. This fixes clock_get_rate returning
error on serial device probing. Moreover, there is no need anymore to
use 'clock-frequency' property for UART nodes in *-u-boot.dtsi files
for all cases where UART is not inited by U-Boot proper or by SPL o by
TPL code but by a preliminary external boot phase (for Rock PI S, UART
is inited by external TPL).

Signed-off-by: Massimo Pegorer <massimo.pegorer+oss@gmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-08-12 10:37:57 +08:00
Massimo Pegorer
e4c6ccc687 clk: rockchip: rk3308: Fix ordering between masking and shifting
As per definitions of masks and shift offsets in cru_rk3308.h, values
read from registers must be first masked and then shifted. By the way,
this fix is binary invariant, because in all of fixed cases the shift
offset is zero.

Signed-off-by: Massimo Pegorer <massimo.pegorer+oss@gmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-08-12 10:37:57 +08:00
Massimo Pegorer
36adce7372 rockchip: spl: Drop out of scope debug message related to uart init
Debug uart is no more inited in board_init_f function: remove this
debug message from board_init_f. If an earliest-as-possible message
after debug uart initialization is needed, enable DEBUG_UART_ANNOUNCE
Kconfig option, instead.

Signed-off-by: Massimo Pegorer <massimo.pegorer+oss@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-08-12 10:37:32 +08:00
Massimo Pegorer
08e74ac3d9 rockchip: spl: Drop useless call to debug_uart_init
Since commit 0dba45864b ("arm: Init the debug UART") function
debug_uart_init is called in crt files _main before calling
board_init_f. Therefore, there is no need to call it again
inside board_init_f implementation in arm/mach-rockchip/spl.c.

Signed-off-by: Massimo Pegorer <massimo.pegorer+oss@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-08-12 10:37:32 +08:00
Jonas Karlman
520fece4ca rockchip: rk356x-u-boot: Set max-frequency prop in sdhci node
Most board device trees for RK356x set max-frequency = <200000000> in
the sdhci node, some boards like Quartz64 do not. This result in an
error message due to sdhci driver trying to set a clock rate of 0
instead of the max-frequency value.

  rockchip_sdhci_probe clk set rate fail!

Fix this by setting a common max-frequency in rk356x-u-boot.dtsi. A
patch to set default max-frequency of sdhci node in linux is planned.

Also remove the forced status = "okay" for the sdhci and sdmmc0 nodes,
boards already set correct state for these nodes.

Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-08-12 10:35:35 +08:00
Jonas Karlman
9296f9a8d7 clk: rockchip: rk3568: Add dummy support for GMAC speed clocks
Pine64 Quartz64 boards DT reference SCLK_GMAC1_RGMII_SPEED in the
assigned-clocks property of the gmac1 node. This result in a ENOENT
error when driver core tries to set a parent for this clock.

The clock speed in rgmii/rmii mode is changed using clk_set_rate of the
tx_rx clock and not using clk_set_parent of the speed clock.

Add dummy support for SCLK_GMAC1_RGMII_SPEED and similar clocks to clk
driver to allow a driver for gmac node to probe.

Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-08-12 10:35:35 +08:00
Jonas Karlman
ff46cd5631 clk: rockchip: rk3568: Include UART clocks in SPL
The clock driver for RK3568 does not include support for UART clocks in
SPL. This result in the following message with high enough loglevel.

  ns16550_serial serial@fe660000: pinctrl_select_state_full: uclass_get_device_by_phandle_id: err=-19

Fix this by including support for UART clocks in SPL.

Fixes: 4a262feba3 ("rockchip: rk3568: add clock driver")
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Eugen Hristev <eugen.hristev@collabora.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-08-12 10:35:35 +08:00
Jonas Karlman
6da8400d7a clk: rockchip: rk3568: Fix mask for clk_cpll_div_25m_div
The field for clk_cpll_div_25m_div in CRU_CLKSEL_CON81 is 6 bits wide,
not 5 bits wide as currently defined in CPLL_25M_DIV_MASK.

Fix this and the assert so that CPLL_25M can be assigned a 25 MHz rate.

Fixes: 4a262feba3 ("rockchip: rk3568: add clock driver")
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-08-12 10:35:35 +08:00
Damon Ding
acb9812034 clk: rockchip: rk3568: Fix clk selection in rk3568_pwm_get_clk
Fix use of wrong clk selection for CLK_PWM1 on RK3568.

Fixes: 4a262feba3 ("rockchip: rk3568: add clock driver")
Signed-off-by: Damon Ding <damon.ding@rock-chips.com>
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-08-12 10:35:35 +08:00
Anton
6e710897aa rockchip: cru: Enable cpu info support for rk3568
Add cru structure definition in head file to support cpu_info driver.

Series-version: 2
Series-changes: 2
Format the patch header, add commit message and signature.

Signed-off-by: Anton <vao@asu-vei.ru>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2023-08-12 10:28:30 +08:00
Alvaro Fernando García
8300cebcd6 video: avoid build failure on veyron board
533ad9dc avoided an overflow but causes compilation
failure on 32bit boards (eg. veyron speedy)

this commit uses div_u64 which has a fallback codepath
for 32bit platforms

Signed-off-by: Alvaro Fernando García <alvarofernandogarcia@gmail.com>
Tested-by: Simon Glass <sjg@chromium.org>  # chromebook_jerry
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-08-12 10:18:12 +08:00
Andy Yan
bb38db086c rockchip: rk3568: Add EmbedFire Lubancat 2 support
LubanCat2 is a rk3568 based SBC from EmbedFire.

Specification:
- Rockchip rk3568
- LPDDR4/4X 1/2/4/8 GB
- TF scard slot
- eMMC 8/32/64/128 GB
- Gigabit ethernet x 2
- HDMI out
- USB 2.0 Host x 1
- USB 2.0 Type-C OTG x 1
- USB 3.0 Host x 1
- Mini PCIE interface for WIFI/BT module
- M.2 key for 2280 NVME
- 40 pin header

The dts file is sync from linux mainline.

Signed-off-by: Andy Yan <andyshrk@163.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-08-12 10:17:59 +08:00
Jagan Teki
2fa09b455a rockchip: rv1126: Enable fdtoverlay support
Add fdtoverlay_addr_r and enable OF_LIBFDT_OVERLAY for the
use of DT overlay in RV1126.

Signed-off-by: Jagan Teki <jagan@edgeble.ai>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-08-12 10:14:51 +08:00
Peter Robinson
10e38327f0 rockchip: dts: rk3328: rock64: Align spi flash entry
Align the SPI flash entry with upstream. There's no need
to diverge here.

Signed-off-by: Peter Robinson <pbrobinson@gmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-08-12 10:13:44 +08:00
Peter Robinson
080030f276 rockchip: dts: rk3328: Add rng details to u-boot.dtsi
Add the rk3328 rng details to the u-boot.dtsi and
enable the RNG on the Rock64 to be able to provide
a random seed via UEFI.

Signed-off-by: Peter Robinson <pbrobinson@gmail.com>
(Fix typo message)
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2023-08-12 10:13:14 +08:00
Peter Robinson
a13a7a0b45 config: rock64: enable efuse for stable mac addr
Enable the rockchip efuse driver on the Rock64 to
provide a stable ethernet address on the device.

Signed-off-by: Peter Robinson <pbrobinson@gmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-08-12 10:13:06 +08:00
Jonas Karlman
0e2474f550 pci: rockchip: Release resources on failing probe
The PCIe driver for RK3399 is affected by a similar issue that was fixed
for RK35xx in the commit e04b67a7f4 ("pci: pcie_dw_rockchip: release
resources on failing probe").

Resources are not released on failing probe, e.g. regulators may be left
enabled and the ep-gpio may be left in a requested state.

Change to use regulator_set_enable_if_allowed and disable regulators
after failure to keep regulator enable count balanced, ep-gpio is also
released on regulator failure.

Also add support for the vpcie12v-supply, remove unused include and
check return value from dev_read_addr_name.

Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-08-12 09:59:18 +08:00
Quentin Schulz
e5422ea512 rockchip: rk3399: remove duplicate call to regulators_enable_boot_on
An earlier commit makes the common SPL code call
regulators_enable_boot_on and regulators_enable_boot_off before
iterating over possible boot media for U-Boot proper. There is therefore
no need to do this in the rk3399-specific code, so let's remove it.

Cc: Quentin Schulz <foss+uboot@0leil.net>
Tested-by: Xavier Drudis Ferran <xdrudis@tinet.cat>
Signed-off-by: Quentin Schulz <quentin.schulz@theobroma-systems.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2023-08-12 09:58:55 +08:00
Tom Rini
a5899cc69a Merge https://source.denx.de/u-boot/custodians/u-boot-watchdog
- cmd: cyclic: Remove duplicate command name in help text (Alexander)
- ftwdt010: need to reset watchdog in ftwdt010_wdt_start() (Sergei)
2023-08-10 11:40:09 -04:00
Tom Rini
824f104422 Merge https://source.denx.de/u-boot/custodians/u-boot-riscv
+ Add USB host support on VisionFive2 board
+ Enable SPI flash support on VisionFive2 board
+ Enable Random Number Generator in RISC-V QEMU board
+ Display new SBI extension
+ Add SPL_ZERO_MEM_BEFORE_USE Kconfig for jh7110 L2 LIM
  (Loosely-Integrated Memory)
2023-08-10 10:36:43 -04:00
Sergei Antonov
160984ed3a watchdog: ftwdt010: need to reset watchdog in ftwdt010_wdt_start()
ftwdt010_wdt_start() has to call ftwdt010_wdt_reset() after setting-up
the timeout in the same fashion ftwdt010_wdt_expire_now() does it.

Without this patch the "wdt start <ms>" command does not actually start
the watchdog timer until the "wdt reset" command is executed.

Signed-off-by: Sergei Antonov <saproj@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
2023-08-10 08:39:16 +02:00
Alexander Dahl
8ba4eae01d cmd: cyclic: Remove duplicate command name in help text
Function 'cmd_usage()' already prints one command in usage before
printing out the help text given to the U_BOOT_CMD_WITH_SUBCMDS macro.

Wrong previous output:

    Usage:
    cyclic cyclic demo <cycletime_ms> <delay_us> - register cyclic demo function
    cyclic list - list cyclic functions

Signed-off-by: Alexander Dahl <ada@thorsis.com>
Reviewed-by: Stefan Roese <sr@denx.de>
2023-08-10 08:39:11 +02:00