There are several differences between Linux, Windows and U-boot for initialising the
USB devices. While analysing the behaviour of U-boot it turned out that U-boot does
things really different, and some are wrong (compared to the USB standard).
This patch fixes some errors:
* The NEW_init procedure that was already in the code is good, while the old procedure
is wrong. See code comments for more info.
* On a Control request the data returned by the device can be more than 8 bytes, while
the host limits it to 8 bytes. This caused the host to generate a DataOverrun error.
This results in a lot of USB sticks not being recognised, and the transmission ended
frequently with a CTL:TIMEOUT Error.
* Added a flag CONFIG_LEGACY_USB_INIT_SEQ to allow users to use the old init procedure.
Signed-off-by: Remy Bohmer <linux@bohmer.net>
Signed-off-by: Markus Klotzbuecher <mk@denx.de>
This patch refactors some large routines of the USB OHCI code by
making some routines smaller and more readable which helps
debugging and understanding the code. (Makes the code looks
somewhat more like the Linux implementation.)
Also made entire file compliant to Linux Coding Rules (checkpatch.pl compliant)
Signed-off-by: Remy Bohmer <linux@bohmer.net>
Signed-off-by: Markus Klotzbuecher <mk@denx.de>
The GCC-compiler makes an optimisation error while optimising the routine
usb_set_maxpacket(). This should be fixed in the compiler in the first place,
but there lots of compilers out there that makes this error, that it is
probably wiser to workaround it in U-boot itself.
What happens is that the register r3 is used as loop-counter 'i', but gets
overwritten later on. From there it starts using register r3 for several other
things and the assembler code is becoming a big mess. This is clearly a compiler bug.
This error occurs on at least several versions of Code Sourcery Lite compilers
for ARM. Like the Edition 2008q1, and 2008q3, It has also been seen on other
compilers, while compiling for armv4t, or armv5te with Os, O1 and O2.
We work around it by splitting up this routine in 2 parts, and making sure that
the split out part is NOT inlined any longer. This will make GCC spit out assembler
that do not show this problem. Another possibility is to adapt the Makefile to stop
optimisation for the complete file. I think this solution is nicer.
Signed-off-by: Remy Bohmer <linux@bohmer.net>
Signed-off-by: Markus Klotzbuecher <mk@denx.de>
Fix TBI PHY accesses to use the proper offset in CPU register space. The
previous code would incorrectly access the TBI PHY by reading/writing to CPU
register space at the same location as would be used to access external PHYs.
Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
Acked-by: Andy Fleming <afleming@freescale.com>
After switching to using the CFI flash driver, the correct remapping
of the flash banks was forgotten.
Also, some boards were not adapted, and the old legacy flash driver
was not removed yet.
Signed-off-by: Wolfgang Denk <wd@denx.de>
This patch is an attempt to implement autoprobing for the Lime
presence on the bus.
Configure GPCM for Lime CS2 and try to access chip ID registers.
Second read atempt delivers register values if the chip is present.
Signed-off-by: Anatolij Gustschin <agust@denx.de>
Commit 2a1a2cb6 didnt remove the dummy mem reservation in fdt_chosen,
and this stopped Linux from booting with a Ramdisk. This patch fixes
this, by deleting the useless dummy mem reservation.
When booting with a Ramdisk, a fix offset FDT_RAMDISK_OVERHEAD is now
added to of_size, so we dont need anymore a dummy mem reservation.
I measured the value of FDT_RAMDISK_OVERHEAD on a MPC8270 based
system (=0x44 bytes) and rounded it up to 0x80).
Signed-off-by: Heiko Schocher <hs@denx.de>
Acked-by: Kumar Gala <galak@kernel.crashing.org>
This patch deletes oobavail assignments, they're calculated by the nand
core code in nand_scan_tail, plus current oobavail values are wrong for
the LP NANDs.
Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
Signed-off-by: Scott Wood <scottwood@freescale.com>
This patch implements support for flash-based BBT for chips working
through ELBC NAND controller, so that NAND core will not have to re-scan
for bad blocks on every boot.
Because ELBC controller may provide HW-generated ECCs we should adjust
bbt pattern and bbt version positions in the OOB free area.
Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
Signed-off-by: Scott Wood <scottwood@freescale.com>
For large page chips, nand_bbt is looking into OOB area, and checking
for "0xff 0xff" pattern at OOB offset 0. That is, two bytes should be
reserved for bbt means.
But ELBC driver is specifying ecclayout so that oobfree area starts at
offset 1, so only one byte left for the bbt purposes.
This causes problems with any OOB users, namely JFFS2: after first mount
JFFS2 will fill all OOBs with "erased marker", so OOBs will contain:
OOB Data: ff 19 85 20 03 00 ff ff ff 00 00 08 ff ff ff ff
OOB Data: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
OOB Data: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
OOB Data: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
And on the next boot, NAND core will rescan for bad blocks, then will
see "0xff 0x19" pattern, and will mark all blocks as bad ones.
To fix the issue we should implement our own bad block pattern: just one
byte at OOB start. Though, this will work only for x8 chips. For x16
chips two bytes must be checked. Since ELBC driver does not support x16
NANDs (yet), we're safe for now.
Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
Signed-off-by: Scott Wood <scottwood@freescale.com>
This patch fixes a problem introdiced with patch
bbeff30c [ppc4xx: Remove superfluous dram_init() call or replace it by
initdram()].
The boards affected are:
- PCI405
- PPChameleonEVB
- quad100hd
- taihu
- zeus
Signed-off-by: Stefan Roese <sr@denx.de>
This patch prevents linker error on AT91RM9200 boards, if
CONFIG_CMD_I2_TREE is set.
It implements i2c_set_bus_speed and i2c_get_bus_speed as a dummy function.
Signed-off-by: Jens Scharsig <esw@bus-elektronik.de>
This patch changes get_timer() for i.MX to return the time since
'base' instead of the time since the counter was at zero.
Symptom seen is flash timeout errors when erasing or programming a
sector using the common cfi flash code.
Signed-off-by: Andrew Dyer <adyer@righthandtech.com>
1) Change the i.MX serial driver to use the baud rate set in the
u-boot environment
2) don't assume a 16MHz value for PERCLK1 in baud rate calculations
3) don't write a 1 to the RDR bit in the USR2 reg. (bit is not "write
one to clear" like other status bits in the reg.)
Signed-off-by: Andrew Dyer <adyer@righthandtech.com>
Code in cpu/arm920t/start.S will die with a compilation error if
CONFIG_STACKSIZE + CFG_MALLOC_LEN works out to an invalid constant for
the ARM sub instruction. Change the code so that each is subtracted
independently to avoid the error.
Signed-off-by: Andrew Dyer <adyer@righthandtech.com>
- Correct Invalid #define of MPUTIM_PTV_MASK for
omap1510 & omap730 register definition
MPUTIM_PTV_MASK is defined as
#define MPUTIM_PTV_MASK (0x7<<PTV_BIT)
while it should have been
#define MPUTIM_PTV_MASK (0x7<<MPUTIM_PTV_BIT)
- Below Patch corrects the same
Signed-off-by: Gururaja Hebbar <gururajakr@sanyo.co.in>
The i.MX31 has three SPI buses and each bus has several chip selects
and the MC13783 chip can be connected to any of these. The current
RTC driver for MC13783 is hardcoded for CSPI2/SS2.
This patch makes make MC13783 SPI bus and chip select configurable
via CONFIG_MC13783_SPI_BUS and CONFIG_MC13783_SPI_CS.
Signed-off-by: Magnus Lilja <lilja.magnus@gmail.com>
This patch adds the reset_timer() function (needed by nand_base.c) and
modifies the get_timer_masked() to work in the same way as the omap24xx
function.
Signed-off-by: Magnus Lilja <lilja.magnus@gmail.com>
