Commit graph

82 commits

Author SHA1 Message Date
Masahiro Yamada
61f2e5ee12 mmc: sdhci: change data transfer failure into debug message
During the tuning, drivers repeat data transfer, changing timing
parameters in the controller hardware.  So, the tuning commands
(CMD19 for SD, CMD21 for eMMC) fail, and this is not a problem
at all.

Showing "Error detected..." in normal operation just make users
upset.  This should not be shown.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2018-01-22 14:11:58 +09:00
Masahiro Yamada
be165fbbf1 mmc: sdhci: do not overwrite host_caps in sdhci_setup_cfg()
This line overwrites host_cap that has been set by drivers and/or
helpers like mmc_of_parse().  Accumulate capabilities flags.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2018-01-22 14:11:58 +09:00
Heinrich Schuchardt
bb7b4ef370 mmc: sdhci: do not compare pointer to 0
data is defined as struct mmc_data *data.
So it should not be compared to 0.

Problem identified with Coccinelle.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2018-01-12 18:11:03 +09:00
Jorge Ramirez-Ortiz
713e6815d9 mmc: sdhci: don't clear SDHCI_INT_STATUS register during CMD_INHIBIT
Fixes emmc initialization regression on the db410c platform.

Clearing this register while SDHCI_PRESENT_STATE reports
SDHCI_CMD_INHIBIT leads to undefined behaviour on the db410c.

When commit 7dde50 was merged (mmc: sdhci: Wait for SDHCI_INT_DATA_END
when transferring), SDHCI transfers transitioned to wait for bit
SDHCI_INT_DATA_END before flagging transfers done.

Without this patch, the db410 platform fails to initialize its eMMC
due to all of its transfers timing out (SDHCI_INT_DATA_END is never
raised after all the blocks have been transferred).

Signed-off-by: Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org>
2018-01-12 18:11:03 +09:00
Simon Glass
e7881d85a9 dm: mmc: Drop CONFIG_DM_MMC_OPS
All boards which use DM_MMC have now been converted to use DM_MMC_OPS.
Drop the option and good riddance.

Signed-off-by: Simon Glass <sjg@chromium.org>
2017-08-17 16:59:55 +09:00
Wenyou Yang
0e0dcc1916 mmc: sdhci: Fix maximum clock for programmable clock mode
In the programmable clock mode, the SDCLK frequency is incorrectly
assigned when the maximum clock has been assigned during probe,
this causes the SDHCI not work well.

In the programmable clock mode, when calculating the SDCLK Frequency
Select, when the maximum clock has been assigned, it is the actual
value, should not be multiplied by host->clk_mul. Otherwise, the
maximum clock is multiplied host->clk_mul by the base clock achieved
from the BASECLKF field of the Capabilities 0 Register.

Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
2017-05-15 18:28:22 +09:00
Alex Deymo
7dde50d707 mmc: sdhci: Wait for SDHCI_INT_DATA_END when transferring.
sdhci_transfer_data() function transfers the blocks passed up to the
number of blocks defined in mmc_data, but returns immediately once all
the blocks are transferred, even if the loop exit condition is not met
(bit SDHCI_INT_DATA_END set in the STATUS word).

When doing multiple writes to mmc, returning right after the last block
is transferred can cause the write to fail when sending the
MMC_CMD_STOP_TRANSMISSION command right after the
MMC_CMD_WRITE_MULTIPLE_BLOCK command, leaving the mmc driver in an
unconsistent state until reboot. This error was observed in the rpi3
board.

This patch waits for the SDHCI_INT_DATA_END bit to be set even after
sending all the blocks.

Test: Reliably wrote 2GiB of data to mmc in a rpi3.

Signed-off-by: Alex Deymo <deymo@google.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-04-14 15:23:14 +09:00
Kevin Liu
fa7720b21e mmc: sdhci: only flush cache for data command
No need to flush cache for command without data.

Signed-off-by: Kevin Liu <kevinliu@asrmicro.com>
2017-03-21 21:03:14 +09:00
Stefan Roese
210841c690 mmc: sdhci: Add support for optional controller specific set_ios_post()
Some SDHCI drivers might need to do some special controller configuration
after the common clock set_ios() function has been called (speed / width
configuration). This patch adds a call to the newly created function
set_ios_port() when its configured in the host driver.

This will be used by the Xenon SDHCI controller driver used on the
Marvell Armada 3700 and 7k/8k ARM64 SoCs.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Jaehoon Chung <jh80.chung@samsung.com>
Cc: Simon Glass <sjg@chromium.org>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
2017-01-25 07:03:44 +01:00
Stefan Roese
899fb9e352 mmc: sdhci: Clear SDHCI_CLOCK_CONTROL before configuring the new value
This patch completely clears the SDHCI_CLOCK_CONTROL register before the
new value is configured instead of just clearing the 2 bits
SDHCI_CLOCK_CARD_EN and SDHCI_CLOCK_INT_EN. Without this change, some
clock configurations will lead to the "Internal clock never stabilised."
error message on the Xenon SDHCI controller used on the Marvell Armada
3700 and 7k/8k ARM64 SoCs.

The Linux SDHCI core driver also writes 0 to this register before
the new value is configured. So this patch simplifies the driver a bit
and brings the U-Boot driver more in-line with the Linux one.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Jaehoon Chung <jh80.chung@samsung.com>
Cc: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Cc: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
2017-01-25 07:03:39 +01:00
Stefan Herbrechtsmeier
6d0e34bf4e mmc: sdhci: Distinguish between base clock and maximum peripheral frequency
The sdhci controller assumes that the base clock frequency is fully supported by
the peripheral and doesn't support hardware limitations. The Linux kernel
distinguishes between base clock (max_clk) of the host controller and maximum
frequency (f_max) of the card interface. Use the same differentiation and allow
the platform to constrain the peripheral interface.

Signed-off-by: Stefan Herbrechtsmeier <stefan.herbrechtsmeier@weidmueller.com>
2017-01-23 15:37:42 +09:00
Masahiro Yamada
bf9c4d1464 mmc: sdhci: fix NULL pointer access when host->ops is not set
Until recently, sdhci_ops was used only for overriding IO accessors.
(so, host->ops was not set by any drivers except bcm2835_sdhci.c)

Now, we have more optional callbacks, get_cd, set_control_reg, and
set_clock.  However, the code

    if (host->ops->get_cd)
            host->ops->get_cd(host);

... expects host->ops is set for all drivers.

Commit 5e96217f04 ("mmc: pic32_sdhci: move the code to
pic32_sdhci.c") and commit 62226b6863 ("mmc: sdhci: move the
callback function into sdhci_ops") added sdhci_ops for pic32_sdhci.c
and s5p_sdhci.c, but the other drivers still do not (need not) set
host->ops because all callbacks in sdhci_ops are optional.

host->ops must be checked to avoid the system crash caused by NULL
pointer access.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-01-13 12:17:03 +09:00
Jaehoon Chung
3fd0a9ba8c mmc: sdhci: combine the Host controller v3.0 feature into one condition
It doesn't need to seperate the condition.

Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
2017-01-11 19:40:13 +09:00
Jaehoon Chung
f37b7e4f6c mmc: sdhci: remove the SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER
Ther is no usage anywhere. It doesn't need to maintain this bit.

Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
2017-01-11 19:40:13 +09:00
Jaehoon Chung
62226b6863 mmc: sdhci: move the callback function into sdhci_ops
callback function should be moved into sdhci_ops struct.
Other controller can use these ops for controlling clock or their own
specific register.

Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
2017-01-11 19:40:13 +09:00
Jaehoon Chung
07b0b9c00c mmc: change the set_ios return type from void to int
To maintain consistency, set_ios type of legacy mmc_ops changed to int.

Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
2017-01-11 19:40:13 +09:00
Jaehoon Chung
6f88a3a5d9 mmc: sdhci: remove the SDHCI_QUIRK_NO_CD
This quirk doesn't need anymore.
It's replaced to get_cd callback function.

Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
2017-01-11 19:40:12 +09:00
Jaehoon Chung
5e96217f04 mmc: pic32_sdhci: move the code to pic32_sdhci.c
This code is used for only pic32_sdhci controller.
To remove the "#ifdef", moves to pic32_sdhci.c.
And use the get_cd callback function.

Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
2017-01-11 19:40:11 +09:00
Jaehoon Chung
62358a988e mmc: sdhci: remove the unused code about testing Card detect
This code is dead code..There is no usage anywhere.

Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
2017-01-11 18:14:47 +09:00
Jaehoon Chung
ecd7b246f6 mmc: sdhci: disable the 8bit mode when host doesn't support it
Buswidth is depeneded on Hardware schematic.
Evne though host can support the 8bit buswidth, if hardware doesn't
support 8bit mode, it doesn't work fine.
So the buswidth mode selection leaves a matter in each SoC drivers.

On the contrary to this, hardware supports 8bit mode, but host doesn't
support it. then controller has to disable the MMC_MODE_8BIT.
(Host can check whether 8bit mode is supported or not, since V3.0)

Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
2017-01-11 18:14:47 +09:00
Masahiro Yamada
45a68fe267 mmc: move some SDHCI related options to Kconfig
While I moved the options, I also renamed them so that they are all
prefixed with MMC_SDHCI_.

This commit was created in the following steps.

[1] Rename with the following command
find . -name .git -prune -o ! -path ./scripts/config_whitelist.txt \
-type f -print | xargs sed -i -e '
s/CONFIG_MMC_SDMA/CONFIG_MMC_SDHCI_SDMA/g
s/CONFIG_BCM2835_SDHCI/CONFIG_MMC_SDHCI_BCM2835/g
s/CONFIG_KONA_SDHCI/CONFIG_MMC_SDHCI_KONA/g
s/CONFIG_MV_SDHCI/CONFIG_MMC_SDHCI_MV/g
s/CONFIG_S5P_SDHCI/CONFIG_MMC_SDHCI_S5P/g
s/CONFIG_SPEAR_SDHCI/CONFIG_MMC_SDHCI_SPEAR/g
'

[2] create the Kconfig entries in drivers/mmc/Kconfig

[3] Move the options by the following command
tools/moveconfig.py -y MMC_SDHCI_SDMA MMC_SDHCI_BCM2835 \
MMC_SDHCI_KONA MMC_SDHCI_MV MMC_SDHCI_S5P MMC_SDHCI_SPEAR

[4] Sort drivers/mmc/Makefile for readability

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
2016-12-29 13:08:16 -05:00
Jaehoon Chung
2a1bedaa03 mmc: sdhci: assign to clk_mul when host version is upper than SD3.0
To prevent the wrong value check the SD version.

Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
2016-10-28 11:02:16 +09:00
Jaehoon Chung
be256cbf04 mmc: sdhci: fix the "misaligned operation at range" for cache
This pathc is fixed the below thing.
If misaligned the cache range, Just flush to CACHLINE_SIZE.
"CACHE: Misaligned operation at range [7ae55b00, 7ae55b08]"

Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
2016-10-28 11:02:16 +09:00
Jaehoon Chung
2cb5d67c1a mmc: sdhci: use the generic error number
Use the generic error number instead of meaningless value.

Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2016-10-10 15:23:33 +09:00
Jaehoon Chung
895549a2d9 mmc: sdhci: use the host version value in sdhci_setup_cfg
"host->version" isn't a SoC specific value.
It doesn't need to get in each SoC drivers.

Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
Reviewed-by: Minkyu Kang <mk7.kang@samsung.com>
2016-10-10 15:23:33 +09:00
Wenyou Yang
6dffdbc3a5 mmc: sdhci: Add the programmable clock mode support
Add the programmable clock mode for the clock generator.

Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
2016-09-20 06:46:01 +09:00
Masahiro Yamada
65a25b2086 mmc: sdhci: drop CONFIG_ from CONFIG_SDHCI_CMD_MAX_TIMEOUT
No need for per-SoC adjustment for this parameter.  It should be
determined by the slowest hardware.  Currently, no board overrides
this CONFIG, so 3.2 sec is large enough.  (If not, we can make it
even larger.)

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-09-20 06:46:01 +09:00
Masahiro Yamada
d8ce77b28c mmc: sdhci: drop CONFIG_ from CONFIG_SDHCI_CMD_DEFAULT_TIME
This CONFIG is not configurable since it is not guarded by #ifndef.
Nobody has complained about that, so there is no need to keep it as
a CONFIG option.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-09-20 06:46:01 +09:00
Masahiro Yamada
15bd09959f mmc: sdhci: move SDMA capability check to sdhci_setup_cfg()
If CONFIG_BLK is enabled, add_sdhci() is never called.  Move this
quirk handling to sdhci_setup_cfg(), which is now the central place
for hardware capability checks.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-09-20 06:46:01 +09:00
Masahiro Yamada
3137e645e2 mmc: sdhci: move broken voltage quirk handling to sdhci_setup_cfg()
If CONFIG_BLK is enabled, add_sdhci() is never called.  Move this
quirk handling to sdhci_setup_cfg(), which is now the central place
for hardware capability checks.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-09-20 06:46:01 +09:00
Masahiro Yamada
6c67954c93 mmc: sdhci: move error message to more relevant place
"Hardware doesn't specify base clock frequency" may not be only the
error case of sdhci_setup_cfg().  It is better to print this where
the corresponding error is triggered.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-09-20 06:46:01 +09:00
Masahiro Yamada
8d549b61dc mmc: sdhci: move sdhci_reset() call to sdhci_init()
If CONFIG_BLK is enabled, add_sdhci() is never called.
So, sdhci_reset() is not called, either.  This is a problem for
my board as it needs the reset to start from a sane state.

Move the add_sdhci() call to sdhci_init(), which is visited
by both of the with/without CONFIG_BLK cases.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-09-20 06:46:01 +09:00
Jaehoon Chung
89f69e5173 mmc: sdhci: fix the compiler warning when disable CONFIG_MMC_SDMA
When disabled CONFIG_MMC_SDMA, variable caps didn't use.
This patch fixes the compiler error for -Wunused-but-set-variable

Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
2016-08-05 20:48:01 +09:00
Jaehoon Chung
14bed52d27 mmc: sdhci: remove the unnecessary arguments for sdhci_setup_cfg
Some arguments don't need to pass to sdhci_setup_cfg.
Generic variable can be used in sdhci_setup_cfg, and some arguments are
already included in sdhci_host struct.

It's enough that just pass the board specific things to sdhci_setup_cfg().
After removing the unnecessary arguments, it's more simpler than before.
It doesn't consider "Version" and "Capabilities" anymore in each SoC
driver.

Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2016-08-05 11:31:07 +09:00
Jaehoon Chung
6a879ec8e7 mmc: sdhci: remove the unused argument for sdhci_setup_cfg
buswidth isn't used anywhere in sdhci_setup_cfg.

Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
Reviewed-by: Minkyu Kang <mk7.kang@samsung.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2016-08-05 11:21:25 +09:00
Jaehoon Chung
e1ea7c44d6 mmc: sdhci: revert "mmc: sdhci: Claer high speed if not supported"
This "commit 429790026021d522d51617217d4b86218cca5750" is wrong.
SDHCI_QUIRK_NO_HISPD_BIT is for skipping to set CTRL_HISPD bit.

For example, Exynos didn't have CTRL_HISPD. But Highspeed mode
is supported.
(This quirks doesn't mean  that driver didn't support the Highseepd mode.)

Note: If driver didn't support the Highspeed Mode, use or add the other
quirks.

After applied this patch, all Exynos SoCs are just running with 25MHz.

Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
2016-08-05 11:21:25 +09:00
Jaehoon Chung
915ffa5213 mmc: use the generic error number
Use the generic error number instead of specific error number.
If use the generic error number, it can debug more easier.

Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Minkyu Kang <mk7.kang@samsung.com>
2016-08-05 11:21:25 +09:00
Jaehoon Chung
17ea3c8628 mmc: sdhci: set to INT_DATA_END when there are data
There is no data, it doesn't needs to wait for completing data transfer.
(It seems that it can be removed.)
Almost all timeout error is occured from stop command without data.
After applied this patch, I hope that we don't need to increase timeout value anymore.

Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
Acked-by: Lukasz Majewski <l.majewski@samsung.com>
Tested-by: Lukasz Majewski <l.majewski@samsung.com>
Acked-by: Minkyu Kang <mk7.kang@samsung.com>
2016-08-05 11:21:24 +09:00
Masahiro Yamada
bae4a1fdf5 mmc: sdhci: clean up timeout detection
The current timeout detection logic is not very nice; it calls
get_timer(start) in the while() loop, and then calls it again after
the loop to check if a timeout error happened.

Because of the time difference between the two calls of get_timer(),
the timeout detected after the loop may not be true.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Acked-by: Jaehoon Chung <jh80.chung@samsung.com>
Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
2016-08-05 11:21:24 +09:00
Siva Durga Prasad Paladugu
1d405e207b mmc: sdhci: Disable internal clock enable bit
Disable internal clock by clearing the internal
clock enable bit. This bit needs to be cleared too
when we stop the SDCLK for changing the frequency
divisor. This bit should be set to zero when the
device is not using the Host controller.

Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2016-07-22 14:03:50 +02:00
Simon Glass
ef1e4eda6b dm: mmc: sdhci: Support CONFIG_BLK and CONFIG_DM_MMC_OPS
Add support for using driver model for block devices and MMC operations in
this driver.

Signed-off-by: Simon Glass <sjg@chromium.org>
2016-07-11 14:06:44 -06:00
Simon Glass
2a809093f0 dm: mmc: sdhci: Refactor configuration setup to support DM
Move the configuration setting into a separate function which can be used by
the driver-model code.

Signed-off-by: Simon Glass <sjg@chromium.org>
2016-07-11 14:06:44 -06:00
Steve Rae
d90bb43933 mmc: increase MMC SDHCI read status timeout
Otherwise,  ocassionally see errors like this:
  Flashing sparse image at offset 2078720
  Flashing Sparse Image
  sdhci_send_command: Timeout for status update!
  mmc fail to send stop cmd
  write_sparse_image: Write failed, block #2181088 [0]

This does not affect the actual writing speed, which is controlled by
the default value:
  CONFIG_SDHCI_CMD_DEFAULT_TIMEOUT

It only increases the retries when reading:
  SDHCI_INT_STATUS
to avoid the timeout error.

Signed-off-by: Steve Rae <steve.rae@raedomain.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Tested-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Tested-by: Jaehoon Chung <jh80.chung@samsung.com>
2016-07-01 17:42:57 -04:00
Simon Glass
19d2e34237 dm: mmc: Convert sdhci to support CONFIG_BLK
Update sdhci.c so that it works with driver model enabled for block devices.

Signed-off-by: Simon Glass <sjg@chromium.org>
2016-05-27 10:23:08 -06:00
Simon Glass
bcce53d048 dm: block: Rename device number member dev to devnum
This is a device number, and we want to use 'dev' to mean a driver model
device. Rename the member.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Stephen Warren <swarren@nvidia.com>
2016-03-14 15:34:50 -06:00
Andrei Pistirica
102142c9e0 drivers: mmc: add driver for Microchip PIC32 SDHCI controller.
This driver implements platform specific glue and fixups for
PIC32 internal SDHCI controller.

Signed-off-by: Andrei Pistirica <andrei.pistirica@microchip.com>
Signed-off-by: Sandeep Sheriker Mallikarjun <sandeepsheriker.mallikarjun@microchip.com>
Signed-off-by: Purna Chandra Mandal <purna.mandal@microchip.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2016-02-01 22:14:01 +01:00
Siva Durga Prasad Paladugu
4297900260 mmc: sdhci: Clear high speed if not supported
Clear high speed bit if it was not supported by
the driver.

Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Emil Lenchak <emill@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2016-01-27 15:55:54 +01:00
Wenyou Yang
79667b7b76 mmc: sdhci: Fix the SD clock stop sequence
According to the SDHC specification, stopping the SD Clock is by setting
the SD Clock Enable bit in the Clock Control register at 0, instead of
setting all bits at 0.

Before stopping the SD clock, we need to make sure all SD transactions
to complete, so add checking the CMD and DAT bits in the Presen State
register, before stopping the SD clock.

Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
2015-11-03 14:21:30 +01:00
Stefan Roese
492d3223b0 mmc: sdhci.c: Add config option to use a fixed buffer for transfers
While implementing SDIO/MMC SPL booting for the Marvell Armada 38x, the
following problem occured. The SPL runs in internal SRAM which is
the L2 cache locked to memory. When the MMC buffers now are located
on the stack (or bss), the SDIO controller (SDHCI) can't write into
this L2 cache memory.

This patch introduces a method to use a fixed buffer that will be
used for all transfers by defining CONFIG_FIXED_SDHCI_ALIGNED_BUFFER.
This way, the board can use this buffer address located in SDRAM
for all transfers. This solves this SPL problem on the A38x and
should only be used in the SPL U-Boot version.

Tested for SPL booting on Marvell Armada 38x DB-88F6820-GP board.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Pantelis Antoniou <panto@antoniou-consulting.com>
Cc: Luka Perkov <luka.perkov@sartura.hr>
2015-07-10 14:54:05 +02:00
Stefan Roese
29905a451b mmc: sdhci: Use timer based timeout detection in sdhci_send_command()
The loop counter based timeout detection does not work on the Armada
38x based board (DB-88F6820-GP). At least with dcache enabled a
timeout is detected. Without dcache enabled, the timeout does not
occur. Increasing the loop counter solves this issue. But a better
solution is to use a timer based timeout detection instead. This
patch now implements this timer based detection.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Pantelis Antoniou <panto@antoniou-consulting.com>
Cc: Luka Perkov <luka.perkov@sartura.hr>
2015-07-10 14:54:00 +02:00