Commit graph

47 commits

Author SHA1 Message Date
Siva Durga Prasad Paladugu
1a897668ac fpga: Added support to load bit stream from SD/MMC
Added support to load a bitstream image in chunks by reading it in
chunks from SD/MMC.
Command format:
loadfs [dev] [address] [image size] [blocksize] <interface>
       [<dev[:part]>] <filename>
Example: fpga loadfs 0 1000000 3dbafc 4000 mmc 0 fpga.bin

Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2014-05-20 15:23:46 +02:00
Michal Simek
5b815c9c61 fpga: zynqpl: Clean partial bitstream handling
Do not do partial bitstream detection based on bitstream
size and use bitstream_type argument which is passed
from the fpga core.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2014-05-20 15:23:46 +02:00
Michal Simek
7a78bd2679 fpga: Define bitstream type based on command selection
Clean up partial, full and compressed bitstream handling.
U-Boot supports full bitstream loading and partial
based on detection which is not 100% correct.
Extending fpga_load/fpga_loadbitstream() with one more
argument which stores bitstream type.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2014-05-20 15:23:46 +02:00
Siva Durga Prasad Paladugu
3108185985 fpga: zynq: Use helper function zynq_validate_bitstream
Use helper function zynq_validate_bitstream so that the
code can be reused easily for different cases of dma transfer.

Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2014-05-13 09:14:05 +02:00
Siva Durga Prasad Paladugu
a0735a34f8 fpga: zynq: Use helper functions for zynq dma
Use zynq_dma_xfer_init, zynq_align_dma_buffer,
zynq_dma_transfer helper function performing dma
transfers so that the code can be reused easily for
different cases of dma transfer.

Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2014-05-13 09:14:04 +02:00
Michal Simek
42a74a08eb fpga: zynq: Remove sparse warnings
Warnings:
drivers/fpga/zynqpl.c:150:32: warning: Using plain integer as NULL pointer
drivers/fpga/zynqpl.c:152:16: warning: Using plain integer as NULL pointer

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2014-05-13 09:14:04 +02:00
Michal Simek
14cfc4f373 fpga: xilinx: Simplify load/dump/info function handling
Connect FPGA version with appropriate operations
to remove huge switch-cases for every FPGA family.
Tested on Zynq. Spartan2/Spartan3/Virtex2 just compile test.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2014-05-13 09:13:59 +02:00
Michal Simek
f8c1be9816 fpga: xilinx: Avoid CamelCase for in Xilinx_desc
No functional changes.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2014-05-13 09:12:53 +02:00
Michal Simek
d9071ce0a8 fpga: virtex2: Avoid CamelCase
No functional changes.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2014-05-13 09:12:53 +02:00
Michal Simek
2a6e3869f2 fpga: spartan3: Avoid CamelCase
No functional changes.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2014-05-13 09:12:52 +02:00
Michal Simek
b625b9aef3 fpga: spartan2: Avoid CamelCase
No functional changes.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2014-05-13 09:12:52 +02:00
Alexey Brodkin
1ace402239 sizes.h - consolidate for all architectures
Copied from Linux sources "include/linux/sizes.h" commit
413541dd66d51f791a0b169d9b9014e4f56be13c

Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>

Cc: Vineet Gupta <vgupta@synopsys.com>
Cc: Tom Rini <trini@ti.com>
Cc: Stefan Roese <sr@denx.de>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Acked-by: Tom Rini <trini@ti.com>
Acked-by: Stefan Roese <sr@denx.de>
[trini: Add bcm Kona platforms to the patch]
Signed-off-by: Tom Rini <trini@ti.com>
2014-03-04 12:15:01 -05:00
Novasys Ingenierie
c83a35f652 fpga: zynq: Correct fpga load when buf is not aligned
When ARCH_DMA_MINALIGN is greater than header size of the bit file, and buf is
not aligned, new_buf address became greater then buf_start address and the
load_word loop corrupts bit file data.

A work around is to decrease new_buf of ARCH_DMA_MINALIGN, it might corrupt data
before buf but permits to load correctly.

Signed-off-by: Stany MARCEL <smarcel@novasys-ingenierie.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2014-02-06 10:08:03 +01:00
Masahiro Yamada
7b6af41ef3 drivers: descend into sub directories only when it is necessary
- Descend into drivers/fpga/ only when CONFIG_FPGA=y
  - Descend into drivers/bios_emulator only when CONFIG_BIOSEMU=y

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2013-11-17 14:11:30 -05:00
Michal Simek
b129e8cfb0 fpga: zynqpl: Do not place bitstream below 1MB
DMA doesn't work when src is placed below 1MB limit.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Acked-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
2013-11-06 09:15:12 +01:00
Jagannadha Sutradharudu Teki
ec4b73f09c fpga: zynqpl: Add dcache flush support
Buffers must be cache and dma aligned.

Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2013-11-06 09:15:12 +01:00
Masahiro Yamada
710f1d3d5f drivers: convert makefiles to Kbuild style
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2013-10-31 13:26:01 -04:00
Wolfgang Denk
3765b3e7bd Coding Style cleanup: remove trailing white space
Signed-off-by: Wolfgang Denk <wd@denx.de>
2013-10-14 16:06:53 -04:00
Soren Brinkmann
5f93227ce0 fpga: zynqpl: Clear loopback mode during device init
Some versions of the Zynq first stage boot loader enable PCAP loopback
during boot regardless of whether or not the boot image includes PL
configuration. This behavior only appears in certain boot modes (notably
QSPI boot). Attempting to configure the PL with the loopback bit set
will result in timeouts and will prevent successful configuration.

In order to avoid this problem, and to avoid dependency on the version
of the FSBL used to boot the system, ensure that the loopback enable bit
is cleared when loading the driver.

Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2013-08-12 08:52:01 +02:00
Michal Simek
fd2b10b6d6 fpga: zynqpl: Add support for zc7100 device.
- Add support for zc7100 device.
- FPGA programming on few of the SOC(zc7100) takes more
  than 1sec, hence increased the program time by 4sec to
  sync' all soc's.

Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2013-08-12 08:01:50 +02:00
Wolfgang Denk
1a4596601f Add GPL-2.0+ SPDX-License-Identifier to source files
Signed-off-by: Wolfgang Denk <wd@denx.de>
[trini: Fixup common/cmd_io.c]
Signed-off-by: Tom Rini <trini@ti.com>
2013-07-24 09:44:38 -04:00
Michal Simek
6631db4773 fpga: Check device name against bitstream name
Ensure that wrong bitstream won't be loaded
to current device.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Tom Rini <trini@ti.com>
2013-05-06 10:41:25 +02:00
Michal Simek
d5dae85f23 fpga: zynq: Add support for loading bitstream
Devcfg device requires to load bitstream in binary format.
But u-boot also has an option for loading bitstream in bit
format. Let's handle both cases by zynqpl driver.
Also add suport for loading partial bitstreams.

The first driver version was done by:
Joe Hershberger <joe.hershberger@ni.com>

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Tom Rini <trini@ti.com>
2013-05-06 10:41:24 +02:00
Michal Simek
23f4bd756d fpga: Change the first parameter in fpga_loadbitstream
All fpga functions use devnum as int. Only fpga_loadbitstream
is using it as unsinged long dev.
This patch synchronize it.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Tom Rini <trini@ti.com>
2013-05-06 10:41:20 +02:00
Michal Simek
52c2064476 cmd: fpga: Move fpga_loadbitstream to fpga.c
In bitstream decoding you can directly check device
which you want to load and in fpga.c are fpga_validate
and fpga_dev_info functions which should be used for it.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Tom Rini <trini@ti.com>
2013-05-06 10:41:19 +02:00
Michal Simek
ee976c1b03 fpga: Fix debug message compilation error
CONFIG_FPGA in past was a bitfield where bits
were use for vendor identification.

This fix should be the part of this commit:
"Improve configuration of FPGA subsystem"
(sha1: 0133502e39)

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Tom Rini <trini@ti.com>
2013-05-06 10:41:17 +02:00
Michal Simek
f6555d90c1 fpga: Clean coding style
No functional changes.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Tom Rini <trini@ti.com>
2013-05-06 10:40:53 +02:00
York Sun
472d546054 Consolidate bool type
'bool' is defined in random places. This patch consolidates them into a
single header file include/linux/types.h, using stdbool.h introduced in C99.

All other #define, typedef and enum are removed. They are all consistent with
true = 1, false = 0.

Replace FALSE, False with false. Replace TRUE, True with true.
Skip *.py, *.php, lib/* files.

Signed-off-by: York Sun <yorksun@freescale.com>
2013-04-01 16:33:52 -04:00
Stephan Gatzka
a99c040c33 FPGA: Cyclon II: Correctly reset the FPGA before configuration
Deassert the CONFIG pin before asserting it again. This assures that the
FPGA will be resetted and therefore configuration will be correctly
enabled.

This is also already done on other FPGA's, e.g. Stratix.

Signed-off-by: Stephan Gatzka <stephan.gatzka@hbm.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2012-10-29 14:21:20 -07:00
Thomas Weber
b199c6e2d7 Remove execute permissions from source files
Signed-off-by: Thomas Weber <weber@corscience.de>
2012-03-04 21:56:15 +01:00
Stefano Babic
33e1e01820 fpga: Spartan-3: let print the progress if configured
CONFIG_SYS_FPGA_PROG_FEEDBACK was already introduced to print
the current status of FPGA loading - an undef in the code made this
CONFIG_ useless.

Signed-off-by: Stefano Babic <sbabic@denx.de>
2012-01-05 16:20:12 +01:00
Stefano Babic
69de63e1f2 FPGA: drivers/fpga/ivm_core.c: GCC4.6 fix build warnings
Fix:
ivm_core.c: In function 'ispVMLCOUNT':
ivm_core.c:2105:16: warning: unused variable 'usByte'

Signed-off-by: Stefano Babic <sbabic@denx.de>
CC: Wolfgang Denk <wd@denx.de>
2011-11-16 20:49:40 +01:00
Marek Vasut
b89c708bb7 GCC4.6: Squash warnings in lattice.c
lattice.c:319:4: warning: format '%x' expects type 'unsigned int', but argument
3 has type 'const char *'
lattice.c:319:4: warning: format '%x' expects type 'unsigned int', but argument
4 has type 'long unsigned int'

Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Cc: Mike Frysinger <vapier@gentoo.org>
2011-10-27 23:54:07 +02:00
Wolfgang Denk
fb2d6efbf2 FPGA: constify Lattice FPGA code
The Lattice code was missed by commit e6a857d "fpga: constify to fix
build warning" resulting in such warnings:

fpga.c: In function 'fpga_load':
fpga.c:238: warning: passing argument 2 of 'lattice_load' discards qualifiers from pointer target type
fpga.c: In function 'fpga_dump':
fpga.c:278: warning: passing argument 2 of 'lattice_dump' discards qualifiers from pointer target type

Signed-off-by: Wolfgang Denk <wd@denx.de>
cc: Stefano Babic <sbabic@denx.de>
2011-09-05 11:41:42 +02:00
Wolfgang Denk
e6a857da74 fpga: constify to fix build warning
Fix compiler warning:

cmd_fpga.c:318: warning: passing argument 3 of 'fit_image_get_data'
from incompatible pointer type

Adding the needed 'const' here entails a whole bunch of additonal
changes all over the FPGA code.

Signed-off-by: Wolfgang Denk <wd@denx.de>
Cc: Andre Schwarz <andre.schwarz@matrix-vision.de>
Cc: Murray Jensen <Murray.Jensen@csiro.au>
Acked-by: Andre Schwarz<andre.schwarz@matrix-vision.de>
2011-08-01 15:19:40 +02:00
Michael Jones
ee44fb298d fpga: support FPP Cyclone configuration
Support FPGAs which use Fast Passive Parallel configuration

Signed-off-by: Michael Jones <michael.jones@matrix-vision.de>
2011-07-28 16:47:11 +02:00
Michael Jones
f18361b9a8 altera: fix printf typo
Signed-off-by: Michael Jones <michael.jones@matrix-vision.de>
Acked-by: Detlev Zundel <dzu@denx.de>
2011-07-28 16:33:25 +02:00
Wolfgang Wegner
b0bc8b70ff add Xilinx_abort_fn to Xilinx_Spartan3_Slave_Serial_fns
Currently the hardware was left in an undefined state in case Spartan3
serial load failed. This patch adds Xilinx_abort_fn to give the board
a possibility to clean up in this case.

Signed-off-by: Wolfgang Wegner <w.wegner@astro-kom.de>
2010-11-30 21:59:21 +01:00
Sebastien Carlier
6d8962e814 Switch from archive libraries to partial linking
Before this commit, weak symbols were not overridden by non-weak symbols
found in archive libraries when linking with recent versions of
binutils.  As stated in the System V ABI, "the link editor does not
extract archive members to resolve undefined weak symbols".

This commit changes all Makefiles to use partial linking (ld -r) instead
of creating library archives, which forces all symbols to participate in
linking, allowing non-weak symbols to override weak symbols as intended.
This approach is also used by Linux, from which the gmake function
cmd_link_o_target (defined in config.mk and used in all Makefiles) is
inspired.

The name of each former library archive is preserved except for
extensions which change from ".a" to ".o".  This commit updates
references accordingly where needed, in particular in some linker
scripts.

This commit reveals board configurations that exclude some features but
include source files that depend these disabled features in the build,
resulting in undefined symbols.  Known such cases include:
- disabling CMD_NET but not CMD_NFS;
- enabling CONFIG_OF_LIBFDT but not CONFIG_QE.

Signed-off-by: Sebastien Carlier <sebastien.carlier@gmail.com>
2010-11-17 21:02:18 +01:00
Wolfgang Denk
071bc92330 Coding Style cleanup
Signed-off-by: Wolfgang Denk <wd@denx.de>
2010-10-27 22:48:30 +02:00
Wolfgang Denk
439f6f7ec1 FPGA: fix support for non-Lattice devices
Commit 3b8ac464 "FPGA: add support for downloading Lattice bitstream"
added support for Lattice devices, but failed to add #ifdef's that are
needed when building for non-Lattice devices, which results in build
failures like these:

Configuring for GEN860T board...
drivers/fpga/libfpga.a(fpga.o): In function `fpga_dev_info':
/home/wd/git/u-boot/work/drivers/fpga/fpga.c:145: undefined reference to `lattice_info'
drivers/fpga/libfpga.a(fpga.o): In function `fpga_dump':
/home/wd/git/u-boot/work/drivers/fpga/fpga.c:269: undefined reference to `lattice_dump'
drivers/fpga/libfpga.a(fpga.o): In function `fpga_load':
/home/wd/git/u-boot/work/drivers/fpga/fpga.c:233: undefined reference to `lattice_load'
make: *** [u-boot] Error 1

Add the missing code.

Signed-off-by: Wolfgang Denk <wd@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
2010-10-18 21:32:14 +02:00
Stefano Babic
3b8ac464f2 FPGA: add support for downloading Lattice bitstream
The patch adds support to load a Lattice's bitstream
image (called VME file) into a Lattice FPGA. The code
containing the state machine delivered as part of
Lattice's ispVMtools is integrated.

The FPGA is programmed using the JTAG interface. The
board maintainer must provide accessors to drive the
JTAG signals TCK, TMS, TDI and to get the value of the
input signal TDO.

Signed-off-by: Stefano Babic <sbabic@denx.de>
2010-10-13 18:09:31 +02:00
Wolfgang Wegner
89083346d0 add block write function to spartan3 slave serial load
Using seperate function calls for each bit-bang of slave serial
load can be painfully slow. This patch adds the possibility to
supply a block write function that loads the complete block of
data in one call (like it can already be done with Altera FPGAs).
On an MCF5373L (240 MHz) loading an XC3S4000 this reduces the load
time from around 15 seconds to around 3 seconds

Signed-off-by: Wolfgang Wegner <w.wegner at astro-kom.de>
2010-03-24 11:08:43 -05:00
Peter Tyser
6385b28116 fpga: Remove relocation fixups
PPC boards are the only users of the current FPGA code which is littered
with manual relocation fixups.  Now that proper relocation is supported
for PPC boards, remove FPGA manual relocation.

Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
2009-10-03 10:17:56 +02:00
Matthias Fuchs
670cbde8da fpga: Fix Spartan III FPGA booting
This patch does some minor fixing of the Xilinx Spartan III
FPGA boot code:

- Fixed call order of post configuration callback and
  success message printing (result of copy-paste?)
- remove obsolete comment
- minor coding style cleanup

Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
2009-02-21 22:52:44 +01:00
Matthias Fuchs
3818b67764 fpga: Fix Spartan II FPGA booting
This patch does some minor fixing of the Xilinx Spartan II
FPGA boot code:

- Fixed call order of post configuration callback and
  success message printing (result of copy-paste?)
- relocate post configuration callback only when it
  is implemented
- remove obsolete comment
- minor coding style cleanup

Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
2009-02-21 22:52:43 +01:00
Jean-Christophe PLAGNIOL-VILLARD
c8aa7dfc18 FPGA: move fpga drivers to drivers/fpga
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
2008-12-05 22:41:33 +01:00