Commit graph

4149 commits

Author SHA1 Message Date
Tom Rini
7a1a01c602 For 2020.10
-----------
 
 - mx6: SOCs user selectable
        Fix for imx6q_logic
        Some DM conversion
 - mx7: introduce secondary boot device
 
 Travis: https://travis-ci.org/github/sbabic/u-boot-imx/builds/720918010
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Merge tag 'u-boot-imx-20200825' of https://gitlab.denx.de/u-boot/custodians/u-boot-imx

For 2020.10
-----------

- mx6: SOCs user selectable
       Fix for imx6q_logic
       Some DM conversion
- mx7: introduce secondary boot device

Travis: https://travis-ci.org/github/sbabic/u-boot-imx/builds/720918010

Signed-off-by: Tom Rini <trini@konsulko.com>
2020-08-25 23:12:43 -04:00
Tom Rini
9f9ecd3e4d Merge https://gitlab.denx.de/u-boot/custodians/u-boot-marvell
- Add basic Marvell/Cavium OcteonTX/TX2 support (Suneel)
- Infrastructure changes to PCI uclass to support these SoC's (Suneel)
- Add PCI, MMC & watchdog driver drivers for OcteonTX/TX2 (Suneel)
- Increase CONFIG_SYS_MALLOC_F_LEN for qemu-x86 (Stefan)
2020-08-25 13:38:29 -04:00
Suneel Garapati
04cd0a0fa0 arm: octeontx2: Add headers for OcteonTX2
Signed-off-by: Suneel Garapati <sgarapati@marvell.com>
2020-08-25 08:01:16 +02:00
Suneel Garapati
387d321add arm: octeontx: Add headers for OcteonTX
Signed-off-by: Suneel Garapati <sgarapati@marvell.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2020-08-25 08:01:16 +02:00
Suneel Garapati
c2f45b6588 arm: include/asm/io.h: Add 64bit clrbits and setbits helpers
Add 64bit API for clrbits and setbits.

Signed-off-by: Suneel Garapati <sgarapati@marvell.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2020-08-25 08:01:16 +02:00
Usama Arif
565add124d board: armltd: Add support for Total Compute platform
Total Compute is based on ARM architecture and has
the following features enabled in u-boot:
- PL011 UART
- PL180 MMC
- NOR Flash
- FIT image with Signature
- AVB

Signed-off-by: Usama Arif <usama.arif@arm.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2020-08-24 14:11:31 -04:00
Marek Vasut
af50d92ae7 ARM: imx: ddr: Add deskew register programming
Fill is code for programming the DDR_PHY_CMD_DESKEW_CONx registers,
which are optional, but can be used to fill in the byte lane delays.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: NXP i.MX U-Boot Team <uboot-imx@nxp.com>
Cc: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
2020-08-17 17:55:49 +02:00
Marek Vasut
5ec83561c4 ARM: imx: Add support for switching primary/secondary boot mode to bmode
The i.MX6/i.MX7 is capable of booting a secondary "redundant" system
image in case the primary one is corrupted. The user can force this
boot mode as well by explicitly setting SRC GPR10 bit 30. This can be
potentially useful when upgrading the bootloader itself. Expose this
functionality to the user.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: NXP i.MX U-Boot Team <uboot-imx@nxp.com>
Cc: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
Reviewed-by: Stefano Babic <sbabic@denx.de>
2020-08-17 17:54:01 +02:00
Marek Vasut
c72372d38c ARM: imx: Add bmode support for iMX7
Add the basic differentiation between i.MX6 and i.MX7 into the bmode
command, the mechanism really works almost the same on both platforms.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: NXP i.MX U-Boot Team <uboot-imx@nxp.com>
Cc: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
2020-08-17 17:53:55 +02:00
Oleksandr Andrushchenko
486544161f xen: Port Xen hypervisor related code from mini-os
Port hypervisor related code from Mini-OS. This is referencing the code
of Mini-OS from [1] by Huang Shijie and Volodymyr Babchuk which is for
ARM64.
Update essential arch code to support required bit operations, memory
barriers etc.

Copyright for the bits ported belong to at least the following authors,
please see related files for details:

Copyright (c) 2002-2003, K A Fraser
Copyright (c) 2005, Grzegorz Milos, gm281@cam.ac.uk,Intel Research Cambridge
Copyright (c) 2014, Karim Allah Ahmed <karim.allah.ahmed@gmail.com>

[1] - https://github.com/zyzii/mini-os.git

Signed-off-by: Oleksandr Andrushchenko <oleksandr_andrushchenko@epam.com>
Signed-off-by: Anastasiia Lukianenko <anastasiia_lukianenko@epam.com>
[trini: Drop wmb() from musb-net/linux-compat.h now]
Signed-off-by: Tom Rini <trini@konsulko.com>
2020-08-14 15:18:30 -04:00
Andrii Anisov
770a8eef3e board: Introduce xenguest_arm64 board
Introduce a minimal Xen guest board running as a virtual
machine under Xen Project's hypervisor [1], [2].

Part of the code is ported from Xen mini-os and also uses
work initially done by different authors from NXP: please see
relevant files for their copyrights.

[1] https://xenbits.xen.org
[2] https://wiki.xenproject.org/

Signed-off-by: Andrii Anisov <andrii_anisov@epam.com>
Signed-off-by: Oleksandr Andrushchenko <oleksandr_andrushchenko@epam.com>
Signed-off-by: Anastasiia Lukianenko <anastasiia_lukianenko@epam.com>
2020-08-14 15:18:27 -04:00
Chia-Wei, Wang
98ef128b56 include/configs: aspeed: Remove hardcoded variables
The hardcoded platform variables such as DRAM base address are not
common to Aspeed SoCs AST24xx/AST25xx/AST26xx. This patch replaces
those hardcoded with macros defined in a newly added header, where
the basic SoC HW information are assigned accordingly.

Signed-off-by: Chia-Wei, Wang <chiawei_wang@aspeedtech.com>
2020-08-14 09:46:40 -04:00
Simon Glass
153f269ebe mediatek: Drop dm.h header file
This header file should not be included in other header files. Remove it
and use a forward declaration instead.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-08-03 22:19:54 -04:00
Rayagonda Kokatanur
2ae7adc659 arch: arm: use dt and UCLASS_SYSCON to get gic lpi details
Use device tree and UCLASS_SYSCON driver to get
Generic Interrupt Controller (GIC) lpi address and
maximum GIC redistributors count.

Also update Kconfig to select REGMAP and SYSCON when
GIC_V3_ITS is enabled.

Signed-off-by: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2020-07-29 10:37:11 -04:00
Rayagonda Kokatanur
912fe3768f gpio: do not include <asm/arch/gpio.h> on TARGET_BCMNS3
As no gpio.h is defined for this architecture, to avoid
compilation failure, do not include <asm/arch/gpio.h> for
arch bcmns3.

Signed-off-by: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2020-07-29 10:37:11 -04:00
Abhishek Shah
ef7192e404 board: ns3: add api to save boot parameters passed from BL31
Add API to save boot parameters passed from BL31

Use assembly implementation of save_boot_params instead of c function.
Because generally ATF does not set up SP_EL2 on exiting.
Thus, usage of a C function immediately after exiting with no stack
setup done by ATF explicitly, may cause SP_EL2 to be not sane,
which in turn causes a crash if this boot was not lucky to get
an SP_EL2 in valid range. Replace C implementation with assembly one
which does not use stack this early, and let u-boot to set up its stack
later.

Signed-off-by: Abhishek Shah <abhishek.shah@broadcom.com>
Signed-off-by: Rajesh Ravi <rajesh.ravi@broadcom.com>
Signed-off-by: Vladimir Olovyannikov <vladimir.olovyannikov@broadcom.com>
Signed-off-by: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2020-07-29 10:13:41 -04:00
Ard Biesheuvel
6744ace5b3 arm: enable allocate-on-read for LPAE's DCACHE_WRITEBACK/_WRITETHROUGH
The LPAE versions of DCACHE_WRITEBACK and DCACHE_WRITETHROUGH are currently
defined as no-allocate for both reads and writes, which deviates from the
non-LPAE definition, and mostly defeats the purpose of enabling the caches
in the first place.

So align LPAE with !LPAE, and enable allocate-on-read for both. And while
at it, add some clarification about the meaning of the chosen values.

Signed-off-by: Ard Biesheuvel <ardb@kernel.org>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
2020-07-29 08:43:40 -04:00
Michael Walle
308deab9b1 armv8: layerscape: clean exported symbols in spintable.S
Add a new variable secondary_boot_code_start, which holds a pointer to
the start of the spin table code. This will help to relocate the code
section. While at it, move the size variable from the end to the
beginning so there is a common section for the variables. Remove any
other symbols.

Signed-off-by: Michael Walle <michael@walle.cc>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-07-27 14:16:28 +05:30
Michael Walle
c31ac97f96 armv8: layerscape: remove determine_mp_bootpg()
Only the PowerPC architecture needs this function. Remove it.

Signed-off-by: Michael Walle <michael@walle.cc>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-07-27 14:16:27 +05:30
Michael Walle
3d3fe8b12d armv8: layerscape: properly use CPU_RELEASE_ADDR
The generic armv8 code already has support to bring up the secondary
cores. Thus, don't hardcode the jump in the layerscape lowlevel_init to
the spin table code; instead just return early and let the common armv8
code handle the jump. This way we can actually use the CPU_RELEASE_ADDR
feature.

Signed-off-by: Michael Walle <michael@walle.cc>
[Rebased, Removed kontron_sl28.h change as file does not exist]
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-07-27 14:16:27 +05:30
hui.song
02decd4e0c dm: armv8: gpio: include <asm/arch/gpio.h> for fsl-layerscape
Enable the gpio feature on fsl-layerscape platform.

Signed-off-by: hui.song <hui.song_1@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-07-27 14:16:27 +05:30
hui.song
08333fa50b armv8: gpio: add gpio feature
add one struct mpc8xxx_gpio_plat to enable gpio feature.

Signed-off-by: hui.song <hui.song_1@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-07-27 14:16:26 +05:30
Jagan Teki
e230c579a3 rockchip: Separate the reset cause from display cpuinfo
reset cause is a generic functionality based on the soc
cru registers in rockchip. This can be used for printing
the cause of reset in cpuinfo or some other place where
reset cause is needed. 

Other than cpuinfo, reset cause can also be using during
bootcount for checking the specific reset cause and glow
the led based on the reset cause.

So, let's separate the reset cause code from cpuinfo, and
add a check to build it for rk3399, rk3288 since these two
soc are supporting reset cause as of now.

Tested-by: Suniel Mahesh <sunil@amarulasolutions.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2020-07-22 20:55:13 +08:00
Jagan Teki
88132e0a28 rockchip: Don't clear the reset status reg
reset reason can be used several stages of U-Boot bootloader
like SPL, U-Boot proper based on the requirements.

Clearing the status register end of get_reset_cause will end
up showing the wrong reset cause when it read the second time.
For example, if board resets, SPL reads the reset status as
RST whereas U-Boot proper reads the status as POR.

However, based on the latest testing clearing reset status
won't be required for determine the last reset cause or
following resets.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2020-07-22 20:55:13 +08:00
Jagan Teki
c60d1c4e17 rockchip: Add rk3288 SoC detection helper
Rockchip SoC's has a new revision chip for rk3288 SoCs.

RK3288 has a new revision chip called RK3288W which is similar
but different hclk_vio clock and fixed OHCI host.

Add common Rockchip SoC detection helper to support this rk3288w
detection.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2020-07-22 20:55:13 +08:00
Kever Yang
b32858ca51 rockchip: ram: fix debug funcfion define when RAM_ROCKCHIP_DEBUG not set
The empty function define should not be in the header file, or else the
build will error with function multi definition after CONFIG_RAM_ROCKCHIP_DEBUG
is disabled.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2020-07-22 20:22:33 +08:00
Masahiro Yamada
b75d8dc564 treewide: convert bd_t to struct bd_info by coccinelle
The Linux coding style guide (Documentation/process/coding-style.rst)
clearly says:

  It's a **mistake** to use typedef for structures and pointers.

Besides, using typedef for structures is annoying when you try to make
headers self-contained.

Let's say you have the following function declaration in a header:

  void foo(bd_t *bd);

This is not self-contained since bd_t is not defined.

To tell the compiler what 'bd_t' is, you need to include <asm/u-boot.h>

  #include <asm/u-boot.h>
  void foo(bd_t *bd);

Then, the include direcective pulls in more bloat needlessly.

If you use 'struct bd_info' instead, it is enough to put a forward
declaration as follows:

  struct bd_info;
  void foo(struct bd_info *bd);

Right, typedef'ing bd_t is a mistake.

I used coccinelle to generate this commit.

The semantic patch that makes this change is as follows:

  <smpl>
  @@
  typedef bd_t;
  @@
  -bd_t
  +struct bd_info
  </smpl>

Signed-off-by: Masahiro Yamada <masahiroy@kernel.org>
2020-07-17 09:30:13 -04:00
Ye Li
dfbdaa66b7 misc: scu_api: Add SCFW API to get the index of boot container set
Add SCFW API sc_misc_get_boot_container to get current boot container
set index.
The index value returns 1 for primary container set, 2 for secondary
container set.

Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
2020-07-16 11:19:50 +02:00
Peng Fan
7a42bf0489 imx8m: power down fused cores
For non-Quad SoCs, the fused cpu cores could be powered down in SPL
to save power.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2020-07-14 15:23:47 +08:00
Ye Li
d1eee7eed9 imx8mp: Add fused parts support
iMX8MP has 6 fused parts in each qualification tier, with core, VPU,
ISP, NPU or DSP fused respectively.

The configuration tables for enabled modules:
MIMX8ML8DVNLZAA          Quad Core, VPU, NPU, ISP, DSP
MIMX8ML7DVNLZAA          Quad Core, NPU, ISP
MIMX8ML6DVNLZAA          Quad Core, VPU, ISP
MIMX8ML5DVNLZAA          Quad Core, VPU
MIMX8ML4DVNLZAA          Quad Lite
MIMX8ML3DVNLZAA          Dual Core, VPU, NPU, ISP, DSP

Add the support in U-Boot

Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2020-07-14 15:23:47 +08:00
Oliver Chen
b335966958 drivers: ddr: imx Workaround for i.MX8M DDRPHY rank to rank issue
Add logic to automatically update umctl2's setting based
on phy training CDD value for rank to rank space issue

Acked-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Oliver Chen <Oliver.Chen@nxp.com>
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2020-07-14 15:23:46 +08:00
Sherry Sun
f3acb02386 drivers: ddr: imx8mp: Add inline ECC feature support
the DRAM Controller in i.MX8MP will support a feature called "Inline ECC".
This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and
DDR3L). When this feature is enabled by software, the DRAM Controller
reserves 12.5% of DRAM capacity for ECC information, and presents only
the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to
the rest of the SoC.
The DRAM memory can be divided into 8 regions so that if a use case only
requires ECC protection on a subset of memory, then only that subset of
memory need support inline ECC. If this occurs, then there is no
performance penalty accessing the non-ECC-protected memory (no need to
access ECC for this portion of the memory map). This is all configured
with the DRAM Controller.

Signed-off-by: Sherry Sun <sherry.sun@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2020-07-14 15:23:46 +08:00
Marek Szyprowski
d877f8fd0f arm: provide a function for boards init code to modify MMU virtual-physical map
Provide function for setting arbitrary virtual-physical MMU mapping
and cache settings for the given region.

Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2020-07-10 14:10:43 -04:00
Marek Szyprowski
f5a9fcc602 arm: update comments to the common style
Update the comments in include/asm/system.h to the common style.

Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2020-07-10 14:10:43 -04:00
Heinrich Schuchardt
22a4e006be arm: use correct argument size of special registers
Compiling with clang on ARMv8 shows errors like:

./arch/arm/include/asm/system.h:162:32: note: use constraint modifier "w"
                asm volatile("msr sctlr_el1, %0" : : "r" (val) : "cc");
                                             ^~
                                             %w0

These errors are due to using an incorrect size for the variables used
for writing to and reading from special registers which have 64 bits on
ARMv8.

Mask off reserved bits when reading the exception level.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2020-07-07 18:23:48 -04:00
Heinrich Schuchardt
b87d8d6a0e arm: remove outdated comment concerning -ffixed-x18
Clang 9 supports -ffixed-x18.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
2020-07-07 18:23:48 -04:00
Amit Singh Tomar
3c5c4ee35f net: designware: s700: Add glue code for S700 mac
This patchs adds glue logic to enable designware mac present on
Action Semi based S700 SoC, Configures SoC specific bits.

Undocumented bit that programs the PHY interface select register
comes from vendor source.

It has been tested on Cubieboard7-lite based on S700 SoC.

Signed-off-by: Amit Singh Tomar <amittomer25@gmail.com>
2020-07-07 17:11:58 -04:00
Amit Singh Tomar
3a21734605 clk: actions: Add Ethernet clocks
This commit adds clocks needed for ethernet operations for
Actions OWL family of SoCs (S700 and S900).

Signed-off-by: Amit Singh Tomar <amittomer25@gmail.com>
2020-07-07 16:09:22 -04:00
Marek Vasut
cb82ee25f7 ARM: imx: ddr: Fill in missing DDRC ZQCTLx on i.MX7
The iMX7 defines further DDRC ZQCTLx registers, however those were
thus far missing from the list of registers and not programmed. On
systems with LPDDR2 or DDR3, those registers must be programmed with
correct values, otherwise the DRAM may not work. However, existing
systems which worked without programming these registers before are
now setting those registers to 0, which is the default value, so no
functional change there.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: NXP i.MX U-Boot Team <uboot-imx@nxp.com>
Cc: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
2020-06-22 17:44:06 +02:00
Marek Vasut
0e06d63d19 ARM: imx: ddr: Add missing PHY reset
The iMX7D RM 9.2.4.9.3 Power removal flow Table 9-11. Re-enabling power
explicitly says both the DDR controller and the PHY must be reset in the
correct sequence. Currently the code only resets the controller. This
leads to a misbehavior where the system brings the DRAM up after reboot,
but the DRAM is unstable. Add the missing reset.

The easiest way to trigger this is by triggering WDT without having the
WDT assert WDOG_B signal, i.e. mw.w 0x30280000 0x25 .

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: NXP i.MX U-Boot Team <uboot-imx@nxp.com>
Cc: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
2020-06-08 10:42:54 +02:00
Tom Rini
1b6ae82a5a Pull request for UEFI sub-system for efi-2020-07-rc4
This patch series addresses the following issues:
 
 * allow compiling with clang
 * add missing function descriptions to the HTML documentation
 * simplify the validation of UEFI images
 * validate load options in the UEFI boot manager
 
 In a preparatory patch a structure definition is moved.
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Merge tag 'efi-2020-07-rc4' of https://gitlab.denx.de/u-boot/custodians/u-boot-efi

Pull request for UEFI sub-system for efi-2020-07-rc4

This patch series addresses the following issues:

* allow compiling with clang
* add missing function descriptions to the HTML documentation
* simplify the validation of UEFI images
* validate load options in the UEFI boot manager

In a preparatory patch a structure definition is moved.
2020-06-03 14:10:03 -04:00
Heinrich Schuchardt
4f7dc5f608 efi_loader: allow compiling with clang
On ARM systems gd is stored in register r9 or x18. When compiling with
clang gd is defined as a macro calling function gd_ptr(). So we can not
make assignments to gd.

In the UEFI sub-system we need to save gd when leaving to UEFI binaries and
have to restore gd when reentering U-Boot.

Define a new function set_gd() for setting gd and use it in the UEFI
sub-system.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Tested-by: Tom Rini <trini@konsulko.com>
2020-06-03 17:19:17 +02:00
Masahiro Yamada
9f8aa0fbee ARM: add psci_arch_init() declaration for CONFIG_ARMV7_PSCI
arch/arm/include/asm/system.h declares psci_arch_init(), but it is
surrounded by #ifdef CONFIG_ARMV8_PSCI.

psci_arch_init() is called for CONFIG_ARMV7_PSCI too. Add the missing
function declaration.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2020-06-02 17:27:04 -04:00
Adam Ford
94ed66194f usb: ehci-omap: Add Support for DM_USB and OF_CONTROL
The omap3.dtsi file shows the usbhshost node with two sub-nodes
for ohci and ehci.  This patch file creates the usbhshost, and
pulls the portX-mode information.  It then locates the EHCI
sub-node, and initializes the EHCI controller with the info
pulled from the usbhshost node.

There is still more to do since there isn't an actual link
between the 'phys' reference and the corresponding phy driver,
and there is no nop-xceiv driver yet.

In the meantime, the older style reference to
CONFIG_OMAP_EHCI_PHYx_RESET_GPIO is still needed to pull
the phy out of reset until the phy driver is completed and the
phandle reference is made.

Signed-off-by: Adam Ford <aford173@gmail.com>
2020-05-22 15:22:35 +02:00
Tom Rini
b0b13f4114 Merge https://gitlab.denx.de/u-boot/custodians/u-boot-fsl-qoriq
- Add DM_ETH support for lx2160aqds, ls2080aqds, ls1088aqds
- QSI related fixes on ls1012a, ls2080a, ls1046a, ls1088a, ls1043a based
  platforms
- Bug-fixes/updtaes related to ls1046afrwy, fsl-mc, msi-map property
2020-05-20 08:46:56 -04:00
Kuldeep Singh
c93ad777b8 treewide: Remove unused FSL QSPI config options for Layerscape platforms
Some of these options are not used by the driver anymore and some of
them are obsolete as the information is gathered from the dt. Also
consolidating defines in common headers.

Signed-off-by: Frieder Schrempf <frieder.schrempf@kontron.de>
Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com>
Signed-off-by: Kuldeep Singh <kuldeep.singh@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-05-19 09:22:05 +05:30
Simon Glass
cd93d625fd common: Drop linux/bitops.h from common header
Move this uncommon header out of the common header.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-05-18 21:19:23 -04:00
Simon Glass
f09f1ecbe7 Use __ASSEMBLY__ as the assembly macros
Some places use __ASSEMBLER__ instead which does not work since the
Makefile does not define it. Fix them.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-05-18 21:19:23 -04:00
Simon Glass
f7ae49fc4f common: Drop log.h from common header
Move this header out of the common header.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-05-18 21:19:18 -04:00
Simon Glass
0914011310 command: Remove the cmd_tbl_t typedef
We should not use typedefs in U-Boot. They cannot be used as forward
declarations which means that header files must include the full header to
access them.

Drop the typedef and rename the struct to remove the _s suffix which is
now not useful.

This requires quite a few header-file additions.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-05-18 18:36:55 -04:00
Simon Glass
90526e9fba common: Drop net.h from common header
Move this header out of the common header. Network support is used in
quite a few places but it still does not warrant blanket inclusion.

Note that this net.h header itself has quite a lot in it. It could be
split into the driver-mode support, functions, structures, checksumming,
etc.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-05-18 17:33:31 -04:00
Simon Glass
c3dc39a2f8 arm: Don't include common.h in header files
It is bad practice to include common.h in other header files since it can
bring in any number of superfluous definitions. It implies that some C
files don't include it and thus may be missing CONFIG options that are set
up by that file. The C files should include these themselves.

Update some header files in arch/arm to drop this.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-05-18 14:54:24 -04:00
Peng Fan
ed5b253d0e imx: imx8qm/qxp: check whether m4 partition booted
Add code to check m4 partition booted or not, we will use this
to runtime set device tree file that passed to Linux Kernel.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2020-05-10 20:55:20 +02:00
Peng Fan
231401de2e imx: imx8qm/imx8qxp: Power down the resources before SPL jump to u-boot
Make sure that all devices that are powered up by SPL are powered down
before entering into the u-boot. Otherwise the subsystem/device will
never be powered down by SCFW, due to SPL and u-boot are in different
partitions.

Benefiting from power domain driver, this patch implements the function
"imx8_power_off_pd_devices" to power off all active devices.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2020-05-10 20:55:20 +02:00
Han Xu
214b7d534d cmd: nandbcb: Reconstruct the nandbcb tool for all platforms
The original nandbcb tool was designed for imx6 only, when trying to
leverage it to replace the kobs-ng tool, we found the design is not
friendly for supporting all platforms. To support all iMX6/7/8 platforms
and for easy further maintain, I reconstruct the structure of the tool.

The main changes including:

1. Use platform_data to determine the logic branches rather than simply
   use SOC name.
2. More data structures as parameter for functions.
3. Global variables to define the FCB/DBBT/FW locations.
4. Implement the kobs-ng default 4 FCB/4 DBBT/2 FW layout.
5. Support Hamming coding/ 40bit BCH/ 62bit BCH coding FCB.
6. Dump and compare all written FCB/DBBT to verify data integrity.

The tool has been verified on iMX6Q/DL, 6SX, 7D, 6ULL, iMX8QX, iMX8MM.

Signed-off-by: Han Xu <han.xu@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2020-05-10 20:55:20 +02:00
Peng Fan
8c0a1c6de8 imx8: power: Add PD device lookup interface to power domain uclass
Add power_domain_lookup_name interface to power domain uclass to find
a power domain device by its DTB node name, not using its associated
client device.

Through this interface, we can operate the power domain devices directly.
This is needed for non-DM drivers.

Modified from Ye's NXP downstream patch

only for legacy imx8 power domain driver, since we have not migrated
to use new power domain driver.

Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2020-05-10 20:55:20 +02:00
Peng Fan
39320e7256 mtd: nand: support GPMI NAND driver for i.MX8
enable the GPMI NAND driver for i.MX8, i.MX8 use similar controller as
i.MX8M

- register definition for i.mx8
- DMA structure must be 32bit address

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2020-05-10 20:55:20 +02:00
Han Xu
17282f45ab mtd: mxs_nand: fix the gf_13/14 definition issue
gf_13/14 mask was not set correctly in register definition.

Signed-off-by: Han Xu <han.xu@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2020-05-10 20:55:20 +02:00
Ye Li
ff99041b3b mxs_nand: Add support for i.MX8M
Update the gpmi/apbh_dma/bch drivers and relevant registers for i.MX8M.

Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2020-05-10 20:55:20 +02:00
Peng Fan
29f40c07e7 nand: mxs: correct bitflip for erased NAND page
This patch is a porting of
http://git.freescale.com/git/cgit.cgi/imx/linux-2.6-imx.git/
commit/?h=imx_4.1.15_1.0.0_ga&id=e4dacc44d22e9474ec456cb330df525cd805ea38
"
i.MX6QP and i.MX7D BCH module integrated a new feature to detect the
bitflip number for erased NAND page. So for these two platform, set the
erase threshold to gf/2 and if bitflip detected, GPMI driver will
correct the data to all 0xFF.

Also updated the imx6qp dts file to ditinguish the GPMI module for i.MX6Q
with the one for i.MX6QP.
"

In this patch, i.MX6UL is added and threshold changed to use ecc_strength.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2020-05-10 20:55:20 +02:00
Peng Fan
ef56281cf3 imx: regs: add more fuse bank structure
Add more fuse bank structure for use.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2020-05-10 20:55:20 +02:00
Ye Li
9d4194f179 fec: Move imx_get_mac_from_fuse declare to imx file
imx_get_mac_from_fuse is used to load MAC address from fuse. On imx8mp,
we have two different ENET controllers and both need to call this
function. So decouple its declare from fec driver.

Reviewed-by: Fugang Duan <fugang.duan@nxp.com>
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2020-05-10 20:55:20 +02:00
Peng Fan
3c42c0f673 imx: add module fuse support
There are different parts from one SoC. Take i.MX6ULL for example,
some part might not have ENET, some might have; some might not have
USB, some might have. The information could be got from OCOTP,
to make one image support the different parts, we need runtime
disable linux kernel dts node and uboot driver probe if the
corresponding module not exists in the part.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2020-05-10 13:21:13 +02:00
Stefano Babic
b77d0292ca Merge branch 'master' of git://git.denx.de/u-boot 2020-05-10 13:03:56 +02:00
Tom Rini
143414c03f i.MX for 2020.07
----------------
 
 - imxrt: fix LCD clock, fix doc
 - new board: Coral Dev
 - imx8: enable Cache in SPL. SNVS, update SCFW API
 - imx8MM: fix reset, 8MQ quand and QuadLite, CPU speed grading
 - MX6ULL : is_imx6ull to include i.MX6ULZ
 - Net: add config to enable TXC delay
 
 Travis: https://travis-ci.org/github/sbabic/u-boot-imx/builds/682033914
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Merge tag 'u-boot-imx-20200502' of https://gitlab.denx.de/u-boot/custodians/u-boot-imx

i.MX for 2020.07
----------------

- imxrt: fix LCD clock, fix doc
- new board: Coral Dev
- imx8: enable Cache in SPL. SNVS, update SCFW API
- imx8MM: fix reset, 8MQ quand and QuadLite, CPU speed grading
- MX6ULL : is_imx6ull to include i.MX6ULZ
- Net: add config to enable TXC delay

Travis: https://travis-ci.org/github/sbabic/u-boot-imx/builds/682033914
2020-05-04 09:29:42 -04:00
Frank Li
8142a97d54 cpu: imx8: show RevC instead of Rev? at boot log
Add REVC informaiton.

Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Frank Li <Frank.Li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2020-05-03 15:45:49 +02:00
Patrick Delaunay
2e8d68e241 arm: caches: add DCACHE_DEFAULT_OPTION
Add the new flags DCACHE_DEFAULT_OPTION to define the default
option to use according the compilation flags
CONFIG_SYS_ARM_CACHE_*.

This new compilation flag allows to simplify dram_bank_mmu_setup()
and can be used as third parameter (option=dcache option to select)
of mmu_set_region_dcache_behaviour function.

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2020-05-01 11:34:01 -04:00
Patrick Delaunay
f8dc7f2f18 configs: migrate CONFIG_SYS_ARM_CACHE_* in Kconfig
Move CONFIG_SYS_ARM_CACHE_WRITETHROUGH and
CONFIG_SYS_ARM_CACHE_WRITEALLOC into Kconfig done by moveconfig.py.

Kconfig uses a choice between the 3 values supported in U-Boot,
including the new configuration CONFIG_SYS_ARM_CACHE_WRITEBACK
(the default configuration).

The patch also avoids to select simultaneously 2 configurations.

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2020-05-01 11:34:01 -04:00
Franck LENORMAND
242d1cd69b imx8: Configure SNVS
Add a module to configure the tamper and secure violation of
the SNVS using the SCU API.

The module also adds some commands:
 - snvs_cfg: Configure the SNVS HP and LP registers
 - snvs_dgo_cfg: Configure the SNVS DGO bloc if present (8QXP)
 - tamper_pin_cfg: Change the configuration of the tamper pins
 - snvs_clear_status: Allow to write to LPSR and LPTDSR to clear
   status bits

Reviewed-by: Fabio Estevam <festevam@gmail.com>
Signed-off-by: Franck LENORMAND <franck.lenormand@nxp.com>
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2020-05-01 13:46:22 +02:00
Ye Li
73d769d8af imx8: Update SCFW API to version 1.5
Sync the latest SCFW API with below commit
6dcd0242ae7a53ac ("SCF-105: Revert accidental change") to add
interfaces for PM resource reset and read/write SNVS security
violation and tamper DGO registers.

Reviewed-by: Fabio Estevam <festevam@gmail.com>
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2020-05-01 13:46:22 +02:00
Breno Lima
f959594db2 imx8: scu api: Add support for SECO manufacturing protection APIs
SECO provides APIs to support CAAM manufacturing protection:

- sc_seco_get_mp_key()
- sc_seco_get_mp_sign()
- sc_seco_update_mpmr()

Add SCFW APIs support.

Reviewed-by: Fabio Estevam <festevam@gmail.com>
Signed-off-by: Breno Lima <breno.lima@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2020-05-01 13:46:22 +02:00
Ye Li
1c97fcda7f imx8mm: clock: fix fracpll decode issue
The fracpll decoding is using the bit definitions for int pll. Most of
them are same, but the CLKE bit is different. Fix the wrong CLKE_MASK
for fracpll and correct all bit definitions in fracpll decoding.

Reviewed-by: Fabio Estevam <festevam@gmail.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2020-05-01 13:46:22 +02:00
Peng Fan
712a341c76 imx8mq: Set ARM core clock directly from ARM PLL
For ARM core clock, there are two input branches, and can select via mux:
one from ARM PLL directly, second from CCM A53 clock root.

Currently we are using second branch. But IC confirmed the CCM A53 root
signoff timing is 1Ghz, so we should switch to input from ARM PLL directly.

This patch fixes the CORE SEL slice configuration and switch ARM clock
to ARM PLL.

Reviewed-by: Fabio Estevam <festevam@gmail.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2020-05-01 13:46:21 +02:00
Peng Fan
6b87b3f4dc imx8m: update clock root and fix core_sel
Update clock root table to let it be easy to configure clock at
very early stage. Also the core_sel mux parent should be A53 CLK
root and ARM PLL.

Reviewed-by: Fabio Estevam <festevam@gmail.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2020-05-01 13:46:21 +02:00
Peng Fan
9b4e197d4b imx: update is_imx6ull to include i.MX6ULZ
Update is_imx6ull helper to include i.MX6ULZ SoC. i.MX6ULZ could
share same macro, then we no need to add is_imx6ulz in various drivers.

Reviewed-by: Fabio Estevam <festevam@gmail.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2020-05-01 13:46:21 +02:00
Peng Fan
c915403218 imx: imx8m: add i.MX8MN variants support
Add i.MX8MN variants support

Reviewed-by: Fabio Estevam <festevam@gmail.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2020-05-01 13:46:21 +02:00
Peng Fan
cb1a1de6a0 imx: imx8m: add i.MX8MQ Dual and QuadLite support
Add i.MX8MQ Dual and QuadLite variants.

Reviewed-by: Fabio Estevam <festevam@gmail.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2020-05-01 13:46:21 +02:00
Peng Fan
499c94975e imx: fix cpu_type helper
i.MX8MP use 0x182 as its ID, so 0xff is not valid to get the cpu type,
extend it to 0x1ff.

Reviewed-by: Fabio Estevam <festevam@gmail.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2020-05-01 13:46:21 +02:00
Tom Rini
b9da77f195 Merge https://gitlab.denx.de/u-boot/custodians/u-boot-fsl-qoriq
- Add DM_ETH support for DPAA1, DPAA2 based RDB platforms: ls1046ardb,
  ls1043ardb, lx2160ardb, ls2088ardb, ls1088ardb.
- Add GICv3 support for ls1028a, ls2088a, ls1088a.
- Add lpuart support on ls1028aqds.
- Few bug fixes and updates on ls2088a, ls1012a, ls1046a, ls1021a based
  platforms.
2020-04-30 10:06:54 -04:00
Tom Rini
306881a0bf Convert CONFIG_PHYLIB et al to Kconfig
This converts the following to Kconfig:
   CONFIG_PHYLIB
   CONFIG_BITBANGMII
   CONFIG_MV88E6352_SWITCH
   CONFIG_MV88E61XX_SWITCH
   CONFIG_PHYLIB_10G
   CONFIG_PHY_AQUANTIA
   CONFIG_PHY_ATHEROS
   CONFIG_PHY_BROADCOM
   CONFIG_PHY_CORTINA
   CONFIG_PHY_DAVICOM
   CONFIG_PHY_ET1011C
   CONFIG_PHY_LXT
   CONFIG_PHY_MARVELL
   CONFIG_PHY_MICREL
   CONFIG_PHY_NATSEMI
   CONFIG_PHY_REALTEK
   CONFIG_RTL8211X_PHY_FORCE_MASTER
   CONFIG_PHY_SMSC
   CONFIG_PHY_TERANETICS
   CONFIG_PHY_TI
   CONFIG_PHY_VITESSE
   CONFIG_PHY_XILINX

Signed-off-by: Tom Rini <trini@konsulko.com>
2020-04-28 15:57:58 -04:00
Hou Zhiqiang
f40b120e93 fsl-layerscape: Move GIC RD tables init to soc.c
Move GIC redistributor tables initialization to CPU setup function.

This patch introduces a GIC redistributor tables init function, and
moves the function of reserving memory for GIC redistributor tables
to soc.c and adds a argument for the memory size to reserve, BTW
rename the function so that it is more readable.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Wasim Khan <wasim.khan@nxp.com>
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-04-28 17:46:46 +05:30
Amit Singh Tomar
8b520ac153 clk: actions: Add common clock driver
This patch converts S900 clock driver to something common that can
be used for other SoCs, for instance S700(few of clk registers are same).

Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Amit Singh Tomar <amittomer25@gmail.com>
2020-04-24 16:40:09 -04:00
Ovidiu Panait
6184858b85 arm: asm/cache.c: Introduce arm_reserve_mmu
As a preparation for turning reserve_mmu into an arch-specific variant,
introduce arm_reserve_mmu on ARM. It implements the default routine for
reserving memory for MMU TLB and needs to be weakly defined in order to allow
for machines to override it.

Without this decoupling, after introducing arch_reserve_mmu, there would be two
weak definitions for it, one in common/board_f.c and one in
arch/arm/lib/cache.c.

Signed-off-by: Ovidiu Panait <ovpanait@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2020-04-24 15:17:14 -04:00
Tom Rini
bdcb29960e Merge https://gitlab.denx.de/u-boot/custodians/u-boot-fsl-qoriq
- Backplane support and bug fixes
2020-04-21 15:20:42 -04:00
Tom Rini
e4837da782 - enable DM_RNG on meson boards
- fix SMBIOS info on Odroid-C2
 - Fix video output on GXBB/GXL/GXM boards
 - add USB gadget support for GXL/GXM boards
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Merge tag 'u-boot-amlogic-20200420' of https://gitlab.denx.de/u-boot/custodians/u-boot-amlogic

- enable DM_RNG on meson boards
- fix SMBIOS info on Odroid-C2
- Fix video output on GXBB/GXL/GXM boards
- add USB gadget support for GXL/GXM boards
2020-04-20 13:44:27 -04:00
Neil Armstrong
838c0af9d2 phy: meson-gxl-usb: add set_mode call to force switch to peripheral mode
Add set_mode function in the Amlogic GXL PHYs that will be called by
the arch code to switch PHYs from/to gadget mode.

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2020-04-20 14:19:10 +02:00
Yinbo Zhu
316fc6ff76 armv8: ls1028a: define esdhc_status_fixup
This patch is to define esdhc_status_fixup function for ls1028a to disable
SDHC1/SDHC2 status in device tree node if not selected.

Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com>
Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com>
Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-04-20 13:35:11 +05:30
Giulio Benetti
aa045701c2 video: mxsfb: add support for i.MXRT
Add support for i.MXRT by adding CONFIG_IMXRT in register structure and
adding .compatible = "fsl,imxrt-lcdif".

Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
Reviewed-by: Anatolij Gustschin <agust@denx.de>
2020-04-18 12:54:43 +02:00
Bernhard Messerklinger
7794d889d3 arm: imx6: configure NoC on i.MX6DQP
The i.MX6DP and i.MX6QP incorporate NoC interconnect logic
which needs to be configured in order to use external DDR memory.

This patch enables the SPL to configure the necessary registers
in accordance with the NXP engineering bulletin EB828.

Co-developed-by: Filip Brozović <fbrozovic@gmail.com>

Signed-off-by: Bernhard Messerklinger <bernhard.messerklinger@br-automation.com>
Signed-off-by: Filip Brozovic <fbrozovic@gmail.com>
2020-04-17 18:56:19 +02:00
Tom Rini
60f1cc529c Merge branch 'master' of https://gitlab.denx.de/u-boot/custodians/u-boot-tegra
- Add support for Jetson Nano, plus miscellaneous other fixes found
  during Nano bringup.
- Add Igor's update_uboot wrapper patches.
2020-04-03 16:05:46 -04:00
Tom Warren
a482f32992 mmc: t210: Fix 'bad' SD-card clock when doing 400KHz card detect
According to the HW team, for some reason the normal clock select code
picks what appears to be a perfectly valid 375KHz SD card clock, based
on the CAR clock source and SDMMC1 controller register settings (CAR =
408MHz PLLP0 divided by 68 for 6MHz, then a SD Clock Control register
divisor of 16 = 375KHz). But the resulting SD card clock, as measured by
the HW team, is 700KHz, which is out-of-spec. So the WAR is to use the
values given in the TRM PLLP table to generate a 400KHz SD-clock (CAR
clock of 24.7MHz, SD Clock Control divisor of 62) only for SDMMC1 on
T210 when the requested clock is <= 400KHz. Note that as far as I can
tell, the other requests for clocks in the Tegra MMC driver result in
valid SD clocks.

Signed-off-by: Tom Warren <twarren@nvidia.com>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
2020-04-02 14:30:01 -07:00
Tom Warren
5e965e8140 mmc: t210: Add autocal and tap/trim updates for SDMMC1/3
As per the T210 TRM, when running at 3.3v, the SDMMC1 tap/trim and
autocal values need to be set to condition the signals correctly before
talking to the SD-card. This is the same as what's being done in CBoot,
but it gets reset when the SDMMC1 HW is soft-reset during SD driver
init, so needs to be repeated here. Also set autocal and tap/trim for
SDMMC3, although no T210 boards use it for SD-card at this time.

Signed-off-by: Tom Warren <twarren@nvidia.com>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
2020-04-02 14:30:01 -07:00
JC Kuo
d491dc09e4 t210: do not enable PLLE and UPHY PLL HW PWRSEQ
This commit removes the programming sequence that enables PLLE and UPHY
PLL hardware power sequencers. Per TRM, boot software should enable PLLE
and UPHY PLLs in software controlled power-on state and should power
down PLL before jumping into kernel or the next stage boot software.

Adds call to board_cleanup_before_linux to facilitate this.

Signed-off-by: JC Kuo <jckuo@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Acked-by: Stephen Warren <swarren@nvidia.com>
2020-04-02 14:30:01 -07:00
Jagan Teki
e67243f1a3 video: rockchip: Fix vop modes for rk3399
VOP display endpoint pipeline configuration differs
between rk3288 vs rk3399.

These VOP pipeline configuration depends on how the
different display interfaces connected in sequence to
IN and OUT ports like for,

RK3288:

vopb_out: port {
	#address-cells = <1>;
	#size-cells = <0>;
	vopb_out_edp: endpoint@0 {
		reg = <0>;
		remote-endpoint = <&edp_in_vopb>;
	};
	vopb_out_hdmi: endpoint@1 {
		reg = <1>;
                remote-endpoint = <&hdmi_in_vopb>;
        };
        vopb_out_lvds: endpoint@2 {
                reg = <2>;
                remote-endpoint = <&lvds_in_vopb>;
        };
        vopb_out_mipi: endpoint@3 {
                reg = <3>;
                remote-endpoint = <&mipi_in_vopb>;
        };
};

RK3399:

vopb_out: port {
         #address-cells = <1>;
         #size-cells = <0>;
         vopb_out_edp: endpoint@0 {
                reg = <0>;
                remote-endpoint = <&edp_in_vopb>;
         };
         vopb_out_mipi: endpoint@1 {
                reg = <1>;
                remote-endpoint = <&mipi_in_vopb>;
         };
         vopb_out_hdmi: endpoint@2 {
                reg = <2>;
                remote-endpoint = <&hdmi_in_vopb>;
         };
         vopb_out_mipi1: endpoint@3 {
                reg = <3>;
                remote-endpoint = <&mipi1_in_vopb>;
         };
         vopb_out_dp: endpoint@4 {
                reg = <4>;
                remote-endpoint = <&dp_in_vopb>;
         };
};

here, HDMI interface has endpoint 1 in rk3288 and 2 in rk3399.

The rockchip vop driver often depends on this determined endpoint
number and stored in vop_mode. So based on this vop_mode the bpp
and pin polarity would configure on detected display interface.

Since, the existing driver using rk3288 vop mode settings enabling
the same will result wrong display interface configuration for rk3399.

Add the patch for fixing these vop modes for rk3399.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Tested-by: Peter Robinson <pbrobinson@gmail.com>
2020-04-02 15:47:35 +02:00
Biwen Li
bb1165f900 dm: arm64: ls1046a: add i2c DM support
This supports i2c DM and enables CONFIG_DM_I2C
for SoC LS1046A

Signed-off-by: Biwen Li <biwen.li@nxp.com>
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-03-30 08:12:13 +05:30
Biwen Li
fefac937fb dm: arm64: ls1043a: add i2c DM support
This supports i2c DM and enables CONFIG_DM_I2C
for SoC LS1043A

Signed-off-by: Biwen Li <biwen.li@nxp.com>
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-03-30 08:12:13 +05:30
Masahiro Yamada
9d86b89c59 dma-mapping: move dma_map_(un)single() to <linux/dma-mapping.h>
The implementation of dma_map_single() and dma_unmap_single() is
exactly the same for all the architectures that support them.

Factor them out to <linux/dma-mapping.h>, and make all drivers to
include <linux/dma-mapping.h> instead of <asm/dma-mapping.h>.

If we need to differentiate them for some architectures, we can
move the generic definitions to <asm-generic/dma-mapping.h>.

Add some comments to the helpers. The concept is quite similar to
the DMA-API of Linux kernel. Drivers are agnostic about what is
going on behind the scene. Just call dma_map_single() before the
DMA, and dma_unmap_single() after it.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2020-02-19 21:27:30 +08:00
Masahiro Yamada
950c596867 dma-mapping: fix the prototype of dma_unmap_single()
dma_unmap_single() takes the dma address, not virtual address.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2020-02-19 21:27:30 +08:00
Masahiro Yamada
c22c0dbd7d dma-mapping: fix the prototype of dma_map_single()
Make dma_map_single() return the dma address, and remove the
pointless volatile.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2020-02-19 21:27:30 +08:00
Jason Li
f267f84b93 gpio: do not include <asm/arch/gpio.h> for Cortina CAxxxx SoCs
The Cortina CAxxxx GPIO driver maintains DM_GPIO support
across different CPU ISA in the CAxxxx Soc Family; Not just ARM.
Therefore, it is not desirable to split out and maintain separete
gpio header file for each CPU architecture.

Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Jason Li <jason.li@cortina-access.com>
Signed-off-by: Alex Nemirovsky <alex.nemirovsky@cortina-access.com>
2020-02-07 14:01:21 -05:00