Commit graph

68258 commits

Author SHA1 Message Date
Sean Anderson
c41045411b Revert "riscv: Clear pending interrupts before enabling IPIs"
Clearing MIP.MSIP is not guaranteed to do anything by the spec. In
addition, most existing RISC-V hardware does nothing when this bit is set.

The following commits "riscv: Use a valid bit to ignore already-pending
IPIs" and "riscv: Clear pending IPIs on initialization" should implement
the original intent of the reverted commit in a more robust manner.

This reverts commit 9472630337.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Rick Chen <rick@andestech.com>
2020-09-30 08:54:52 +08:00
Sean Anderson
422c3c5edf riscv: Update SiFive device tree for new CLINT driver
We currently do this in a u-boot specific dts, but hopefully we can get
these bindings added in Linux in the future.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Pragnesh Patel <pragnesh.patel@openfive.com>
Reviewed-by: Bin Meng <bin.meng@windriver.com>
2020-09-30 08:54:46 +08:00
Sean Anderson
e89e8983dc riscv: Update Kendryte device tree for new CLINT driver
The interrupt controller property is removed from the clint binding because
the clint is not an interrupt-controller. That is, no other devices have an
interrupt which is controlled by the clint.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Bin Meng <bin.meng@windriver.com>
2020-09-30 08:54:46 +08:00
Sean Anderson
a952c3a454 riscv: clk: Add CLINT clock to kendryte clock driver
Another "virtual" clock (in the sense that it isn't configurable). This
could possibly be done as a clock in the device tree, but I think this is a
bit cleaner.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
2020-09-30 08:54:46 +08:00
Sean Anderson
e5ca9a7523 riscv: Rework Sifive CLINT as UCLASS_TIMER driver
This converts the clint driver from the riscv-specific interface to be a
DM-based UCLASS_TIMER driver. In addition, the SiFive DDR driver previously
implicitly depended on the CLINT to select REGMAP.

Unlike Andes's PLMT/PLIC (which AFAIK never have anything pass it a dtb),
the SiFive CLINT is part of the device tree passed in by qemu. This device
tree doesn't have a clocks or clock-frequency property on clint, so we need
to fall back on the timebase-frequency property. Perhaps in the future we
can get a clock-frequency property added to the qemu dtb.

Unlike with the Andes PLMT, the Sifive CLINT is also an IPI controller.
RISCV_SYSCON_CLINT is retained for this purpose.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Pragnesh Patel <pragnesh.patel@openfive.com>
2020-09-30 08:54:46 +08:00
Sean Anderson
15943bb558 riscv: Clean up initialization in Andes PLIC
This merges the PLIC initialization code from two functions into one.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Bin Meng <bin.meng@windriver.com>
2020-09-30 08:54:46 +08:00
Sean Anderson
e86463f8e3 riscv: Rework Andes PLMT as a UCLASS_TIMER driver
This converts the PLMT driver from the riscv-specific timer interface to be
a DM-based UCLASS_TIMER driver.

The clock-frequency/clocks properties are preferred over timebase-frequency
for two reasons. First, properties which affect a device should be located
near its binding in the device tree. Using timebase-frequency only really
makes sense when the cpu itself is the timer device. This is the case when
we read the time from a CSR, but not when there is a separate device.
Second, it lets the device use the clock subsystem which adds flexibility.
If the device is configured for a different clock speed, the timer can
adjust itself.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Rick Chen <rick@andestech.com>
2020-09-30 08:54:45 +08:00
Sean Anderson
7616e3687e timer: Add a test for timer_timebase_fallback
To test this function, sandbox CPU must set cpu_platdata.timebase_freq on
bind. It also needs to expose a method to set the current cpu. I also make
some most members of cpu_sandbox_ops static.

On the timer side, the device tree property
sandbox,timebase-frequency-fallback controls whether sandbox_timer_probe
falls back to time_timebase_fallback or to SANDBOX_TIMER_RATE.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2020-09-30 08:54:45 +08:00
Sean Anderson
3576121687 timer: Add helper for drivers using timebase fallback
This function is designed to be used when a timer used to be initialized by
the cpu (e.g. RISC-V timers), but now is initialized by dm_timer_init. In
such a case, the timer may prefer to use the clocks and clock-frequency
properties, but should be able to fall back on using the cpu's
timebase-frequency.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Rick Chen <rick@andestech.com>
2020-09-30 08:54:45 +08:00
Sean Anderson
c33efafaf9 riscv: Rework riscv timer driver to only support S-mode
The riscv-timer driver currently serves as a shim for several riscv timer
drivers. This is not too desirable because it bypasses the usual timer
selection via the driver model. There is no easy way to specify an
alternate timing driver, or have the tick rate depend on the cpu's
configured frequency. The timer drivers also do not have device structs,
and so have to rely on storing parameters in gd_t. Lastly, there is no
initialization call, so driver init is done in the same function which
reads the time. This can result in confusing error messages. To a user, it
looks like the driver failed when trying to read the time, whereas it may
have failed while initializing.

This patch removes the shim functionality from the riscv-timer driver, and
has it instead implement the former rdtime.c timer driver. This is because
existing u-boot users who pass in a device tree (e.g. qemu) do not create a
timer device for S-mode u-boot. The existing behavior of creating the
riscv-timer device in the riscv cpu driver must be kept. The actual reading
of the CSRs has been redone in the style of Linux's get_cycles64.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Rick Chen <rick@andestech.com>
2020-09-30 08:54:45 +08:00
Bin Meng
9981a8009e ram: sifive: Remove regmap dependency
The usage of regmap API in the SiFive RAM driver is not correct.
The reg address should be obtained via dev_read_addr_index() API.

Signed-off-by: Bin Meng <bin.meng@windriver.com>
2020-09-30 08:54:38 +08:00
Bin Meng
f8c9660bfe ram: sifive: Check return value on clk_enable()
The return value should be checked otherwise it's useless to
assign the return value to 'ret'.

Signed-off-by: Bin Meng <bin.meng@windriver.com>
2020-09-30 08:54:38 +08:00
Heinrich Schuchardt
08bff30d5d doc/sipeed/maix: describe RESET and BOOT button
In the boot flow description add the RESET and BOOT button as well as the
function of the DTR and RTS lines of the serial interface.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2020-09-30 08:54:31 +08:00
Heinrich Schuchardt
d53a95ba5e doc: correct kflash settings for Maix One Dock
The correct kflash parameter value for the Maix One Dock is "dan".

See:
https://github.com/sipeed/platform-kendryte210/blob/master/boards/sipeed-maix-one-dock.json#L22

Fixes: 137dc153fd ("doc: riscv: Update documentation for Sipeed MAIX boards")
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2020-09-30 08:54:25 +08:00
Pragnesh Patel
c5a7e5b3dd cmd: irq: disable CMD_IRQ for riscv arch
For RISC-V arch, no need for CMD_IRQ so disable the same.

Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Rick Chen <rick@andestech.com>
Reviewed-by: Bin Meng <bin.meng@windriver.com>
2020-09-30 08:54:03 +08:00
Tom Rini
0ac83d080a Merge branch 'next' of https://gitlab.denx.de/u-boot/custodians/u-boot-x86 into next
- Enhance the 'zboot' command to be more like 'bootm' with sub-commands
- The last series of ACPI core changes for programmatic generation of
  ACPI tables
- Add all required ACPI tables for ApolloLake and enable ACPIGEN on
  Chromebook Coral
- A feature minor enhancements to the 'hob' command
- Intel edison: Support for writing an xFSTK image via binman
2020-09-25 09:04:01 -04:00
Simon Glass
8c180d669a x86: edison: Add documentation for using am xFSTK image
Add a description of how to flash Edison using the xFSTK tool.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
2020-09-25 11:27:29 +08:00
Simon Glass
2e3b883014 x86: edison: Generate an image suitable for xFSTK
It is useful to be able to flash Edison directly without relying on the
installed U-Boot being functional.

Add a binman image for this. It includes a 'OSIP' header (which happens to
look like an MBR / (Master-Boot Record), U-Boot binary and an environment.

I am not able to find a specification for OSIP.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
2020-09-25 11:27:28 +08:00
Simon Glass
fb91d5675e binman: Support adding a U-Boot environment
In some cases it is useful to include a U-Boot environment region in an
image. This allows the board to start up with an environment ready to go.

Add a new entry type for this. The input is a text file containing the
environment entries, one per line, in the format:

   var=value

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
2020-09-25 11:27:28 +08:00
Simon Glass
204aa78e04 binman: Show an error when a file is missing
The recent support for missing external binaries does not show an error
message when a file is genuinely missing (i.e. it is missing but not
marked as 'external'). This means that when -m is passed to binman, it
will never report a missing file.

Fix this and add a test.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
2020-09-25 11:27:28 +08:00
Simon Glass
2463f165a3 x86: Use multiple images
We already use binman's 'multiple-images' feature with Chrome OS and we
want to use it for Edison. There is no real down-side.

Adjust x86 to always use multiple-images.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
2020-09-25 11:27:28 +08:00
Simon Glass
308b1a960e x86: video: Show information about each video device
At present the 'bdinfo' command shows the framebuffer address, but not the
address of the copy framebuffer, if present. Add support for this.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-09-25 11:27:27 +08:00
Simon Glass
29d2d64ed5 x86: Add support for more than 8 MTRRs
At present the mtrr command only support 8 MTRRs. Some SoCs have more than
that. Update the implementation to support up to 10. Read the number of
MTRRs dynamically instead.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-09-25 11:27:27 +08:00
Simon Glass
51af144eb7 x86: Allow showing details about a HOB entry
Some HOBs include information that can be decoded. Add a -v option to the
hob command, to allow this to be displayed. Add the ability to decode a
resource descriptor.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-09-25 11:27:27 +08:00
Simon Glass
10536ceae9 x86: hob: Try to show a name instead of a GUID
GUIDs are one of the seven evils of the computer world. They obfuscate the
meaning and require people to look up long hex strings to decode it.

Luckily only a miniscule fraction of the 10^38 possible GUIDs are in use.

Add a way to decode the GUIDs known to U-Boot. Add a few more to the list
for good measure.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-09-25 11:27:27 +08:00
Simon Glass
d11544dfa9 x86: hob: Add way to show a single hob entry
The 'hob' command currently lists all HOB entries. Add way to list a
single entry, by index.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-09-25 11:27:26 +08:00
Simon Glass
9c6aaf1347 acpi: Use I2cSerialBusV2() instead of I2cSerialBus()
Use the correct name of the ACPI structure being created.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-09-25 11:27:26 +08:00
Simon Glass
1e4073b855 acpi: Add more documentation for struct acpi_gpio
Add some documentation provided by Andy Shevchenko to describe how to
use struct acpi_gpio.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-09-25 11:27:26 +08:00
Simon Glass
49f5141ed3 x86: coral: Update config and device tree for ACPI
Enable new features and provide require device-tree config so that U-Boot
produces the correct ACPI tables on Coral.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-09-25 11:27:25 +08:00
Simon Glass
ee3cb7c648 x86: Move include of bitops out of ACPI region
At present linux/bitops.h is included in ACPI code. This is not needed and
can cause a problem in fls64.h since BITS_PER_LONG is not defined. Move
the #include into the part not used by ACPI.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-09-25 11:27:25 +08:00
Simon Glass
70c202c480 x86: Add a way to add to the e820 memory table
Some boards want to reserve extra regions of memory. Add a 'chosen'
property to support this.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-09-25 11:27:25 +08:00
Simon Glass
2a2ebf880c acpi: Use defines for field lengths
A few fields have an open-coded length. Use the defines for this purpose
instead.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-09-25 11:27:25 +08:00
Simon Glass
cc5e02fcbf x86: fsp: Show FSP-S or FSP-M address in fsp_get_header()
At present this function only supports FSP-M but it is also used to read
FSP-S, in which case FSP-M may be zero. Add support for showing whichever
address is present in the FSP binary.

Also change the debug() statements to log_debug() while here.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-09-25 11:27:24 +08:00
Simon Glass
4558d3294d x86: fsp: Add more debugging for silicon init
If locating the FSP header hangs for whatever reason it is useful to see
where it got stuck. Add a debug print. Also show the address of the FSP-S
entry point as a sanity check.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-09-25 11:27:24 +08:00
Simon Glass
96bf9be89e x86: apl: Check low-level init in FSP-S pre-init
If U-Boot is not running FSP-S it should not do the pre-init either. Add a
condition to handle this.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-09-25 11:27:24 +08:00
Simon Glass
a30898f2a1 x86: coral: Add audio descriptor files
Add files describing the various audio configurations supported on coral.
These are passed to Linux in the ACPI tables.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-09-25 11:27:24 +08:00
Simon Glass
2da4b6998e x86: acpi: Set the log category for x86 table generation
This file doesn't currently have a log category. Add one so that items
are logged correctly.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-09-25 11:27:23 +08:00
Simon Glass
77bb1c69df acpi: tpm: Add a TPM1 table
This provides information about a v1 TPM in the system. Generate this
table if the TPM is present.

Add a required new bloblist type and correct the header order of one
header file.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-09-25 11:27:23 +08:00
Simon Glass
9179c3571c acpi: tpm: Add a TPM2 table
This provides information about a v2 TPM in the system. Generate this
table if the TPM is present.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-09-25 11:27:23 +08:00
Simon Glass
4ff3591988 x86: Correct handling of MADT table CPUs
At present if hyperthreading is disabled the CPU numbering is not
sequential. Fix this.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-09-25 11:27:23 +08:00
Simon Glass
26c3d3d7d5 x86: Add a header guard to asm/acpi_table.h
This file cannot currently be included in ASL files. Add a header guard
to permit this.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-09-25 11:27:22 +08:00
Simon Glass
3a25073a40 x86: Correct the assembly guard in e820.h
This is currently in the wrong place, so including the file in the device
tree fails. Fix it.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-09-25 11:27:22 +08:00
Simon Glass
7c73cea442 x86: Notify the FSP of the 'end firmware' event
Send this notification when U-Boot is about to boot into Linux, as
requested by the FSP.

Currently this causes a crash with the APL FSP, so leave it disabled for
now.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-09-25 11:27:22 +08:00
Simon Glass
f31b02c84e x86: Sort the MTRR table
At present the MTRR registers are programmed with the list the U-Boot
builds up in the same order. In some cases this list may be out of order.
It looks better in Linux to have the registers in order, so sort them,

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-09-25 11:27:22 +08:00
Simon Glass
aec7c1c565 x86: cpu: Report address width from cpu_get_info()
Add support for this new field in the common code used by most x86 CPU
drivers.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-09-25 11:27:21 +08:00
Simon Glass
c90b302d5f x86: fsp: Update the FSP API with the end-firmware method
This new method is intended to be called when UEFI shuts down the 'boot
services', i.e. any lingering code in the boot loader that might be used
by the OS.

Add a definition for this new method and update the comments a little.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-09-25 11:27:21 +08:00
Simon Glass
eaac971736 tpm: cr50: Add ACPI support
Generate ACPI information for this device so that Linux can use it
correctly.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-09-25 11:27:21 +08:00
Simon Glass
ca60199fee x86: apl: Drop unnecessary code in PMC driver
We don't have CONFIG_PCI in TPL but it is present in SPL, etc. So this
code is not needed. Drop it, and fix a code-style nit just above.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-09-25 11:27:20 +08:00
Simon Glass
ea78675b96 x86: apl: Generate ACPI table for LPC
Add an ACPI table for the LPC on Apollo Lake.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-09-25 11:27:20 +08:00
Simon Glass
60c0231078 x86: apl: Generate CPU tables
Add ACPI generation to the APL CPU driver.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-09-25 11:27:20 +08:00